JPH03104252A - Manufacture of tape carrier - Google Patents

Manufacture of tape carrier

Info

Publication number
JPH03104252A
JPH03104252A JP24274789A JP24274789A JPH03104252A JP H03104252 A JPH03104252 A JP H03104252A JP 24274789 A JP24274789 A JP 24274789A JP 24274789 A JP24274789 A JP 24274789A JP H03104252 A JPH03104252 A JP H03104252A
Authority
JP
Japan
Prior art keywords
carrier tape
defective
round hole
semiconductor element
carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24274789A
Other languages
Japanese (ja)
Inventor
Kazunori Sakurai
和徳 桜井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP24274789A priority Critical patent/JPH03104252A/en
Publication of JPH03104252A publication Critical patent/JPH03104252A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the yield of production and reduce production cost by indicating acceptance test results of carrier tape to an alignment mark and mounting a semiconductor element only with a good quality of carrier tape. CONSTITUTION:An inner lead bonder takes in an image of binary alignment marks, calculates the area of a round hole to obtain a gravity coordinates of the round hole, and then calculates the deviation against the gravity coordinates 8 of the round hole, moves the position of a carrier tape or a semiconductor element, aligns an inner lead with an electrode of the semiconductor element, and carriers out bonding operation. The carrier tape where the round hole of the alignment mark is expanded because it is decided as defective by a carrier tape tester results in a larger hole compared with the round hole of an alignment mark formed on a non defective carrier tape. Therefore, it is possible to bond a semiconductor element only with a non defective carrier tape during alignment by providing a boundary value of non defective and defective articles to the area of the round hole, thereby attaining enhanced yield and cost reduction of carrier tape.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、テープキャリアを製造する際に良品のキャリ
アテープにのみ半導体素子を実装する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for mounting semiconductor elements only on good quality carrier tapes when manufacturing tape carriers.

[従来の技術] 従来、キャリアテープに半導体素子を実装する場合、受
け入れられたキャリアテープにはすべて半導体素子が実
装されていた。
[Prior Art] Conventionally, when semiconductor elements were mounted on a carrier tape, semiconductor elements were mounted on all accepted carrier tapes.

通常、キャリアテープは製造工場にて出荷検査が行われ
ているが、それが抜取り検査であった場合は不良が混入
している可能性があり、また全数検査の場合でも検査後
の取扱や搬送時にキャリアテープのインナーリードを曲
げる等の不良が発生していた。
Normally, carrier tapes are inspected at the manufacturing factory before shipping, but if it is a sampling inspection, there is a possibility that defects may be mixed in, and even in the case of a 100% inspection, handling and transportation after inspection may be difficult. Occasionally, defects such as bending of the inner lead of the carrier tape occurred.

このようなキャリアテープが半導体素子のボンディング
工程に流れた場合、インナーリードボンダーでは第2図
に示すようなアライメントマーク1を認識して半導体素
子の電極とインナーリード5を位置合わせしてボンディ
ングするか、インナーリード5の一部を認識してボンデ
ィングするかのどちらかであるため、認識しないインナ
ーリード部分や配線パターンに不良が発生していても半
導体素子をボンディングしてしまっていた.不良のキャ
リアテープにポンディングされた半導体素子は最終的に
は不良のテープキャリアと判定されるが、テスティング
工程までは良品としてあつかわれる。
When such a carrier tape is sent to the bonding process of a semiconductor element, the inner lead bonder recognizes the alignment mark 1 as shown in Fig. 2 and aligns the electrode of the semiconductor element and the inner lead 5 for bonding. Since either part of the inner lead 5 is recognized and bonded, the semiconductor element is bonded even if there is a defect in the unrecognized part of the inner lead or in the wiring pattern. Although a semiconductor device bonded to a defective carrier tape is ultimately determined to be a defective tape carrier, it is treated as a non-defective product until the testing process.

[発明が解決しようとする課題] しかし、前述の従来技術では不良のキャリアデーブに良
品の半導体素子を実装してしまうため、不留りの低下を
招く。また、不良のキャリアテープにボンディングされ
た半導体素子は樹脂封止や半田メッキ、テスティング等
の後の工程も流れるため、無駄な工数をかけることとな
りコストアップにつながった。
[Problems to be Solved by the Invention] However, in the above-mentioned conventional technology, a good semiconductor element is mounted on a defective carrier wave, resulting in a decrease in retention. In addition, semiconductor elements bonded to defective carrier tapes undergo subsequent processes such as resin encapsulation, solder plating, and testing, resulting in wasted man-hours and increased costs.

そこで、本発明の目的とするところは、良品のキャリア
テープにのみ半導体素子をボンディングし、後の工程で
は不良のキャリアテープは無視してテープキャリアを製
造することにより、不留りの向上とコストダウンをはか
ることにある。
Therefore, an object of the present invention is to improve retention and reduce costs by bonding semiconductor elements only to good carrier tapes and ignoring defective carrier tapes in the subsequent process to manufacture tape carriers. The purpose is to measure the down.

[課題を解決するための手段] 本発明のテープキャリアの製造方法は、キャリアテープ
を検査し、後に半導体素子を実装してなるテープキャリ
アの製造方法において、半導体素子をボンディングする
際に用いるアライメントマークに、キャリアテープの検
査の合否判定結果を示し、良品のキャリアテープにのみ
半導体素子を実装することを特徴とする。
[Means for Solving the Problems] A method for manufacturing a tape carrier of the present invention is a method for manufacturing a tape carrier in which a carrier tape is inspected and a semiconductor element is later mounted thereon. The present invention is characterized in that it shows the pass/fail determination results of carrier tape inspection, and that semiconductor elements are mounted only on non-defective carrier tapes.

[実施例] 以下実施例により、本発明の詳細を示す。[Example] The details of the present invention will be shown below with reference to Examples.

第1図(a)は本発明の実施例に用いるキャリアテープ
に形成されたアライメントマークの拡大図である。また
、(b)図は不良のキャリアテープのアライメントマー
クの拡大図である。キャリアテープ検査機によって不良
と判定されたキャリアテープは、丸穴3が大きく広げら
れる。丸穴を大きく広げるためには、針を通すか、パン
チングによる方法をとる。
FIG. 1(a) is an enlarged view of an alignment mark formed on a carrier tape used in an embodiment of the present invention. Moreover, FIG. 2B is an enlarged view of an alignment mark on a defective carrier tape. In carrier tapes that are determined to be defective by the carrier tape inspection machine, the round holes 3 are enlarged. To enlarge the round hole, either pass a needle through it or use punching.

インナーリードボンダーは、このアライメントマークを
2値化して画像を取り込み、九穴3の面積を計算して九
大の重心座標を求める。しかる後、第3図に示す半導体
素子6の電極7とキャリアテープ2のインナーリード5
との位置が合うように予め設定されていた九大の重心座
標8とのズレを計算して、キャリアテープかあるいは半
導体素子の位置を移動してインナーリードと半導体素子
の電極との位置合わせをしてボンディングを行う。
The inner lead bonder binarizes this alignment mark, captures the image, calculates the area of the nine holes 3, and obtains the coordinates of the center of gravity of the nine holes. After that, the electrodes 7 of the semiconductor element 6 and the inner leads 5 of the carrier tape 2 shown in FIG.
Calculate the deviation from Kyushu University's center of gravity coordinate 8, which was set in advance, so that the inner lead and the electrode of the semiconductor element are aligned by moving the carrier tape or the position of the semiconductor element. and perform bonding.

前記キャリアテープ検査機によって不良と判定されてア
ライメントマークの九六が広げられたキャリアテープは
、前記インナーリードボンダーでアライメントを行う際
に計算される丸穴の面積が良品のキャリアテープに形成
されているアライメントマークの九大の面積と比較して
大きい結果となる。そこで、丸穴の面積に良品と不良品
の境界値を設けて記憶しておくことにより、アライメン
トの際に不良のキャリアテープは無視して良品のキャリ
アテープにのみ半導体素子をボンディングすることがで
きる。
A carrier tape that is determined to be defective by the carrier tape inspection machine and whose alignment mark has been expanded has a round hole area that is calculated when alignment is performed by the inner lead bonder and is formed on a non-defective carrier tape. This results in a large result compared to the area of the nine alignment marks. Therefore, by setting and storing a boundary value between good and defective products in the area of the round hole, it is possible to ignore defective carrier tapes during alignment and bond semiconductor elements only to good carrier tapes. .

このようにして半導体素子がボンディングされなかった
不良のキャリアテープは樹脂封止や半田メッキ、テステ
ィング等の後の工程においても無視され、無駄な工数を
かけずに済む。
In this way, defective carrier tapes to which semiconductor elements have not been bonded are ignored in subsequent processes such as resin sealing, solder plating, and testing, thereby eliminating unnecessary man-hours.

次に、ボンデイングの際にインナーリードの一部を認識
してアライメントを行うインナーリードボンダーで不良
のキャリアテープを検出する方法を述べる。
Next, a method for detecting a defective carrier tape using an inner lead bonder that recognizes and aligns a part of the inner lead during bonding will be described.

キャリアテープ検査機において不良と判定されたキャリ
アテープは、インナーリードボンダーで認識する一部の
インナーリード部を曲げるか切り取っておく。
For carrier tapes that are determined to be defective by the carrier tape inspection machine, some inner lead portions recognized by the inner lead bonder are bent or cut off.

インナーリードポンダーではインナーリードの一部を認
識してパターンマッチングによりアライメントを行うの
で、キャリアテープ検査機によって前記一部のインナー
リードが曲げられたり切り取られているとミスマッチン
グとなりアライメントができないため、無視されてボン
ディングは行われない。このように、一部のインナーリ
ードを用いてもアライメントマークの代用とすることが
できる。
The inner lead ponder recognizes a part of the inner lead and performs alignment by pattern matching, so if the part of the inner lead is bent or cut off by the carrier tape inspection machine, it will cause mismatching and alignment will not be possible, so it will be ignored. bonding is not performed. In this way, even if some inner leads are used, they can be used in place of alignment marks.

以上に述べたキャリアテープ検査機とインナーリードボ
ンダーは、各々別の機械として構成して2つの工程で半
導体素子をボンディングすることもできるが、キャリア
テープ検査機をインナーリードボンダーに組み込むこと
により、より効率的にキャリアテープ検査、半導体素子
のボンディングを行うことができる。
The carrier tape inspection machine and inner lead bonder described above can be configured as separate machines and bond semiconductor elements in two processes, but by incorporating the carrier tape inspection machine into the inner lead bonder, it is possible to bond semiconductor devices in two steps. Carrier tape inspection and semiconductor element bonding can be performed efficiently.

[発明の効果] 以上述べたように本発明によれば、良品のキャリアテー
プにのみ半導体素子をボンディングすることができるた
め、実装徨のテープキャリアの歩留りを向上することが
できる。また、不良のキャリアテープを良品と同じよう
に扱うことがないので工数を削減できる。したがって、
完成したテープキャリアの低コスト化が計れる。近年、
半導体素子の高集積化、高機能化が進み半導体素子のコ
ストが上がっている中で、歩留りを向上することはテー
プキャリアの低コスト化に大きく寄与する.の製造に使
用する良品のキャリアテープのアライメントマークの平
面図、第1図(b)は本発明におけるテープキャリアの
製造に使用する不良のキャリアテープのアライメントマ
ークの平面図、第2図は半導体素子を実装した徨のテー
プキャリアの平面図、第3図はアライメントされたキャ
リアテープと半導体素子の平面図。
[Effects of the Invention] As described above, according to the present invention, semiconductor elements can be bonded only to good carrier tapes, so that the yield of tape carriers after mounting can be improved. Furthermore, since defective carrier tapes are not handled in the same way as good products, the number of man-hours can be reduced. therefore,
The cost of the completed tape carrier can be reduced. recent years,
As semiconductor devices become more highly integrated and functional, and the cost of semiconductor devices increases, improving yields will greatly contribute to lowering the cost of tape carriers. FIG. 1(b) is a plan view of the alignment mark of a defective carrier tape used in the manufacture of the tape carrier of the present invention, and FIG. FIG. 3 is a plan view of the aligned carrier tape and semiconductor element.

1・・・アライメントマーク 2・・・キャリアテープ 5・・・インアーリード 6・・・半導体素子 以  上1... Alignment mark 2...Carrier tape 5...In early lead 6...Semiconductor element that's all

Claims (1)

【特許請求の範囲】[Claims] キャリアテープを検査し、後に半導体素子を実装してな
るテープキャリアの製造方法において、半導体素子をボ
ンディングする際に用いるアライメントマークに、キャ
リアテープの検査の合否判定結果を示し、良品のキャリ
アテープにのみ半導体素子を実装することを特徴とする
テープキャリアの製造方法。
In a method for manufacturing tape carriers in which a carrier tape is inspected and semiconductor elements are later mounted, the alignment mark used when bonding semiconductor elements indicates the pass/fail judgment result of the carrier tape inspection, and only good carrier tapes are manufactured. A method for manufacturing a tape carrier, characterized in that a semiconductor element is mounted thereon.
JP24274789A 1989-09-19 1989-09-19 Manufacture of tape carrier Pending JPH03104252A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24274789A JPH03104252A (en) 1989-09-19 1989-09-19 Manufacture of tape carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24274789A JPH03104252A (en) 1989-09-19 1989-09-19 Manufacture of tape carrier

Publications (1)

Publication Number Publication Date
JPH03104252A true JPH03104252A (en) 1991-05-01

Family

ID=17093662

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24274789A Pending JPH03104252A (en) 1989-09-19 1989-09-19 Manufacture of tape carrier

Country Status (1)

Country Link
JP (1) JPH03104252A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283487A (en) * 1992-04-03 1993-10-29 Mitsubishi Electric Corp Wiring for high-frequency signal and bonding device therefor
EP0641019A2 (en) * 1993-08-27 1995-03-01 Poly-Flex Circuits, Inc. A flexible printed polymer lead-frame
SG80635A1 (en) * 1998-07-31 2001-05-22 Seiko Epson Corp Semiconductor device and tape carrier, and method of manufacturing the same, circuit board, electronic instrument, and tape carrier manufacturing device
US6506980B2 (en) 1998-07-31 2003-01-14 Seiko Epson Corporation Semiconductor device and tape carrier, and method of manufacturing the same, circuit board, electronic instrument, and tape carrier manufacturing device
US7393754B2 (en) * 2003-06-19 2008-07-01 Sharp Kabushiki Kaisha Tape carrier type semiconductor device and method of producing the same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283487A (en) * 1992-04-03 1993-10-29 Mitsubishi Electric Corp Wiring for high-frequency signal and bonding device therefor
EP0641019A2 (en) * 1993-08-27 1995-03-01 Poly-Flex Circuits, Inc. A flexible printed polymer lead-frame
EP0641019A3 (en) * 1993-08-27 1995-12-20 Poly Flex Circuits Inc A flexible printed polymer lead-frame.
US5631191A (en) * 1993-08-27 1997-05-20 Poly-Flex Circuits, Inc. Method for connecting a die to electrically conductive traces on a flexible lead-frame
SG80635A1 (en) * 1998-07-31 2001-05-22 Seiko Epson Corp Semiconductor device and tape carrier, and method of manufacturing the same, circuit board, electronic instrument, and tape carrier manufacturing device
US6506980B2 (en) 1998-07-31 2003-01-14 Seiko Epson Corporation Semiconductor device and tape carrier, and method of manufacturing the same, circuit board, electronic instrument, and tape carrier manufacturing device
US7393754B2 (en) * 2003-06-19 2008-07-01 Sharp Kabushiki Kaisha Tape carrier type semiconductor device and method of producing the same

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