JPH03103948A - Memory protective circuit for microcomputer - Google Patents

Abstract

PURPOSE:To prevent write of erroneous data in a RAM due to program execution on an erroneous address by providing an address comparing circuit which confirms coincidence between a preliminarily determined address and the address where the write instruction read out by a CPU is written. CONSTITUTION:The address of a program memory 13 where the write instruction in a program is written is stored in an address comparing circuit 19. When a CPU 11 reads the write instruction from the program memory 13, coincidence between the address of the program memory 13 and the address in the address comparing circuit 19 is compared. The OR signal between the coincidence signal and the write signal outputted from the CPU 11 is sent to a RAM 15 as the new write signal. Thus, erroneous data write is prevented because the coincidence signal is not outputted from the address comparing circuit 19 in the case of runaway of the CPU 11.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to microcomputers, particularly CPUs.
The present invention relates to a memory protection circuit for a microcomputer that prevents erroneous data from being written to a RAM in the event of runaway.

[Prior Art] Generally, in a microcomputer, ROM (
Store the program in the read φ only memory) and
Various variable data are stored in M (random access memory). FIG. 3 is a block diagram showing the main parts of a general microcomputer.

A ROM 3 that stores fixed data such as programs and a RAM 4 that stores various variable data such as data and tables are connected to a CPU (central processing unit) 1 via a bus line 2, and a ROM 3 or RAM 4 that is accessed by the CPU Selection signal CSO, ? An address decoder 5 that outputs SI is provided.

Then, a continuation signal RD is sent from the CPUI to the ROMB, and a write signal WR is output to the RAM 4 in addition to the read signal RD. Additionally, this CPU can specify a 16-bit address space and output 8-bit data. That is, bus line 2 is composed of 16 lines, and ADO-
Up to AD7 outputs addresses and data in a time-sharing manner,
Only addresses from A8 to A15 are output. Also, ROM3 is assigned addresses [00001u~[7FPP]o, and RAM4 is assigned addresses [8000~~
[9PPP] o is assigned.

Further, the address decoder 5 is manually inputted with bi-soto data of the most significant one or two digits of the 16-bit address, and the bit data is used to control the ROM 3 and RAM.
The selection signals csO and CSI of either one of the four terminals are changed to the L level to control the access enabled state.

Then, for example, the CPU issues a write instruction MOV (8
500). When A-(1) is read, a write process is executed to write data [55]o stored in the A register to the RAM 4 according to the time chart shown in FIG.

First, address [
85001 o and data [55] o are output. At the same time, the selection signal CSI is sent via the address decoder 5.
change to L level. Then, when the write signal WR is output, the write enable terminal WE of the RAM 4 goes to L level, and the data [[
55]}1 is written to address [8500]H specified on the address bus in RAM4.

[Problems to be Solved by the Invention] However, even in the above-mentioned microcomputer, there are the following problems that still need to be solved.

In other words, for example, if the CPU becomes uncontrollable for some reason, that is, if the CPU goes out of control and a program is executed on RAMJ, the data on RAM4 happens to be the same as the write command in equation (1). CPU as instructions
If I reads and executes it, there is a problem that the normal data will be rewritten to other data [55]H because this is different from data writing in the original program flow.

The present invention was made in view of these circumstances, and
By providing an address comparison circuit that confirms that the program memory address to which the write command read by the CPU is written matches a predetermined address, it is possible to perform a write operation to the RAM only when the address matches. The purpose of the present invention is to provide a memory protection circuit for a microcomputer that can prevent data from being written erroneously, prevent important data from disappearing in RAM, and improve the reliability of the entire system. shall be.

5 [Means for Solving the Problems] In order to solve the above problems, the memory protection circuit of the microcomputer of the present invention includes a RAM for temporarily storing data, and a write function that specifies at least write data and an address in the RAM. It has a program memory that stores a program consisting of a plurality of instructions including instructions, and a CPU that controls these memories.The CPU reads a write instruction from the program memory, and this write instruction in the RAM In a microcomputer that also writes data specified by a write command to an address specified by the write command, the CPU compares whether the address of the program memory to which the write command read by the CPU is written matches a predetermined address. This device includes an address comparison circuit and a gate circuit that sends an AND signal of a match signal output from the address comparison circuit and a write signal output from the CPU to the RAM as a new write signal.

[Operation] In the memory protection circuit of the microcomputer configured in this manner, the address of the program memory to which the write command in the program is written is stored in the address comparison circuit.

When the CPU reads a write command from a program memory formed of, for example, a ROM, the address of the program memory where the write command is written matches the address in the address comparison circuit. It is compared whether or not. Then, the AND signal of the match signal and the write signal output from the CPU is stored in the RAM as a new write signal.
sent to.

Therefore, if the CPU goes out of control and reads a write command from an address other than the address where the original command word is written, the address comparison circuit will not output a match signal, so even if the CPU Even if it is output, the write signal is blocked by the gate circuit. As a result, data is prevented from being written erroneously.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

? FIG. 1 is a block diagram showing the main parts of a microcomputer incorporating a memory protection circuit according to an embodiment. 11 in the figure is a CPU that executes each section information processing, and this C
PUI 1 is connected to RO as a program memory that stores programs and various fixed data via bus line 12.
M13, R that temporarily stores general data that is not very important
Access processing is executed for each memory of the AM 14 and the RAM 15 that stores relatively important data. Furthermore, C
PUI is the output permission terminal O of each memory 13, 14.15.
The read signal RD is sent to the write enable terminal WE of the RAM 14 and the NAND gate 17 of the gate circuit 16. Also, similar to the CPUI in Figure 3,
A 16-bit address space can be specified and 8-bit data can be output. That is, the bus line 12 is composed of 16 lines, and addresses and data from ADO to AD7 are outputted in a time-division manner, and only addresses from A8 to A15 are outputted.

Also, ROM1B is [0000]H~[7PPPko ■A? response is allocated and RAM14 is [AOOO]
H ~ [PPPP] u is allocated, and RAM1
5 is assigned [8000]■~[9PPP]+{.

Further, the address decoder 18 receives bit data of, for example, the most significant one or two digits of the 16-bit address, and the bit data allows the ROM]. 3.RAM
One of the selection signals CSO, CSI, and CS2 inputted to each selection terminal CS of 14 and RAM 15 is changed to L level to control the corresponding memory to be accessible.

Furthermore, the 8-bit data output to the data path of the bus line 12 is input to the address comparison circuit 19. Then, the data of ADO-AD7 is taken in as address data of AO-A7 by the address latch signal, and
It is combined with the address of A15 and processed as one 16-bit address data AO to A15. The address comparison circuit 19 stores each address 9 ADS in which the program instructions stored in the ROM 13 are written. Then, if the address AD read from the bus line 12 matches one of the pre-stored addresses AD8, an H (high) level match signal a is output.

The match signal a output from one address comparison circuit is input to the input terminal D of the D-type flip-flop 20 of the gate circuit 6. Further, the read signal RD output from the CPU 11 is input to the clock terminal CP of the flip-flop 20 via the NAND gate 21 . Furthermore, at the other end of the NAND gate 21, from CPU 1, this CP
A fetch signal MI output when the UII reads data from each memory 13, 14, 15 is input. In the gate circuit 16, the output signal b of the output terminal 0 of the flip-flop 20 is applied to the other input terminal of the NAND gate 17.

Therefore, when the output signal 10C of the NAND gate 21 rises from the L level to the H level while the H level match signal a from one address comparison circuit is applied to the input terminal D of the flip-flop 20, the output terminal Output signal b of 0 falls from H level to L level. When the output signal b of the flip-flop 20 falls to the L level, the NAND gate 17 is established when the write signal WR from the CPU 1 inputted to the other input terminal of the NAND gate 17 changes to the L level. te, RAM1
A new write signal d as an L-level AND signal is applied to the write enable terminal WE of No. 5.

The operation of the memory protection circuit configured as described above will be explained using the time chart shown in FIG.

In order to simplify the explanation, a case is shown in which, for example, the write command described above is stored at addresses [10001s to [1002]s of the ROM 13, and the CPU 11 reads and executes this write command.

MOV (8500). A-(2) Therefore, in the address comparison circuit 19 and in the ROM 13,
[1002] of the addresses where the write command is written
o is also memorized.

First, the CPU 11 synchronizes with the fetch signal M1? and a ROM in which the write command is stored in the address bus.
Each address in 13 [10001H, [1001
Outputs ko , [1002] }I. Then,
The address decoder 18 determines the most significant 1 or 2 bits of the address and selects the ROMI 3 selection signal C.
Set SO to L level. Further, a read signal RD is sent out in synchronization with the fetch signal Ml.

As a result, [1000] H, [1001 Ko■, [
1002] Each data corresponding to the write command of formula (2) stored in H [3A] o, [00}l,
[85] H is output to the data path. CPUI 1 reads each data output to the data path.

In this case, one address comparison circuit reads the 16-bit address [1002] o read in the third fetch cycle.
Read as. And this address [1002] H
Since the address matches the pre-stored address, an H level match signal a is output.

Then, when the read signal RD in this fetch period returns to the original H level, the NAND gate 1221 is no longer established, and the output signal C of the NAND gate 21 is
rises to H level. As a result, flip-flop 2
Output terminal 0 of 0 falls from H level to L level. Note that at this point, the write signal WR is still being sent from the CPU II.
is not output, so the NAND gate 17 is not established.

Next, the CPU 1 which has read the write command shown by equation (2) from the ROMI 3 starts writing processing to the RAMI 5. First, output the previously read address [8500]H to the address bus, and
The data stored in the A register in the data path [55
] }Outputs 1.

When data [55]H is output to the data path, the address match of one address comparison circuit is canceled and the match signal a
returns to the L level, but the output signal b of the flip-flop 20 remains at the L level until the next fetch period is started.

Further, when the address [8500] H is output to the address bus, the address decoder 18 sends an L level selection/g CSI 13 to the RAM 15 into which data is to be written. Further, the CPUI1 lowers the write signal WR from the H level to the L level. Then, Nand Gate 1
7 is established, and the write signal d at L level is input to the write enable terminal WE of RAMI 5.

Therefore, data [55] H is written to address [85001 o of the RAM 15.

In the memory protection circuit of a microcomputer configured in this way, the ROM 13 is stored in the address comparison circuit 19.
Each address ADS to which each write command of the program stored in is written is stored. If the address AD read from the bus line 12 matches one of the addresses A D s stored in advance, a match signal a of H (high) level is output. Therefore, for some reason, CPUI 1 goes out of control and R
Even if an attempt is made to read the write command (formula 2) and write data to address [8500]H while the program execution has started on the AM, the address comparison circuit 19 does not output the match signal a.

Therefore, even if the CPU 1 sends out the address and data 14 and changes the write signal WR to the L level, the write signal d at the L level will not be applied to the write enable terminal WE of the corresponding RAM 15. It never happens. As a result, even if a program is executed at the wrong address, important data will not be rewritten and lost.

Therefore, important data stored in the RAM 15 can be
It is possible to reliably protect PUI 1 from running out of control.

[Effects of the Invention] As explained above, according to the memory protection circuit of the present invention,
By providing an address comparison circuit that confirms that the address written in the write command read by the CPU matches a predetermined address, a write operation to the RAM can be performed only when the addresses match. Therefore, even if the CPU goes out of control, it is possible to prevent a program from being executed at the wrong address and writing data to the RAM, which prevents important data in the RAM from being erased. Overall reliability can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the main parts of a microcomputer incorporating the memory protection circuit of the embodiment, Fig. 2 is a time chart 1 showing the operation of the circuit of the embodiment, and Fig. 3 is a general microcomputer. FIG. 4 is a block diagram showing the main parts of the microcomputer, and FIG. 4 is a time chart showing the write operation of the microcomputer. 11...CPU, 12...Bus line, 13...
ROM, 14.15...RAM, 16...Gate circuit, 17.21...NAND gate, 18...Address decoder, 19...Address comparison circuit, 20...
flip flop.

Claims (1)

[Claims] A RAM (random access memory 15) that temporarily stores data, and at least write data and the RAM.
A program memory (13) that stores a program consisting of a plurality of instructions including a write instruction specifying an address in the memory, and a CPU (central processing unit 11) that controls these memories.
), the CPU reads the write instruction from the program memory and writes data specified by the write instruction to an address specified by the write instruction in the RAM, An address comparison circuit (19) that compares whether the address of the program memory (13) in which the write command read by the CPU is written matches a predetermined address.
), the AND signal (d
) to the RAM as a new write signal.