JPH03101222A - Electrode structure of semiconductor element - Google Patents

Electrode structure of semiconductor element

Info

Publication number
JPH03101222A
JPH03101222A JP1238601A JP23860189A JPH03101222A JP H03101222 A JPH03101222 A JP H03101222A JP 1238601 A JP1238601 A JP 1238601A JP 23860189 A JP23860189 A JP 23860189A JP H03101222 A JPH03101222 A JP H03101222A
Authority
JP
Japan
Prior art keywords
semiconductor element
metal layer
plating
electroless
electrode structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1238601A
Other languages
Japanese (ja)
Inventor
Hideo Nakayoshi
中吉　英夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP1238601A priority Critical patent/JPH03101222A/en
Publication of JPH03101222A publication Critical patent/JPH03101222A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05558—Shape in side view conformal layer on a patterned surface
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Wire Bonding (AREA)
  • Chemically Coating (AREA)

Abstract

PURPOSE:To avoid the strength drop by diffusion even if it is let alone underhigh temperature and to improve bonding properties by providing at least an Ni metallic layer by electroless Ni plating. CONSTITUTION:A circuit is made of an SiO2 oxide film 3, an A1 wiring 2, etc., on a semiconductor element 1, and to take connection to the outside of the semiconductor element, the other part is covered with passivation 4. It is soaked in electroless Ni plating solution on the market so as to form an Ni metallic layer 5 on the exposed A1 pad 2. And a very small amount of irregularity is formed on the surface of the electroless Ni plating.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、半導体素子の電極構造に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to an electrode structure of a semiconductor device.

［従来の技術］ 半導体素子の電極構造は従来、第４図のように他の配線
と同じ１μｍ以下のＡｌ層（２）でできていた。その半
導体素子（１）をリードフレーム（１２）に設けたダイ
パッド（１３）に取り付け、半導体素子（１）の外部電
極とリードフレーム（１２）の端子とをそれぞれＡｕあ
るいはＡＩのワイヤ（８）で接続しこれをエポキシ樹脂
のような熱硬化性樹脂（１５）で封止したのち各端子を
切断した第５図のような半導体装置が主流だった。とこ
ろが、最近では電子機器の小型化、薄型化に伴い、これ
に使用する半導体装置も高密度実装するため薄くかつ小
型の半導体装置の出現が望まれてい・る。そこで最近で
は第６図のようにＡｌ電極層（２）上にＣｒやＴｉと言
ったバリアメタル層（１６）を介しその上に１０〜３０
μｍ程度のＡｕメッキを施し突起状にしたいわゆるバン
プ構造（１７）を有する半導体素子（１）とフィルムキ
ャリア（１８）の切欠き穴（１９）に突出して設けたフ
ィンガー（２１）とを熱圧着等で接続した復液状の樹脂
（例えばエポキシ樹脂）からなる封止材を印刷あるいは
ボッティングしてパッケージし９．たＴＡＢ実装方式が
でてきた。第７図はＴＡＢ実装方式を用いた半導体装置
の平面図である。図において、２ｏはスプロケットホー
ルである。[Prior Art] Conventionally, the electrode structure of a semiconductor element has been made of an Al layer (2) of 1 μm or less, which is the same as other interconnections, as shown in FIG. The semiconductor element (1) is attached to a die pad (13) provided on a lead frame (12), and the external electrodes of the semiconductor element (1) and the terminals of the lead frame (12) are connected using Au or AI wires (8). The mainstream was a semiconductor device as shown in FIG. 5, in which the terminals were connected, sealed with a thermosetting resin (15) such as epoxy resin, and then each terminal was cut. However, in recent years, as electronic devices have become smaller and thinner, the semiconductor devices used in these devices are also desired to be thinner and smaller in order to be mounted in higher density. Therefore, recently, as shown in Fig. 6, a barrier metal layer (16) such as Cr or Ti is placed on the Al electrode layer (2), and a layer of 10 to 30
A semiconductor element (1) having a so-called bump structure (17) plated with Au of approximately μm and formed into a protrusion shape and a finger (21) protruding from a notch hole (19) of a film carrier (18) are bonded together by thermocompression. 9. Package by printing or botting a sealing material made of condensate resin (for example, epoxy resin) connected with A new TAB mounting method has been developed. FIG. 7 is a plan view of a semiconductor device using the TAB mounting method. In the figure, 2o is a sprocket hole.

［発明が解決しようとする課題］ 第５図のようなＩＣパッケージは半導体素子のＡｌ電極
へＡｕワイヤを接続しているのがほとんどである。この
Ａｕ−Ａｌ共晶接続は高温放置により拡散が進み、脆い
合金層が形成されて接合強度が低下することが知られて
いる。実際には１５０°Ｃ下で３００時間経過するとボ
ンディング強度がなくなってしまうほどである。このこ
とは、高温時あるいは高温高温時の信頼性が低いことを
意味している。さらにはＡｌ電極自身が腐食性が強くそ
ばに０１やＮａイオンと水が存在すると腐食してＡｌが
溶は出してしまい、最後には接続が外れてしまうことに
なる。このことは高温高温時やプレッシャークツカー試
験と言った信頼性が低いことを意味している。このよう
に従来のＩＣパッケージでは上記の接合レベルでの問題
点があった。[Problems to be Solved by the Invention] In most IC packages as shown in FIG. 5, Au wires are connected to Al electrodes of semiconductor elements. It is known that when this Au-Al eutectic connection is left at high temperatures, diffusion progresses, a brittle alloy layer is formed, and the bonding strength decreases. In fact, the bonding strength is even lost after 300 hours at 150°C. This means that reliability at high temperatures or at high temperatures is low. Furthermore, the Al electrode itself is highly corrosive, and if 01 or Na ions and water are present nearby, it will corrode and the Al will dissolve, eventually resulting in disconnection. This means that the reliability is low when tested at high temperatures or during pressure tests. As described above, conventional IC packages have the above-mentioned problems at the bonding level.

さらにＡｌパッドが１μｍと非常に薄いためボンディン
グのショックでＡｌ下の８１基板にダメージを与えてし
まいクラックが発生したり、バンプ付きテープキャリア
（いわゆるＢＴＡＢＴＡＢ実装方式ボンディング時の加
熱温度及び加熱時間の範囲が狭いと言った問題点が生じ
ていた。Furthermore, since the Al pad is extremely thin at 1 μm, the shock of bonding can damage the 81 board underneath the Al, causing cracks, and the range of heating temperature and heating time during bonding using the bumped tape carrier (so-called BTABTAB mounting method). There was a problem that the space was too narrow.

本発明は、上記の目的を達成すべくなされたもので、高
温時あるいは高温放置時に拡散による脆い合金層を形成
せずボンディング強度を低下させず、さらに高温高温時
やプレッシャークツカー試験時にＡｌ電極がＣ１やＮａ
イオンと水が存在しても腐食しない半導体素子の電極構
造を得、さらにＡｌバッド下のクラックを発生せず、ボ
ンディングの条件範囲を広くすることを目的としたもの
である。The present invention has been made in order to achieve the above objects, and it does not form a brittle alloy layer due to diffusion and reduce bonding strength when exposed to high temperatures or when left at high temperatures, and furthermore, it does not reduce bonding strength when exposed to high temperatures or when left in high temperature conditions. is C1 or Na
The purpose of this invention is to obtain an electrode structure for a semiconductor element that does not corrode even in the presence of ions and water, and also to widen the range of bonding conditions without generating cracks under the Al pad.

［課題を解決するための手段］ 本発明の半導体素子の電極構造は、半導体素子上に設け
た複数の電極と外部回路基板およびり−ドフレームをＡ
ｕ線にて接続する半導体装置の実装構造及び、半導体素
子上に設けた複数の電極とテープキャリアの切欠き穴に
突出して設けた複数のフィンガーとを接続する半導体装
置の実装構造の内、前記半導体素子のＳｉ基板上にＡｌ
電極層を設け、前記Ａｌ電極層上にＮｉ金属層を設け、
前記Ｎｉ金属層上にＡｕ金属層を設けた電極構造におい
て、少なくともＮｉ金属層を無電解Ｎｉメッキにて設け
たことにより前記Ｎｉ金属層表面に微少な凹凸を形成し
たことを特徴とする。[Means for Solving the Problems] The electrode structure of the semiconductor element of the present invention has a plurality of electrodes provided on the semiconductor element, an external circuit board, and a lead frame.
Among the mounting structure of a semiconductor device connected by a U-line and the mounting structure of a semiconductor device connecting a plurality of electrodes provided on a semiconductor element and a plurality of fingers provided protruding into a notch hole of a tape carrier, the above-mentioned Al on the Si substrate of the semiconductor device
providing an electrode layer; providing a Ni metal layer on the Al electrode layer;
The electrode structure in which an Au metal layer is provided on the Ni metal layer is characterized in that at least the Ni metal layer is provided by electroless Ni plating, thereby forming minute irregularities on the surface of the Ni metal layer.

［作用］ Ａｌ電極上にＮｉ金属層さらにはＡｕ金属層を設けたこ
とで接合がＡｕ−Ａｕ接合となるので高温時の拡散がな
く接合強度が低下することがなく、高温時にも電極表面
がＡｕという腐食しない貴金属で覆われていることから
Ｃ１やＮａイオンが存在しても腐食してＡｌがなくなっ
てしまい接合が外れることがない、さらに電極層厚がＡ
ｌパッドよりも厚くなるためボンディングの衝撃でクラ
ックが生じず、無電解Ｎｉメッキ層が微少な凹凸を持っ
ているためボンディング性が向上した。[Function] By providing a Ni metal layer and further an Au metal layer on the Al electrode, the bond becomes an Au-Au bond, so there is no diffusion at high temperatures and the bond strength does not decrease, and the electrode surface remains stable even at high temperatures. Because it is covered with Au, a noble metal that does not corrode, even if C1 or Na ions are present, the bond will not corrode and the Al will disappear, and the bond will not come off.Furthermore, the electrode layer thickness is A
Since it is thicker than the L pad, cracks do not occur due to the impact of bonding, and the electroless Ni plating layer has minute irregularities, improving bonding performance.

［実施例］ 以下に本発明の実施例を図面に基づいて説明する。第１
図は本発明実施例の要部を示す断面図である。半導体素
子（１）の上には５ｉＯ２ｆｉ化膜（３）やＡｌ配ｍ　
（２）等で回路が形成されており、半導体素子外部へ接
続を取るため、その他の部分は回路を保護するためにパ
ッシベーション（４）で覆われているがパッド部分には
パッシベーション（４）がかかっていない。その露出し
たＡｌバッド（２）上にＮｉ金属層（５）を形成するた
めまずＡｌパッド上の汚染物を取り除くためイソプロピ
ルアルコールに浸漬した復硫酸にて軽くエツチングを行
い、ｐｄｃｌａ溶液に浸漬してＰｄをＡｌバッド表面に
吸着させて後、市販の無電解Ｎｉメッキ液に浸漬してＮ
ｉ金属層を形成する。その後無電解Ａｕメッキ液で置換
メッキを行い本発明の半導体素子の電極構造を形成した
。（実施例１） さて以上のように形成した電極は無電解Ｎｉメッキの特
徴である微少な凹凸がＡｕメッキ厚が薄いため電極表面
まで達している。[Example] Examples of the present invention will be described below based on the drawings. 1st
The figure is a sectional view showing a main part of an embodiment of the present invention. On the semiconductor element (1), there is a 5iO2fi film (3) and an Al arrangement.
(2) etc., and in order to connect to the outside of the semiconductor element, the other parts are covered with passivation (4) to protect the circuit, but the pad part is covered with passivation (4). It's not working. In order to form a Ni metal layer (5) on the exposed Al pad (2), first, in order to remove the contaminants on the Al pad, it was lightly etched with resulfuric acid soaked in isopropyl alcohol, and then soaked in PDCL solution. After adsorbing Pd on the surface of the Al pad, it is immersed in a commercially available electroless Ni plating solution to remove N.
i Form a metal layer. Thereafter, displacement plating was performed using an electroless Au plating solution to form the electrode structure of the semiconductor element of the present invention. (Example 1) Now, in the electrode formed as described above, minute irregularities, which are characteristic of electroless Ni plating, reach the electrode surface because the Au plating thickness is thin.

実施例１のようにして作成されたサンプルを第２図のよ
うにワイヤーボンディングして接合強度を測定したとこ
ろ次表のように差異はなかった。When the samples prepared as in Example 1 were wire-bonded as shown in FIG. 2 and the bonding strength was measured, there was no difference as shown in the following table.

尚比較例１は通常のＡｌパッドの電極構造のものをワイ
ヤーボンディングしたものである。又ＣモードとはＡｕ
線の途中で切れたものである。サンプル数は各１００個
である。In Comparative Example 1, an ordinary Al pad electrode structure was wire-bonded. Also, C mode is Au
It was cut in the middle of the line. The number of samples is 100 each.

ィンガー（９）を半導体素子（１）のパッドに対応した
部分にバンブ状の突起（１１）をハーフエツチングを用
いて形成し、パターンをＮｉメッキ後金メッキ（１０）
をおこないそのフィルムキャリアを熱圧着にて接合する
いわゆるＢＴＡＢ実装方式でも接合強度に変化がみられ
なかった。（表２参照）表２ 表１ 表を見て判るように接合強度及び破壊部位に差異は見ら
れなかった。同様に第３図のようにフィルムキャリア（
１８）上にパターンニングされたＣｕフ尚比較例２は通
常のＡｌｌバッドをＢＴＡＢ実装したものである。Ｆモ
ード車とはフィンガー途中で切れたものの割合である。Bump-shaped protrusions (11) are formed on the fingers (9) in areas corresponding to the pads of the semiconductor element (1) using half etching, and the pattern is plated with Ni and then gold plated (10).
Even with the so-called BTAB mounting method, in which the film carrier is bonded by thermocompression bonding, no change in bonding strength was observed. (See Table 2) Table 2 Table 1 As can be seen from the table, no difference was observed in the joint strength and fracture site. Similarly, as shown in Figure 3, the film carrier (
18) Cu pad patterned on the top Comparative example 2 is an ordinary All pad mounted with BTAB. The percentage of F-mode cars is that of cars that break in the middle of the finger.

サンプル数は各１００個である。The number of samples is 100 each.

以上第２図および第３図の実装構造において本発明の電
極構造は通常のＡｌｌバッドと同等がそれ以上の接合強
度を持っており、各金属層間の密着性にはなんの問題も
ない。In the mounting structures shown in FIGS. 2 and 3, the electrode structure of the present invention has a bonding strength equal to or greater than that of a normal All-in-all pad, and there is no problem with the adhesion between the metal layers.

次に以上のサンプルを今度は１５０°Ｃに保った恒温槽
内にて放置した際の各時間における接合強度の変化を表
にした。表３はワイヤーボンディングのサンプル、表４
はＢＴＡＢ実装サンプルで行った結果である。Next, the above samples were left in a constant temperature bath kept at 150°C, and the changes in bonding strength over time were tabulated. Table 3 is a wire bonding sample, Table 4
These are the results obtained using a BTAB implementation sample.

表３ 表４ 表３、表４から実施ＶＡｌはＢＴＡＢ実装サンプルでフ
ィンガー自身が熱で劣化してわずかながら強度が低下し
てしまったが時間が経過しても殆ど変化していないこと
が判る。Table 3 Table 4 From Tables 3 and 4, it can be seen that the actual VAl was a BTAB mounted sample, and the fingers themselves deteriorated due to heat, resulting in a slight decrease in strength, but there was almost no change over time.

次に同様にして作成したサンプルを今度はプレッシャー
クツカー試験（１２１℃１００％２ａｔｍ）にて放置し
た際の各時間における接合強度の変化を表にした。表５
はワイヤーボンディング品表６はＢＴＡＢ実装品である
。Next, samples prepared in the same manner were subjected to a pressure courier test (121° C., 100%, 2 atm), and the changes in bonding strength at each time were tabulated. Table 5
Wire bonding product table 6 is a BTAB mounted product.

表５ 表６ 表５、表６より実施例１では接合強度の変化はみられな
かった。比較例１及び比較例２のサンプルはいずれもＡ
ｌが拡散したのに加えＡｌが腐食してなくなったことに
より強度低下が起こったものである。Table 5 Table 6 From Tables 5 and 6, no change in bonding strength was observed in Example 1. Both samples of Comparative Example 1 and Comparative Example 2 are A
In addition to the diffusion of L, the strength decreased due to the corrosion and disappearance of Al.

次に実施例１の電極構造でＮｉメッキ厚を０゜５〜５μ
ｍまで水準を振ってＢＴＡＢ実装を行い接合部分のＡｌ
パッド下のダメージを観察するためにＫ　ＯＨ液に浸漬
してＡＩを剥離した際のクラック発生率を調べたところ
全ての水準とも０％と全く発生していなかった。比較例
２のサンプルについて同様に調べたところクラック発生
率は約半分も起こっていた。Next, with the electrode structure of Example 1, the Ni plating thickness was set to 0°5 to 5μ.
BTAB mounting was performed with the level up to m, and the Al of the joint part
In order to observe damage under the pad, the rate of crack occurrence when the AI was peeled off after being immersed in a KOH solution was examined, and it was found that no cracks were generated at all, 0% at all levels. When the sample of Comparative Example 2 was examined in the same manner, the crack occurrence rate was approximately half as high.

次に実施例１のサンプルをＢＴＡＢ実装する際の加熱ツ
ール温度と加熱時間を以下の表のように振ってボンディ
ング性の評価を行った。Next, the bonding properties were evaluated by changing the heating tool temperature and heating time when BTAB mounting the sample of Example 1 as shown in the table below.

表の中のボンディング性の評価基準はＯはＦモード率が
１００％で最低ボンディング強度が２０ｇ以上、ＯはＦ
モード率が９０％以上で最低ボンディング強度が２０ｇ
以上、△はＦモード８０〜９０％、ＸはＦモード８０％
以下または最低ボンディング強度が２０ｇ以下、×Ｘは
Ｆモード５０％以下とした。尚表７は本発明の実施例１
の電極構造のＢＴＡＢサンプル、表８は比較例２のＡｌ
パッド品のＢＴＡＢ実装サンプルのボンディング性の評
価結果である。The evaluation criteria for bonding properties in the table are: O has an F mode rate of 100% and a minimum bonding strength of 20g or more;
Mode rate is 90% or more and minimum bonding strength is 20g
Above, △ is F mode 80-90%, X is F mode 80%
or the minimum bonding strength was 20 g or less, and ×X was 50% or less in F mode. Table 7 shows Example 1 of the present invention.
Table 8 shows the Al electrode structure of Comparative Example 2.
This is an evaluation result of the bonding property of a BTAB mounting sample of a pad product.

表７ 表８ 以上の結果より明らかなように本発明の実施例１の電極
構造は比較例１のＡｌｌバッドと比べ格段にボンディン
グ性が向上した。Table 7 Table 8 As is clear from the above results, the electrode structure of Example 1 of the present invention had significantly improved bonding properties compared to the All-Bud pad of Comparative Example 1.

［発明の効果］ 以上説明した本発明の半導体素子の電極構造はワイヤー
ボンディング方式、ＢＴＡＢ実装方式の如何に関わらず
初期ボンディング強度の劣化もなく、例えば１５０″Ｃ
下の高温放置下でも拡散による強度低下もなく、さらに
はプレッシャークツカーテスト等の恒温下でも電極が腐
食することな〈従来のＡｌバッドのものより格段に信頼
性を高めることが出来た。さらにボンディング時のＡｌ
バッド下のクラックの発生もなく、無電解Ｎｉメッキの
特徴である微少な凹凸がボンディング時の加熱温度と時
間の範囲をかなり広げることができ結果的にはボンディ
ング性を向上することが出来た。[Effects of the Invention] The electrode structure of the semiconductor element of the present invention described above has no deterioration in initial bonding strength regardless of the wire bonding method or the BTAB mounting method,
There is no decrease in strength due to diffusion even when left at high temperatures, and the electrodes do not corrode even under constant temperature conditions such as pressure-cutting car tests (reliability has been improved significantly compared to conventional Al pads). Furthermore, Al during bonding
There were no cracks under the pad, and the minute irregularities characteristic of electroless Ni plating allowed the range of heating temperature and time during bonding to be considerably expanded, resulting in improved bonding performance.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の要部を示す断面図。第２図は本発明の
半導体素子をワイヤーボンディングした際の実装断面図
。第３図は本発明の半導体素子をＢＴＡＢＴＡＢ実装の
実装断面図。第４図は従来の半導体素子の電極構造の断
面図。第５図は従来のワイヤーボンディングされたＩＣ
パッケージの実装断面図。第６図は従来のＴＡＢ実装用
のＡｕバンブ構造を有した半導体素子の電ｆｌＳ構造の
断面図。第７図はＴＡＢ実装された半導体装置の実装平
面図である。 に半導体素子、２：Ａｌｌ、３：　Ｓｉ０２層４：パッ
シベーション、５：無電解Ｎｉメッキ層、６：Ａｕ金属
層、７：Ａｕボール、８：Ａｕ線、９：Ｃｕフィンガー
　１０：Ａｕメッキ層、１１：バンブ、１２：　リード
フレーム、１３：ダイバッド、１４：熱硬化樹脂、１５
：バリヤ層、１６：Ａｕバンブ、１７：フィルムキャリ
ア、１８：切欠き穴、１９：スプロケットホール、２０
：フィンガー 以上FIG. 1 is a sectional view showing the main parts of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device of the present invention when wire bonded. FIG. 3 is a cross-sectional view of BTABTAB mounting of the semiconductor element of the present invention. FIG. 4 is a cross-sectional view of the electrode structure of a conventional semiconductor device. Figure 5 shows a conventional wire-bonded IC.
A sectional view of package implementation. FIG. 6 is a cross-sectional view of the electric flS structure of a semiconductor element having a conventional Au bump structure for TAB mounting. FIG. 7 is a mounting plan view of a TAB-mounted semiconductor device. 2: All, 3: Si02 layer 4: Passivation, 5: Electroless Ni plating layer, 6: Au metal layer, 7: Au ball, 8: Au wire, 9: Cu finger 10: Au plating layer, 11: Bamboo, 12: Lead frame, 13: Die pad, 14: Thermosetting resin, 15
: Barrier layer, 16: Au bump, 17: Film carrier, 18: Notch hole, 19: Sprocket hole, 20
:Finger or more

Claims (1)

【特許請求の範囲】[Claims] 半導体素子上に設けた複数の電極と外部回路基板および
リードフレームをＡｕ線にて接続する半導体装置の実装
構造及び、半導体素子上に設けた複数の電極とテープキ
ャリアの切欠き穴に突出して設けた複数のフィンガーと
を接続する半導体装置の実装構造の内、前記半導体素子
のＳｉ基板上にＡｌ電極層を設け、前記Ａｌ電極層上に
Ｎｉ金属層を設け、前記Ｎｉ金属層上にＡｕ金属層を設
けた電極構造において、少なくともＮｉ金属層を無電解
Ｎｉメッキにて設けたことにより前記Ｎｉ金属層表面に
微少な凹凸を形成したことを特徴とする半導体素子の電
極構造。A mounting structure of a semiconductor device in which a plurality of electrodes provided on a semiconductor element are connected to an external circuit board and a lead frame using an Au wire, and a plurality of electrodes provided on a semiconductor element are provided protruding into a notch hole of a tape carrier. In the mounting structure of a semiconductor device that connects a plurality of fingers, an Al electrode layer is provided on the Si substrate of the semiconductor element, a Ni metal layer is provided on the Al electrode layer, and an Au metal layer is provided on the Ni metal layer. 1. An electrode structure for a semiconductor device, characterized in that, in the electrode structure provided with layers, at least a Ni metal layer is provided by electroless Ni plating, thereby forming minute irregularities on the surface of the Ni metal layer.
JP1238601A 1989-09-14 1989-09-14 Electrode structure of semiconductor element Pending JPH03101222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1238601A JPH03101222A (en) 1989-09-14 1989-09-14 Electrode structure of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1238601A JPH03101222A (en) 1989-09-14 1989-09-14 Electrode structure of semiconductor element

Publications (1)

Publication Number Publication Date
JPH03101222A true JPH03101222A (en) 1991-04-26

Family

ID=17032614

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1238601A Pending JPH03101222A (en) 1989-09-14 1989-09-14 Electrode structure of semiconductor element

Country Status (1)

Country Link
JP (1) JPH03101222A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064852A (en) * 2007-09-05 2009-03-26 Okutekku:Kk Semiconductor device, and manufacturing method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009064852A (en) * 2007-09-05 2009-03-26 Okutekku:Kk Semiconductor device, and manufacturing method of semiconductor device

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