JPH03100990A - Method for erasing information in bloch line memory - Google Patents

Abstract

PURPOSE:To realize high-speed erasing by providing a conductor for signal erasing on a polarity layer. CONSTITUTION:When a bias magnetic field is weakened while fixing the position of paired VBL 8 from an initial state, the heads of stripe domains S1, S2 and S3 are extended. Next, by impressing a current to the lower parts of conductors C1, C2 and C3 for erasing and simultaneously executing signal transfer, the paired VBL 8 are separated and moved. The current direction of the conductor C1 is inverted and the VBL is moved. When the current of the conductor C2 is interrupted or reversely inverted, a magnetic field is impressed in a direction reverse to the magnetizing direction of a Bloch magnetic domain wall part, which is sandwiched by the two VBLs forming the paired VBL 8, and the magnetizing direction is inverted. Then, the VBL is erased. Thus, since chopping operation is not adopted for erasing the paired VBL, the VBL can be erased at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of erasing information in a Bloch line memory.
The present invention relates to a method of erasing an information signal (VBL pair) in a Bloch line memory that uses as a recording signal without creating a bubble or collapsing the bubble.

[Conventional technology]

With the development of high-density storage devices, Bloch line memory has attracted attention due to its large storage capacity and non-volatility.

In Bloch line memory, the information storage part is composed of domain walls around striped domains that are elongated bubble domains. Vertical Bloch line pairs (VBL pairs) are written on the domain walls, and the presence or absence of this pair is determined by #1 jj, 0''. This is because the Bloch line memory (BLM) is roughly divided into, as shown in FIG. 1, a bubble transfer section (major line) 1, a signal write/read section 2, Signal storage section (minor loop) 3
It is made up of three elements. Here, if we look at the signal writing/reading section 2 in detail, as shown in FIG.
BL control conductor 4, signal writing conductor 5,
A conductor 6 for signal readout, etc. is provided, and when erasing a signal, the two conductors 5,
6 are often used together.

FIG. 3 shows the principle of operation of conventional signal cancellation. Here, for convenience of explanation, VBLBaO2 exists in the stripe domains S and S, and no VBL pair exists in the stripe domain S2.

In the initial state, one dummy VBL7 exists in the head part of each stripe domain (the third
Figure (a)). Therefore, when transferring the signal (VBL pair),
Since the VBL pair passes through the head section, three VBLs are lined up in the head section. By weakening the bias magnetic field HB while maintaining this state, the head section is stretched to a position where it straddles the conductor 6 (
Furthermore, the stripe head portion is chopped by passing a current through the conductor 6 and generating a current magnetic field in the same direction as the bias magnetic field (Fig. 3(b)).
C)). As a result, the VBL pair to be erased is transferred to the bubble 9 newly generated by the chopping, and at the same time, one dummy VBL is generated in the stripe head portion. And the striped head part in this state is
Figure 3 (
Return to the initial state shown in a), and here the VBL pair (signal)
will have been deleted. In addition, Fig. 3 (a) (b)
In (c), VBL is represented by an arrow.

Meanwhile, the generated bubble 9 is then collapsed.

However, when the signal (VBL pair) is erased using the conventional method, a new bubble is generated along with the erasure, and this bubble must be collapsed by some means, and in the end, the erasure of the VBL pair The drawback is that it takes a long time to win.

[Problem to be solved by the invention]

The present invention solves the above-mentioned drawbacks, and the information=signal (V
This invention provides a method for erasing information in a Bloch line memory, which shortens the time required for erasure and increases the read speed.

[Means to solve the problem]

The method for erasing information (signal) in the Bloch line memory of the present invention involves providing a parallel conductor for signal erasing on the polar layer where the signal is recorded, and vertical Bloch line pairs (VBL).
Bloch domain wall (V
It is characterized by erasing the VBL pair by generating a magnetic field in the opposite direction to the magnetization direction of the BL pair (domain wall between the BL pairs) by passing a current through the conductor.

Incidentally, the present inventors have previously conducted detection and extraction methods for erasing information signals in Bloch line memories, and by manipulating the direction of the magnetic field, the process of bubble generation and bubble collapse can be controlled. The present invention is based on the discovery of a method for erasing VBL pairs without employing the above method.

Below, the VBL pair elimination method of the present invention will be explained in more detail with reference to the drawings (FIG. 2).

In Fig. 2, the initial state is exactly the same as in Fig. 3(a) (Fig. 2(a)), Fig. 2(a)
, the erasing conductors C, ,C, and C1 are arranged parallel to each other and perpendicular to the stripe domain S, ,S, ,S, and the conductor CxtC
, , C are each independently controlled in current. However, although the VBL control conductor, signal write conductor, and signal read conductor are not shown in FIG. 2, it is possible to use some of them together with the erase conductor.

As mentioned earlier, in FIG. 2(a), VBLBaO2 is placed at the position closest to the head of the striped domain.
The existing striped domains S1 and S.

, and a stripe domain S2 in which no such VBL pair exists. Now, this initial state (second
As shown in FIG. 3(a), when the bias magnetic field is weakened while the VBLBaO2 position is fixed, the heads of the stripe domains 5tyS2 and S are stretched as shown in FIG. 3(b).

Next, from this state, a current is applied in the direction indicated by the thick arrow (that is, a current is applied so as to generate an in-plane magnetic field at the bottom of the erasing conductor), and at the same time, signal transfer is performed to separate VBLBaO2, and each Move to the position shown in FIG. 3(C). After that, the current direction of conductor C1 is reversed, and VBL is placed at the position shown in FIG. 2(d).
move.

Finally, when the current in conductor C2 is cut off or the current is reversed in the opposite direction, a magnetic field is applied in the opposite direction to the magnetization direction of the Bloch domain wall sandwiched between the two VBLs forming the VBL pair, causing magnetization. The direction is reversed and VBL is erased (FIG. 2(e)).

Regarding the structure of the Bloch line memory (device) itself used in the method of the present invention, compared to the conventionally known one, erasing conductors CXtC2 and C3 are newly provided. The difference is that the conductor is replaced by a scale (as mentioned above), and since no chopping operation is adopted, no bubble is generated and there is no need to provide a means for collapsing it. Other than that, they are essentially the same.

〔Effect of the invention〕

According to the method of the present invention, erasing of VBL pairs (information signals) does not include the steps of chopping and collapsing bubbles generated by the chopping, so that VBL pairs can be erased at high speed.

[Brief explanation of drawings]

FIG. 1 is a diagram schematically showing the main parts of a Bloch line memory device. FIG. 2 is a diagram for explaining the method of the present invention. FIG. 3 is a diagram for explaining a conventional VBL pair elimination method. S engineering tsatsa...stripe domain C1, C,
, C,... Erasing conductor 8... VBL pair

Claims (1)

[Claims] (1) In a method of erasing a vertical Bloch line pair (VBL pair), which is an information signal, from a Bloch line memory,
A parallel conductor for signal erasing is provided on the magnetic layer where signals are recorded, and a magnetic field is generated in the opposite direction to the magnetization direction of the Bloch domain wall sandwiched between two VBLs forming a VBL pair by passing a current through the conductor. A method for erasing information in a Bloch line memory, characterized by erasing a predetermined VBL pair.