JPH03100775A - Spoke register generating circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale by supplying the address different among respective bit planes from an address generating part to one of first and second memories. CONSTITUTION:Quantized edge directions of a close loop form of a picture are stored in a first 8-bit memory 1 where edge directions quantized to 8 directions are stored, and a local data extracting part 2 simultaneously reads out edge direction data of dot strings corresponding to quantized directions form the first memory 1. An arithmetic processing part 3 generates spoke register based on edge direction data, and contents of the spoke register are stored in a second memory 4, and an address generating part 5 supplies the address common to respective bit planes to one of first and second memories 1 and 4 and supplies the address different among respective bit planes to the other. Thus, the edge direction data area to be held in the local data extracting part is reduced, and a spoke register generating circuit which is smaller-sized than conventional is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a circuit that executes a spoke filter, which is a method for extracting shapes such as circles and ellipses from nine squares.

[Conventional technology]

Conventionally, a method called a spoke filter is known as a method for extracting shapes such as circles and ellipses from fII light images. This method takes advantage of the fact that, for example, in the case of a circle, all edge directions at points on the circumference point toward the center of the circle. ), the entire circle is extracted using the fact that the number of intersections increases near the center of the circle.

This spoke filter process is described in the reference document Le.
ss G, Minor and Jack 5kla
nskyrThe D6teC1iOn and Se
gmentation of Blobs in Inf
Rared ImagesJ IEEE Trans
an-C1lOns Orl 5systems, Ma
rl, and Cybernetlcs.

VOl, SMC-H, No, 3. March 1
As disclosed in 981 (1), 1!4-201), the system consists of the following three steps: ■ A process to generate a spoke register indicating the intersecting state of spokes; Processing to generate an ortosbork register representing the result of the OR operation in the 3X3 neighborhood ■ n, ot or IK depending on the intersecting state of the spokes represented in the ortosbork register
Mapping processing for binarizing and outputting the spoke filter results Among these, the creation of the ortosbork register in ■ is 3X
The binary logical filter processing of 3 and the mapping processing of t and 2 can be executed in real time using standard hardware that performs conversion processing using a lookup table.

On the other hand, there is a spoke register generation circuit for executing the generation of spoke registers in step 1 in real time.

In FIG. 6, which shows a block diagram of a conventional spoke register generation circuit, (1) is a first memory having an 8-bit configuration that is quantized in eight directions and stores nine edge directions; (2) is the first memory ( 1), the quantization direction 1 (i=Q,...
・, 7) Simultaneously 1fC edge direction data of point sequence according to K
i! Y! The local data extraction part of the protruding tiger.

+3) is a calculation processing unit that performs calculations to generate spoke registers based on the edge direction data sent from the local data extraction unit (21); (4I is the calculation processing unit (
8. Store all contents of the spoke registers generated in step 31.
The second memory has a bit configuration, and (5) the first memory has an 8-bit configuration.
This is an address generator that supplies a common address to the @bit plane to each of the memory (1) and the second memory (41).

Then, for all points edge direction data], the final result is the contents of the spoke registers for the entire screen.

(However, in the initial session, all bits of the spoke register are set to O.) Now, the spoke register R (l of xi) for the point of interest
If you look at it the other way around, the presence of 1 in the 14th bit means that there is a 1 in the 14th bit.
As shown in the figure, from point x = (x, y), direction i and the opposite direction [8
If we create an inverse spoke j of length L pixels nine pixels apart, then the point inside it is U=(U.

This means that there exists a point in at least one of V) whose edge direction is It t.

The edge direction is 8 from O to 7 as shown in Figure 12.
When the quantization direction is 1, only the l-th bit is set to 1, and all other bits are set to O. 1st
Assume that the data is stored in the first memory (1) in 8-bit representation as shown in FIG. Point U on this first memory + 1) = (
When the edge direction in U, V) is i, if we create a "spoke" with a length of KS pixels in the i direction for one point uK, the internal point wing = (x, y) will be as follows. is expressed in

0 standing 0. Δyo)=(-t-o)e (AXl, Δy
1):(-1,-1)(N2.Δy2)=(0,-1)
, (Δx3.Δys)=(L 1)(7□4.Δ
y4)=(1,0), (lack5.Δ)'5)=(Ll
)(N6.Δy6)=(Os1)−(Etsu7.Δy7)=
(-1, 1) That is, by sequentially locating the first memory (1) that stores edge direction data using the addresses supplied by the address generation section (5), the first local data extraction section (21) 8 extending from the point of interest X according to the quantization direction i
The edge direction data of the points inside the "reverse spokes" of the seed ode are read out at the same time. Then, for each quantization direction i, the arithmetic processing unit (3) processes at least one of the nine "reverse spokes" according to the quantization direction i.

Determine whether there is a point whose edge direction is i,
If it exists, it outputs #:1'1, and if it does not exist, it outputs 0. The output result of this arithmetic processing unit (31) is transferred to the attention point
Write as the i-th bit of . Edge direction data stored in the first memory il+.

When expressed in 8-bit representation as shown in Figure 13,
The above operation is an independent parallel process for each bit.

FIG. 7 is a circuit configuration diagram showing a local data extraction section in the spoke register generation circuit of FIG. 6.

In the figure, cln is a shift register that holds data for one line, and cln is a latch that holds data at each point. As shown in Figure 1, 2M shift registers (1
) and (2M+1)X(2M-H) latches+
By the configuration in which 211 is placed in a matrix K, (2M
+1) X (2M+1) local data can be held.

Here, M≧S+L. That is, the first memory (1) in which the edge direction is stored is stored in the address generator (5+
using the addresses (ty,v) supplied by Point (U, V), (U-2M, V)
, (U, V-2M).

(U-2M, V-2M)C) l'3 parts (2M+1)
Data of a local region of X(2M+1) is held. Of these, the data sent to the arithmetic processing unit (31) is indicated by the diagonal line in FIG.
= (u, v) (k=1. ”・, M) data.

Further, FIG. 8 is a circuit configuration diagram showing an arithmetic processing section in the spoke register generation circuit of FIG. 6.

Figure 8 Ki? cIp#:t, edge direction data IC(utk) (k=1.-, pa)(D
Of these, the M-bit mask register for validating only the data of the points inside the "reverse spoke" is the edge direction data K(uik) (k=1. . . . ).
M) and the contents of mask register C111 MRk (k=
=1,...,M) between the corresponding bits, AND
Calculation is performed using a 5-AND circuit.

(To) is an M input-1 output OR circuit that performs an OR operation on the outputs of M AND circuits (To).

Note that the contents of the mask register Gυ MRk (k=1...
M) is set as follows according to the values of S and L.

Also, the point of interest (x, Y) on the i-bit plane (common to each bit) is to set = j in the 0 formula and compare it with the ■ formula K
It will be as follows.

At this time, the output of the OR circuit is the above noted point (X, Y)
It is 1 if there is at least one point with edge direction i inside the "reverse spoke" for , and 0 if there is none. The output result of this OR circuit (to) is sent to the second memory (4).

In addition, FIG. 9 shows that the spoke register generation circuit of FIG.
FIG. 3 is a circuit configuration diagram showing an address generation section in the computer. In the figure, (51) is the address generation circuit 1 and 2 that supplies a common address to each bit plane to the first memory (1) and the second memory (41), and (52) is the address generation circuit (51). ) is a timing generation circuit that generates a clock (CLK), a horizontal load signal (box 1), and a vertical load signal (VLD).

For example, if the size of the first memory +11 and the second memory (41) is 25@x25g pixels, the control signals (CLK, HLD, VLD) such as 111V 'j-1 timing generation times - (52) Address generation circuit (s+) d, as shown in Figure 10, a start address register (5) consisting of two II bit latches and an address counter (512) consisting of two 8-bit counters.
It consists of a horizontal load signal (iτ) and a vertical load signal (iτ).
After loading the contents of the start address register (5+1) into the address counter (512) using the clock (VLD) (synchronous loading), the clock (C
LK), and in the vertical direction, a horizontal load signal (HLD) is used to count up and generate horizontal and vertical addresses, respectively.

For the first memory (11), address generation circuit 1 (5
1) Set the start address register (511) to (0°0
)K to generate the address (U, V), and the second
For memory (4), set the start address register (511) of address generation circuit 2 (51) to (-M, -M).
ft to generate the address (x, y).
L is the address of the point of interest (X, Y) #i.

In this way, the output results of the arithmetic processing unit (31) on each bit plane are sequentially written to the points of interest (X, Y) on each bit plane of the second memory 141. Spoke registers can be created.

[Problem to be solved by the invention]

Since the conventional spoke register generation circuit is configured as described above, (2M+1) in one local data extraction section.
Since it is necessary to hold X(2M+1) local data, there is a problem in that the scale of the spoke register generation circuit increases.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a spoke register generation circuit t- which is smaller in size than the conventional one.

[I! 1lIilil! [Means for Solving] In the spoke register generation circuit according to the present invention, the quantized edge direction of the closed loop shape is stored in the first memory m, and the 0 local data extraction unit extracts the quantized edge direction from the first memory. The edge direction data of the point strings are simultaneously read out according to the direction, the arithmetic processing unit generates a spoke register based on the edge direction data sent from the local data extraction unit, and the second memory is generated by the arithmetic processing unit. The address generator stores the contents of the spoke registers.

One of the first memory and the second memory is supplied with a common address for each bit plane, and the other is supplied with a different address for each bit plane.

[Effect]

In the spoke register generation circuit configured as described above, the address generation section supplies a common address to each bit plane to one of the first memory and the second memory, and supplies a common address to each bit plane to the other. supply a different address.

[Embodiments of the invention]

FIG. 1 is a diagram showing the overall configuration of a spoke register generation circuit according to an embodiment of the present invention in the case where, for example, edge directions are quantized in eight directions. In the figure, (
! ) stores the edge direction quantized in the direction 8
A first memory configured in bits.

(21 is from the first memory (1) to the quantization direction 1(i
=O0...7) A local data extraction unit that simultaneously extracts the edge direction data of the point sequence according to K, (31#i
An arithmetic processing section (4+ stores the contents of the spoke registers generated by the arithmetic processing section 31), which performs an arithmetic operation to generate spoke registers based on the edge direction data sent from the local data extraction section (31). The second memory has a one-bit configuration (5+ is the first memory (1
) is supplied with a common address for each bit plane, and #1!2 memory (41) of S-bit configuration is an address firing unit that supplies a different address for each bit plane.

The configuration and operation of each part will be explained below.

The local data extraction unit in the spoke register generation circuit according to the embodiment of the present invention is different from the local data extraction unit in the conventional spoke register generation circuit shown in FIG. XM' latches (arranged in a 211ft matrix) are designed to hold M' x M' local data.Here, M'≧L.In other words, the edge direction is memorized. The first memory (Il′ft
, the address (U, V) supplied by the address generator (5)
By sequentially scanning h″″c using h″″c, each latch 12IlK of
4 points (u, v) on the bit plane of 1, (U-M'
-)-1, V), (υ, V-M'+1), (U-
M'+1. V-M' +1) O inside +7) M'
Data of the local area of XM' is held. Of these, the data sent to the arithmetic processing unit (31) is transmitted to the point indicated by the beveled edge in FIG. 5 on the direct pit plane = (u,
v) (k=t, -, M').

Furthermore, the arithmetic processing unit applied to the spoke register generation circuit according to the embodiment of the present invention is similar to the arithmetic processing unit in the conventional spoke register generation circuit shown in FIG.
M' bit configuration mask register (lft, M' AND circuits (to) 0M' person car 1 output OR circuit (to)
It consists of In addition, mask register x16Do contents MR
k (k=1.-M') is s.

The following settings are made according to the value of L.

Also, the point of interest (XhYt) on the i-bit plane is =
Write j-s and compare it with the formula ■K.

K is as follows.

At this time, the output of the OR circuit Ω is the above noted point (XhYt
) Inside the "reverse nuvoke" against K.

When there is at least one point with edge direction i, it is 1), and when there is no point, it is O. The output result of this OR circuit ■ is the second memo! j 141.

FIG. 2 is a circuit configuration diagram showing an address generation section in a nouveau register generation circuit according to an embodiment of the present invention.

In the figure, (5υ#:) is an address generation circuit 1 that supplies a common address to each bit plane of the first memory (1), and an address generation circuit that supplies a different address to each bit plane of the second memory (41). 2.0~17° (52)
is a timing generation circuit.

For the first memory (13K), address generation circuit 1 (S
+) start address register (511) (0°0
)K to generate the address (U, V).

The second memory (for 4101 bit planes, the start address register (5) of the address generation circuit 2.1 (51)) tube (-m+Δx 1 ・(S +m+ 1 ), -m+
Set ΔY1(S+m+1))K to address (xi,
Yl) (i; o, ..., T), then (Xt
+Yi) is the address of the point of interest.

In this way, the output results of the arithmetic processing unit (81) on each bit plane are stored in the second memory (41). By sequentially writing to , spoke registers for the entire screen can be generated.

Note that in the above embodiment, in the address generation section (5),
The first memory (for llK provides a common address for each bit plane) and the second memory (for 41).

We have explained the case where different addresses are supplied to each bit plane, but conversely, for the first memory (1) K,
q! Supplying a different address for each r bit plane, the second
For the memory (41), a similar effect can be achieved by supplying a common address to each bit plane.
1 is a diagram showing the overall configuration of a spoke register generation circuit according to another embodiment of the present invention, and FIG. 4 is a circuit configuration diagram of an address generation section in this spoke register generation circuit. In Figure 4, (S+) is 9m1 memory (1
) address generation circuits 1.0 to 1.7 that supply a different address for each bit plane of the second memory +41 and address generation circuit 2° (52) that supplies a common address to each bit plane of the second memory +41 are timing generators. It is a circuit.

Now, the address supplied to the 5-bit plane of the first memory (1) is (Ul, vt) (i==Q, . . , 7), and the address commonly sent to each bit plane of the second memory (41) is (x
, Y), then the formula 0) becomes. Therefore, for the i-bit square (IK) of the first memory (1), the start address register (511) of the address generation circuit 1.1 (51) is (m-ΔXl - (S+m+
1).

m-Δys ・(S+m+1))Ko,7)'L
/, K(υblind, V1) (O = 0..., 1), and for s2 memory (41, address generation circuit 2
Set the start address register (511) of (51) to (
0, 0) to generate the address (x, y).

〔Effect of the invention〕

As described above, according to the present invention, by supplying different addresses for each bit plane to 10,000 units of the first memory and the second memory in the address generating unit, the edge to be held in the 9 local data output unit is Since the direction data area can be reduced, the nine-circuit scale can be made very small.

[Brief explanation of drawings]

FIG. 1 is an overall configuration diagram of a spoke register generation circuit according to an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing an address generation section of the present invention, and FIG. FIG. 4 is a circuit diagram showing an address generation section of a spoke register generation circuit according to another embodiment of the present invention, and FIG. Figure 6 is a diagram showing the state of data sent to the arithmetic processing unit. Figure 6 is an overall configuration diagram of a conventional spoke register generation circuit. Figure 1 is a circuit configuration diagram showing a local data extraction unit of a conventional spoke register generation circuit. FIG. 9 is a circuit configuration diagram showing an arithmetic processing section of a conventional spoke register generation circuit. FIG. 9 is a circuit configuration diagram showing an address generation section of a conventional spoke register generation circuit. FIG. 10 is a circuit configuration diagram showing an address generation section of a conventional spoke register generation circuit. 11 is a signal state diagram showing control signals generated by the timing generation circuit, FIG. 12 is an explanatory diagram of the edge quantization direction, and FIG. 13 is a bit representation of the edge direction. 14 and 15 are diagrams showing the state of data by a conventional spoke register generation circuit sent from a local data extraction section to an arithmetic processing section. (2) is the local data extraction section, (4) is the second memory, and +51 is the address generation section. In the two figures, the same symbols are as follows. Indicates the same or equivalent part.

Claims (1)

[Claims] a first memory that stores quantized edge directions of a closed-loop shape of an image; a local data extraction section that simultaneously reads out edge direction data of a point sequence according to the quantization direction from the first memory; and this local data extraction section. an arithmetic processing unit that performs an arithmetic operation to generate a spoke register based on edge direction data sent from the arithmetic processing unit; a second memory that stores the contents of the spoke register generated from the arithmetic processing unit; the first memory and the first memory; 1. A spoke register generation circuit characterized in that one of the two memories is provided with an address generating section that supplies a common address to each bit plane, and the other one supplies a different address for each bit plane.