JPS58114176A - Pattern recognizing device - Google Patents

Pattern recognizing device

Info

Publication number
JPS58114176A
JPS58114176A JP56214032A JP21403281A JPS58114176A JP S58114176 A JPS58114176 A JP S58114176A JP 56214032 A JP56214032 A JP 56214032A JP 21403281 A JP21403281 A JP 21403281A JP S58114176 A JPS58114176 A JP S58114176A
Authority
JP
Japan
Prior art keywords
size
memory
address
lateral
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56214032A
Other languages
Japanese (ja)
Other versions
JPH0234074B2 (en
Inventor
Eiichiro Yamamoto
山本 栄一郎
Yukikazu Shiyouyama
蕉山 幸和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56214032A priority Critical patent/JPS58114176A/en
Publication of JPS58114176A publication Critical patent/JPS58114176A/en
Publication of JPH0234074B2 publication Critical patent/JPH0234074B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06VIMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00Arrangements for image or video recognition or understanding
    • G06V10/20Image preprocessing
    • G06V10/32Normalisation of the pattern dimensions

Abstract

PURPOSE:To prevent the lowering of the recognition rate even if the size of an input pattern is changed, by detecting the longitudinal size and the lateral size of the inputted pattern and converting addresses of a memory in accordance with size by an address conversion table. CONSTITUTION:Lateral and longitudinal start addresses and end addresses obtained by a circuit for detecting the size of a pattern are inputted to subtractors 31 and 32 respectively to calculate the lateral size and the longitudinal size of the pattern; and when the size is determined, counters 33 and 34 generate lateral and longitudinal addresses of a normalized memory 35. A lateral address of a video memory corresponding to the lateral address of the memory 35 is generated by use of the subtractor 31, an address conversion table 36, and an adder 37. In the table 36, the lateral size and the value of the counter 33 are used as addresses. Consequently, when the value of the memory 35 is increased successively, contents of a video memory 38 corresponding to the memory 35 are read out. The similar operation is performed in respect to the longitudinal address, and thus, the size of the pattern is normalized.

Description

【発明の詳細な説明】 (2)発明の技術分野 本発明は文字や数字を含む図形の認識装置に関する。[Detailed description of the invention] (2) Technical field of the invention The present invention relates to a recognition device for figures including letters and numbers.

(2)従来技術と問題点 従来の図形認識装置においては、入力図形の大きさがま
ちまちであると認識性能が著しく低下する欠点があり九
(2) Prior Art and Problems Conventional figure recognition devices have the disadvantage that recognition performance is significantly degraded when the input figure size varies.

(3)  発明の目的 本発明の目的は入力図形の大きさが変化しても認識性能
を低下させることのない図形認識装置?提供することK
ある。
(3) Purpose of the Invention The purpose of the present invention is to provide a figure recognition device that does not reduce recognition performance even if the size of the input figure changes. K to provide
be.

(4)  発明の構成 本発明は図形認識装置において、入力図形全記憶するメ
モリと、この入力された図形の縦および横の大きさを検
出する手段とこの縦および横の゛大きさに従ってメモリ
のアドレスを変換するアドレス変換テーブルを有するこ
と全特徴とする。
(4) Structure of the Invention The present invention provides a figure recognition device that includes a memory for storing all input figures, a means for detecting the vertical and horizontal sizes of the input figures, and a means for detecting the vertical and horizontal sizes of the input figures. The entire feature is that it has an address conversion table for converting addresses.

(6)発明の実施例 第1図は本発明の詳細な説明する図である。(6) Examples of the invention FIG. 1 is a diagram explaining the present invention in detail.

第1図(a) K示すように入力され要因形はまずビデ
オメモリlに格納され、ビデオメモリ内を走査するとと
くより入力図形の横スタートアドレスH8A 。
The input figure as shown in FIG. 1(a) K is first stored in the video memory 1, and when the video memory is scanned, the horizontal start address H8A of the input figure is found.

横エンドアドレスHEム、縦スタートアドレスVSム、
縦エンドアドレスVICAt−検出して入力図形の横の
大きさWX、縦の大きさWYt−求める。
Horizontal end address HE, vertical start address VS,
The vertical end address VICAt is detected and the horizontal size WX and vertical size WYt of the input figure are determined.

この図形を第1図(b)に示すように横の大きさNX。The horizontal size of this figure is NX as shown in FIG. 1(b).

縦の大きさNYとなるように正規化を行なおうとすれば
ビデオメモリから図形の部分を読出しNX/WX、NY
/WYの倍率で縮小拡大を行なえばよい0 第1図(1))の図形は正規化メモリ内に格納されてい
るO 42図に図形の大きさfr検出する回路を示す。
If you want to normalize so that the vertical size is NY, read the graphic part from the video memory and write NX/WX, NY.
The figure shown in FIG. 1 (1) is stored in the normalized memory. Figure 42 shows a circuit for detecting the size fr of the figure.

第2図の1はビデオメモリであシ、これを21゜220
ように4黄方向に読み出す。読み出されたビデオ情報は
フリップ・フロップ23に入力され、亡の出力に図形の
部分(論理1)が出てくるとオフになり、ゲート2によ
り、レジスタ25へのセット信号?以後阻止する。した
がってレジスタ25には最初に図形部分が出現したとき
のメモリアドレスがセットされることになるレジスタ2
6には図形部分が出てくるごとにメモリアドレスがセッ
トされるので、ビデオメモIJl’tすべて読み出し友
時点で図形部分が最後に出現し念ときのメモリアドレス
がセットされていることになる。伺27rJインバータ
である。横方向のスタートアドレス。
1 in Figure 2 is a video memory, which is set at 21°220
4. Read in the yellow direction. The read video information is input to the flip-flop 23, which is turned off when the graphic part (logic 1) appears at the final output, and the gate 2 sends a set signal to the register 25. I will prevent it from now on. Therefore, the memory address when the graphic part first appears is set in register 25.
6, a memory address is set each time a graphic part appears, so when the video memo IJl't is all read out, the graphic part appears last and the memory address just in case is set. It is a 27rJ inverter. Horizontal start address.

エンドアドレスも同様にして求めることができる。The end address can also be found in the same way.

第2図の図形の大きさを検出する回路で得られた涌方向
及び一方向のスタートアドレス、エンドアドレスにそれ
ぞれ第3図の減算器31および32に入力され、図形の
横方向の大きさおよび縦方向の大きさが算出される。横
方向および縦方向の大きさが決定されると、カウンタ3
3および34が正規化メモリ35の横アドレスおよび縦
アドレスを生成する。今、横アドレスについて考えると
、正規化メモリ35の横アドレスに対応するビデオメモ
リの横アドレスが減算器31、アドレス変換テーブル3
6、加算器37を使って生成される。
The start address and end address in the horizontal direction and one direction obtained by the circuit for detecting the size of the figure in FIG. 2 are respectively input to the subtracters 31 and 32 in FIG. The vertical size is calculated. Once the horizontal and vertical dimensions are determined, the counter 3
3 and 34 generate horizontal and vertical addresses of the normalized memory 35. Now, considering the horizontal address, the horizontal address of the video memory corresponding to the horizontal address of the normalization memory 35 is the subtracter 31, the address conversion table 3
6. Generated using adder 37.

アドレス変換テーブル36は横方向の大きさとカウンタ
33の値會テーブルのアドレスとしており、横方向の大
きさが同じものについて、カウンタの値(正規化メモリ
の横アドレス)に対するビデオメモリの横アドレスが記
入されている。し念がって正規化メモリのアドレスを順
次増加してゆくと正規化メモリに対応するビデオメモリ
3日の内容が読み出されることになる。尚36’、3’
7’は夫々縦アドレス用のアドレス変換テーブルおよび
加算器である。これにより図形の大きさ會正規化するこ
とができる。
The address conversion table 36 uses the horizontal size and the address of the counter 33 value table, and for items with the same horizontal size, the horizontal address of the video memory is entered for the counter value (horizontal address of the normalized memory). has been done. If the address of the normalized memory is sequentially increased to be careful, the contents of the video memory corresponding to the normalized memory for three days will be read out. 36', 3'
7' are an address conversion table and an adder for vertical addresses, respectively. This allows the size of the figure to be normalized.

(6)発明の効果 本発明によれば入力図形0正規化が”ic、F、、、i
、、+7)で、入力図形の大きさがまちまちであっても
認識性能ケ低下することがない。
(6) Effects of the Invention According to the present invention, input figure 0 normalization is “ic,F, ,i
,,+7), the recognition performance does not deteriorate even if the sizes of the input figures vary.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の詳細な説明する囚、第2図は本発明の
一実施例において図形の大きさを検出する回路を示す図
、83図は本発明の一実施例′において図形の大きさを
正規化するための回路を示す図である。 1.38:ビデオメモリ、35:正規化メモリ、i、−
W、3  j (υ) 第1図 Cb)
Figure 1 is a detailed explanation of the present invention, Figure 2 is a diagram showing a circuit for detecting the size of a figure in an embodiment of the present invention, and Figure 83 is a diagram showing the size of a figure in an embodiment of the present invention. FIG. 3 is a diagram showing a circuit for normalizing the size. 1.38: Video memory, 35: Normalized memory, i,-
W, 3 j (υ) Figure 1 Cb)

Claims (1)

【特許請求の範囲】[Claims] 入力図形を記憶するメモリと、この入力された図形の縦
および横の大きさを検出する手段と、この縦および横の
大きさく従ってメモリのアドレスを変換するアドレス変
換テーブルを有することを特徴とする図形i!識架装置
It is characterized by having a memory for storing an input figure, a means for detecting the vertical and horizontal sizes of the input figure, and an address conversion table for converting the address of the memory according to the vertical and horizontal sizes. Shape i! Identification device
JP56214032A 1981-12-26 1981-12-26 Pattern recognizing device Granted JPS58114176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56214032A JPS58114176A (en) 1981-12-26 1981-12-26 Pattern recognizing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56214032A JPS58114176A (en) 1981-12-26 1981-12-26 Pattern recognizing device

Publications (2)

Publication Number Publication Date
JPS58114176A true JPS58114176A (en) 1983-07-07
JPH0234074B2 JPH0234074B2 (en) 1990-08-01

Family

ID=16649140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56214032A Granted JPS58114176A (en) 1981-12-26 1981-12-26 Pattern recognizing device

Country Status (1)

Country Link
JP (1) JPS58114176A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172484A (en) * 1986-01-24 1987-07-29 Toshiba Corp Normalization circuit
JPS6457553U (en) * 1987-10-06 1989-04-10
JPH0424781A (en) * 1990-05-15 1992-01-28 Canon Inc Document processor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0491062U (en) * 1990-12-21 1992-08-07

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55110378A (en) * 1979-02-19 1980-08-25 Toshiba Corp Pattern normalization system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55110378A (en) * 1979-02-19 1980-08-25 Toshiba Corp Pattern normalization system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62172484A (en) * 1986-01-24 1987-07-29 Toshiba Corp Normalization circuit
JPS6457553U (en) * 1987-10-06 1989-04-10
JPH0424781A (en) * 1990-05-15 1992-01-28 Canon Inc Document processor
US5784501A (en) * 1990-05-15 1998-07-21 Canon Kabushiki Kaisha Image processing method and apparatus

Also Published As

Publication number Publication date
JPH0234074B2 (en) 1990-08-01

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