KR930010022B1 - All processing circuit for binary picture signal - Google Patents

Abstract

The preprocessor includes a control signal generator (10) for generating control clock signal, a memory (20) for storing pixel data, a first counter (30) for generating memory address signal to output image data to be processed a second counter (40) for generating memory address signal to store external pixel data on the memory (20), a shift register (50) for shifting data sent from the memory (20), a shift register (60) for shifting data in N x N mask by 90 degrees according to a control signal transmitted from the first counter, a programmable logic array (70) for removing noise in the data, a 2 x 1 multiplexer (80) for outputting processed data, a comparator (70) for comparing center pixel data of N x N mask with output data of the 2 x 1 multiplexer (80), and a counter (100) for counting the operation of the comparator (90).

Description

Preprocessing Circuit of Binary Image

1 is an appearance and state diagram of a pretreatment chip according to the present invention.

2 is a block diagram illustrating a schematic configuration of a preprocessing chip according to the present invention.

3 is a block diagram showing a detailed configuration of a preprocessing chip according to the present invention.

4 is a 3 * 3 base mask used in the pretreatment of the present invention.

5 shows a mask to be applied to the noise reduction and thinning of the left direction of the present invention.

FIG. 6 is a circuit diagram illustrating a programmable logic array (PLA) of a mask to be applied to noise reduction and thinning in the left direction of the present invention.

7 shows a 9-bit shift circuit to be applied to the preprocessing circuit according to the present invention.

8 shows a 2 * 1 multipexer to be applied to the preprocessing circuit according to the present invention.

9 shows a comparator of one embodiment to be applied to a preprocessing circuit according to the invention.

10 shows a comparator of an embodiment to be applied to a preprocessing circuit according to the invention.

11a, b, c show basic circuits and symbols to be applied to the preprocessing circuit according to the invention.

Figure 12 shows three bit shift registers to be applied to the preprocessing circuit according to the present invention.

13 shows a 4-bit binary ripple counter to be applied to the preprocessing circuit according to the present invention.

14 illustrates a basic structure of a static random access memory (SRAM) to be applied to a preprocessing circuit according to the present invention.

FIG. 15 shows a 4-bit Mobius counter and its output waveform to be applied to a control signal generator in a preprocessing circuit according to the present invention.

16 shows a control signal generator to be applied to the preprocessing circuit according to the present invention.

17 shows a waveform of a control signal to be applied to a preprocessing circuit according to the present invention.

18 shows an Algorithmic State Machine chart of a preprocessing circuit according to the present invention.

The present invention relates to a recognition circuit of a binary image, and more particularly to a preprocessing circuit of a binary image.

In general, binary image recognition is a basic and very important part of various fields of image recognition, and it is receiving great attention because of necessity and relatively ease of implementation. A binary image is a two-dimensional image composed of a set of objects (black and binary 1) and a background (white and binary 0). The data represented by these binary images are all letters, fingerprints, drawings, etc. Printed circuit board (PCB), printing, medical photography, etc. are very many and can be applied to a wide range of applications. In particular, the character recognition can be made without a keyboard, high-speed input, and can improve the transmission speed of the fax.

The recognition process of binary image is largely divided into preprocessing and recognition stages.

When the image is input by a scanner or the like and quantized (binary imaged), a binary image is obtained. In the preprocessing, the noise of the binary image is removed and sensorization is performed. In the recognition phase, feature points are extracted from thinned images and images are recognized using a predetermined algorithm and technique.

The preprocessing step is essential for effective recognition, and how fast and how effective the preprocessing is depends on the performance of image recognition and facilitates thinning and recognition. In the preprocessing, the thinning, which is the core, is a very important process that facilitates the recognition by skeletal form of the image.

The research on pretreatment has been continued for about 35 years, and various thinning algorithms and techniques have been published mainly due to the active research on thinning. Most preprocessing is done in software, and many of the algorithms studied are based on software processing. However, when implemented in software, the speed of execution is very slow due to many repetitive operations and memory accesses, and even if used in a parallel processing computer, the speed is limited and does not reach the practical speed.

Therefore, the need to improve the speed by implementing the pre-processing (noise removal and thinning) in hardware (hardware) has emerged greatly, and active research is being made in recent years.

The present invention implements the pre-processing algorithm described in the already filed domestic application No. 91-4637 in hardware.

An object of the present invention is to provide a preprocessing circuit having a high performance speed.

Another object of the present invention is to provide a preprocessing circuit with simplified hardware.

In order to achieve the above object, the binary image preprocessing circuit includes a storage means for reading or writing pixel data, and inputting data from the storage means to determine neighboring pixels adjacent to a central pixel in a 3x3 window. And a preprocessing means for performing noise reduction and thinning while rotating by 90 degrees, and a control means for generating a clock suitable for the storage means and the preprocessing means.

Referring to the accompanying drawings, the configuration and operation of the preprocessing circuit of the present invention will be described.

1 is a diagram showing the appearance and state of the preprocessing chip according to the present invention. The clear signal P-Clear performs a function of resetting the chip as a pulsed signal. The idle signal is a stable signal and indicates whether the chip is in an operating state. The data input signal (P-Date In) is a pulsed signal that performs 32bit data input to the chip through a 32bit I / O bus.

The ready-for-out signal is a stable signal indicating that the preprocessing of the data has been performed and waiting for the output of the data. The data output signal (P-Date Out) is a pulsed signal and performs a function of outputting 32-bit data through a 32I / O bus. When the clear signal P-Clear is applied, the chip is reset and enters an idle state, which is not operating.

When a data input signal (P-Date-In) is applied, a data input state is input to input data through a 32-bit I / O bus.

When data is input, the clock signal (Clock) to the execution state (Execution State) to perform the preprocessing operation. When the preprocessing operation is completed, a ready-for-out signal is generated and a ready state for date output is output. When the data output signal (P-Date-Out) is applied, the data is output to the data output state (Data Output State) through the 32-bit I / O bus. After that, the same operation is performed repeatedly.

2 shows a schematic configuration of a preprocessing circuit according to the present invention, a control signal generator 10 for generating a control clock for controlling a system, a storage means 20 for storing pixel data from the outside, A first counter 30 generating a memory address for outputting data to be preprocessed to the storage means 20 and generating a control signal, and inputting pixel data from the outside into the storage means 20, and preprocessing A second counter 40 for generating a memory address for inputting data to which data is to be performed, a shift resist 50 for shifting data from the storage means 20, and an N × N mask to the shift register. A shift register 60 for shifting the data in the 90-degree direction by the control signal of the first counter and data from the shift register are inputted. Is a programmable logic array (PLA) 70 that performs noise canceling and thinning, and a 2 * 1 multiplexer that outputs a noise canceling result or a thinning result by a control signal of the first counter. 80, a comparator 90 for comparing the center pixel value in the N × N mask resulting from the multiplexer 80, and the number of times the comparator 90 is performed It consists of a third counter 100 for counting.

3 shows a detailed configuration of the preprocessing circuit according to the present invention, which preprocesses 32x32-bit pixel data and rotates the 3x3 mask by 90 degrees while windowing the telephone station for left, upper, right and lower sides. A circuit for performing noise reduction and thinning is shown. In order to understand the overall configuration and operation of FIG. 3, the configuration and operation of each individual device will be described first.

4 shows a 3 * 3 base mask. Eight neighboring pixels n1, n2, n3, n4, n5, n6, n7, n8 exist while rotating from the top left to the right about the center pixel P. 5 is a diagram illustrating a left-handed removal and thinning mask according to the present invention, and the following cases are defined as noise.

First, one isolated pixel (mask NA of FIG. 5), second, when two pixels are separated apart (mask NA of FIG. 5), and third, pixel protruding in one diagonal direction (mask NA of FIG. 5) Fourth, the pixel (mask NB of FIG. 5) which protrudes in one orthogonal direction.

Based on the above conditions, the noise canceling tag (NTAG) for the left direction is obtained. NTAG = NA or NB

n ₁ ', n ₂ ', n ₃ ', n ₄ ', n ₅ ', n ₆ ', n ₇ ', n ₈ ' + n ₁ ', n ₂ ', n ₂ ', n ₄ ', n ₅ ', n ₆ ', n ₇ ', n ₈ '

= n ₁ ', n ₂ ', n ₆ ', n ₇ ', n ₈ '(n ₃ ' + n ₃ , n ₄ , n ₅ )

= n ₁ ', n ₂ ', n ₆ ', n ₇ ', n ₈ '(n ₃ ' + n ₄ , n ₅ )

NTAG '= P (n ₁ + n ₂ + n ₆ + n ₇ + n ₈ (n ₃ + n ₄ n ₅ )')

= P (n ₁ + n ₂ + n ₆ + n ₇ + n ₈ + n ₃ (n ₄ , n ₅ ) ')

= P (n ₁ + n ₂ + n ₆ + n ₇ + n ₈ + n ₃ n ₄ 'n ₃ n ₅ ')

It can be expressed as a logical expression such as

With the thinning algorithm, the mask can be removed by converting it to 0 when the mask's central pixel is 1.

First, it must be a border pixel (mask TA); second, it must not be an arc pixel (mask TB, TC). Third, it must not be a terminal pixel (mask TO).

When the three conditions are satisfied at the same time, removing the central pixel preserves the connection and does not deform the characteristics of the pattern. If you design a mask that satisfies the above conditions and scan the binary image according to the algorithm and procedure, you can determine whether to remove the pixel by matching the pixel to the mask. Based on, we get a thinning tag (TTAG) for the left direction,

TTAG = TA and (not TB) and (not TC) and (not TD)

= (n ₄ n ₈ ') (n ₁ n ₂ ' n ₄ n ₈ ') (n ₄ n ₆ ' n ₇ n ₈ ') (n ₂ ' n ₃ 'n ₄ ' n ₅ 'n ₆ ' n ₈ ')

= n ₄ n ₈ '(n ₄ n ₈ ' (n ₁ n ₂ '+ n ₆ ' n ₇ + n ₂ 'n ₃ ' n ₅ n ₆ )) '

= n ₄ n ₈ '(n ₂ (n ₁ + n ₃ ' n ₅ 'n ₆ ') + n ₆ 'n ₇ '

TTAG '= P (n ₄ n ₈ ') 'n ₂ ' (n ₁ + n ₃ 'n ₅ ' n ₆ ') + n ₆ ' n ₇ )

= P (n ₄ '+ n ₈ + (n ₁ n ₂ ' + n ₂ 'n ₃ ' n ₅ 'n ₆ ' + n ₆ 'n ₇ ))

= P (n ₄ '+ n ₈ + n ₁ n ₂ ' + n ₂ 'n ₃ ' n ₅ 'n ₆ ' + n ₆ 'n ₇ )

It can be expressed as a logical expression such as

Figure 6 shows the noise reduction and thinning logic in PLA (Programmable Logic Array, PLA), which can be easily implemented and can be easily modified by adding a new mask, and also reduces the chip area required. There is an advantage. The sixth diagram and the noise reduction and thinning circuit are rotated by 90 degrees clockwise in the order of left (west), upper (north), right (east), and lower (south) in four subcycles. Perform noise reduction and thinning while changing. A 9-bit shift circuit is used to support 4 subcycles, and in each direction, parallel processing is possible for all pixels. If the noise canceling tag (NTAG) and the thinning tag (TTAG) are 1, the corresponding pixel is removed. .

7 shows a 9-bit shift circuit, in which eight neighboring pixels (n ₁ , n ₂ , n ₃ , n ₄ , n ₅ , n ₆₎ input when the control signals clso and clsl are "0 0". NMOS transistors 110 and 111 for directly outputting n ₇ and n ₈ , and NMOS for rotating eight neighboring pixels 180 degrees to the right when the control signals clso and clsl are "10". Transistors 110 and 113, two inverters 114 for inverting the control signals clso and clsl, eight inverters 115 for buffering the input signal, and buffers for the output signal. It consists of eight inverters 116 and rotates eight neighboring pixels excluding the center pixel P by 90 degrees counterclockwise.

8 shows a 2 * 1 multiplexer 2 comprising two CMOS transfer gates 117 for selectively outputting a noise canceling tag NTAG 'or a thinning tag TTAG' value by a control signal S. FIG. * 1 multipexer).

9 shows a 30-bit comparator. When the input signals P and TAG are " 0 ", the PMOS transistors 118 and 119 are turned on and the NMOS transistors 128 are turned on to " 1 " And the input signals P and TAG are " 0 1 ", turn on the PMOS transistors 118 and the NMOS transistors 120 and turn off the NMOS transistors 120 to the output. When the signal of "0" is generated and the input signals P and TAG are "1 0", the PMOS transistors 121 and the NMOS transistors 119 are turned on and the NMOS transistors 122 are turned off and output. Generates a signal of "0", and when the input signal (P, TAG) is "1 1", the NMOS transistors 121 and 120 are turned on and the NMOS transistors 122 are turned on to output "1" to the output. Generate a signal. In other words, if the input signals P and TAGP are the same, an output signal of "1" is generated, and if the input signals P and TAG are different, an output signal of "0" is generated. If each bit value is the same, a value of "1" is output. If each bit value of the input 30 bits is different, a value of "0" is output.

FIG. 10 shows another embodiment of a 30-bit comparator, which can be replaced by the dotted line in FIG. An input signal P for generating a control signal for turning on or off the CMOS transfer gate 123 for outputting the input signal TAG and an output signal of the inverter 124. And the value "1" of the inverted input signal TAG appears when the CMOS transfer gate 123 is turned off, and the value "0" of the inverted input signal TAG appears in the output when "1". In the case of "1 0", the value "1" of the input signal TAG 'appears at the output, and in the case of "1 1", the value "1" of the input signal TAG' appears at the output. In other words, it operates in the same manner as the circuit of FIG.

11 (a), (b) and (c) show a logic circuit diagram, a function table, a logic symbol, and an operation timing diagram of a D flip flop and a T flip flop used in the present invention. It is a well-known circuit diagram.

FIG. 12 shows 3-bit shift registers using the D flip-flops 126, and shifts each 32-bit pixel data in response to the control signal E1.

FIG. 13 shows a binary ripple counter using the T flip flops 127 used in the present invention. The clock signal CLK is applied to the clock signal terminal CLK of the T flip flop and the output terminal ( Q) generates the least significant bit signal Q0, and the inverted output terminal Q is applied to the clock signal terminal of the next T flip-flop to continuously increase the number of bits to count n bits. 127) by connecting.

14 shows a basic structure of a static random access memory (SRAM) used in the present invention.

14 shows a 4-bit binary ripple counter to be applied to the preprocessing circuit according to the present invention. By connecting n, n-bit counters can be configured.

FIG. 15 shows the configuration of the 4-bit Mobius counter used to generate the control signals of the present invention. The clock signal CLOCK is applied to the clock signal terminals of the four D flip-flops 126. Connect the output signal of D to the data input terminal (D) of the rear stage, and the inverted output terminal signal (Q) of the last stage to the data input terminal (D) of the first stage, and then output the output signal ( Q0, Q1, Q2, and Q3) are generated.

The output waveform and the output state according to the clock signal (CLOCK) are also shown.

16 shows a control signal generator of the present invention. The pulsed idle signals P and Idle are applied to the data input terminal D and the clock signal terminal CK of the D flip-flop 128 to generate an idle signal Idle. When the pulsed clear signal P Clear is applied to the preset terminal PRESET of the D flip-flop 128, the idle signal Idle becomes "1" and resets the chip. When the pulsed data input signal P Data In is applied to the clear signal terminal CLEAR of the D flip-flop 128, the idle signal Idle becomes a " 0 " state to indicate that it is in an operating state. When the pulsed data input signal P Data In is applied, the idle signal Idle becomes a " 0 " state to indicate that it is in an operating state. The pulsed data input signal P Data In is applied to the data input terminal D and the clock signal terminal CK of the D flip-flop 129 to apply a " 1 " state signal to the PLA1 130. The PLA1 130 inputs the output signals Q0, Q1, Q2, and Q3 of the 4-bit Mobius counter 131 to output the signals. Generates. The output signal After the operation is completed by " 1 ", the pulsed execution signal P Execute is applied to the data input terminal D and clock signal terminal CK of the D flip-flop 132 to " 1 " state through the output terminal Q. Generates an Execute signal. The execute signal Execute is applied to the CREE signal terminal CLR of the D flip-flop 129 to clear the D flip-flop 129 and to the PLA2 133 at the same time. The PLA2 133 inputs the output signals Q0, Q1, Q2, and Q3 of the 4-bit Mobius counter 133 to output the output signals. Occurs. After performing the operation, the ready-for-out signal _{(Ready-for-Out)} is generated is applied to a clear signal terminal (CLK) of the D flip-flop 132 clears the D flip-flop 132. After that, when the pulsed data output signal P _- Data _- Out is applied to the data input terminal D and the clock signal terminal CK of the D flip-flop 134, the output terminal Q is in the " 1 " state. Generates a data output signal (Data Out). Data output signal (Data _- Out) is applied to PLA3 (135) and inputs the output signal (Q0, Q1, Q2, Q3) of the 4-bit Mobius counter 131 output signal Occurs. When the idle signal Idle signal is applied to the clear signal terminal CLK of the D flip flop 134, the D flip flop 134 is cleared.

FIG. 17 shows waveforms of control signals generated by the control signal generator of FIG.

18 degrees known for defining an algorithm for pre-processing circuit according to the present invention Leeds dynamic state machine chart (Algorithmic State Machine chart: ASM chart ) for showing such, pulse sex data input from the outside in the idle state (135) (P _- Data _- In), the data input signal 136 is in the state "1", and when data is input from the outside, the data input state 137 is entered. When the input of data from the outside is completed, an execute signal (Execute) 138 of "1" is generated from inside. Then, the execution state 139 is executed. When the execution is completed, the ready _- for _- out 14 of " 1 " is output to the outside and the ready-state for data out 141 is output. If the data output signal (Data _- Out) is "0" (142), the standby state is continuously maintained, and if pulsed input is received from the outside, the data output signal (Data _- Out) becomes "1", and the output state (Outputstate ( 143) to output data to the outside.

When the output of the data is completed, an idle signal (Idle) 144 of " 1 " is generated to be output to the outside and back to the idle state 135 again. By repeatedly performing such an operation, the preprocessing of all data is completed.

3 shows a preprocessing circuit according to the present invention, the configuration and function of which are as follows.

When the NOR gate 145 is applied with a pulsed data input signal (P _- Data _- In), an execution signal (P Execute), an idle signal (P-Idle), and a ready-for-out signal (Ready _- for _- Out) A signal of " 0 " is output, the 5-bit address counter 146 is set via the inverter 147, and the 8-bit address counter 148 is reset. AND gate 150 is a chip select signal. And light enable signal When all are "1", the signal of "1" is output. NOR gate 150 is " 1 " through inverter 151 when output signal of AND gate 150 is " 1 " or data input signal (Data _- In) or data output signal (Data _- Out) is " 1 ". It outputs a signal of the to enable the three-state buffer 152 to output the lower 5-bit signal of the 8-bit address counter 148.

The AND gate 153 is a chip select signal And light enable signal If both are "0", a signal of "1" is output. The AND gate 154 outputs a signal of "1" when both the output signal of the AND gate 153 and the output signal of the NOR gate 150 are "1", thereby enabling the three-state buffer 155 to be 5 The 5-bit signal of the bit address counter 146 is output. That is, the AND gate 153, the AND gate 149, the NOR gate 150, and the NAD gate 154 control the write address of the SRAM 156, and the AND gate 149 and the NOR gate 150. The inverter 151 functions to control the read address of the SRAM 156. Counting is started by the control signal EO applied to the clock signal terminal CK of the counters of the 5-bit address counter 146 and the 8-bit address counter 148. The SRAM 156 functions to output 32x32 bits of pixel data by the output signal of the 5-bit counter 146. The AND gate 15 outputs a pulsed execution signal P _- Execute when the sixth bit output signal of the 8-bit counter 148 is "1" and the data input signal Data _- In is "1". The AND gate 158 outputs a pulsed idle signal P _- Idle when the sixth bit output signal of the 8-bit count 148 is "1" and the data output signal Data _- Out is "1". The D flip-flop 159 generates a control signal (S) when the eighth bit output signal is "1". The D flip-flop 159 is cleared by the pulsed execution signal P _- Execute. The D flip-flops 160 store and shift 32 × 32-bit pixel data stored in the SRAM 156 by the control signal E1. The 9-bit shift circuits 161 use the signals (clso, clsl) output from the sixth seventh bit of the 8-bit counter 148 to remove noise in three directions: left, top, right, and bottom. Function to perform line drawing. The connection between the D flip-flops 160 and the 9-bit shift circuits 161 includes eight neighboring pixels n ₁ , n ₂ , n ₃ , n ₄ , arranged in the 3 × 3 basic mask of FIG. ₄ . n ₅ , n ₆ , n ₇ , n ₈ ) are connected in the specified order. The first and last bits of the D flip-flops 160 are tied to the ground terminal Vss. This is because there is no pixel data in these bits. Noise reduction and thinning The PLA 62 inputs the output signals from the 9-bit shift circuits 161 to perform noise reduction and thinning. The multiplex 163 selectively outputs data which has been canceled by the control signal S of the control signal 163 or thinned data. The 30-bit comparator 164 inputs the output signal of the multiplexer 163 and the center pixel signal P to output a signal of "1" in the same case and a signal of "0" in other cases.

The AND gate 165 outputs a signal of "1" when both the control signal E2 and the output signal of the 30-bit comparator 164 are "1". The 8-bit counter 166 starts counting by the output signal of the AND gate 165. Inverter 167 inverts the 30-bit comparator 164 and the output signal. The OR gate 168 outputs a signal of "1" when one of the output signal of the inverter 167 or the pulse execution signal (P _- Execute) is "1" to clear the 8-bit counter 166. .

D flip-flop 169 is when the 8-th bit signal of the 8-bit counter 166 is "1", the ready-for-out signal is generated for (Ready _{- -} for Out) and pulse sex data input signals (P _- Date _- Cree by In). The tri-state buffer 170 is enabled by the control signal W, and stores the output signal of the multiplexer 163 in the SRAM 156 through the 32-bit I / O bus.

The operation of the preprocessing circuit of the present invention shown in FIG. 3 is as follows.

The idle state generates an idle signal Idle when a pulsed clear signal P-Clear is applied to the preset signal terminal PRE of the D flip-flop 128. The data input state is a pulse input data input signal (P-Data-In) is applied to the data input signal terminal (D) of the D flip-flop 129, PLA1 (130) is a control signal of FIG. field Occurs. When the pulsed data input signal P _- Data _- In is applied to the NOR gate 145, the 5-bit counter 146 is set to "1", and the 8-bit counter 148 is reset to "0". Chip Select Signal And enable signal When all are "0", the output signal of the inverter 151 becomes "1" to enable the three-state buffer 152. Chip Select Signal Becomes "1" and the control signal EO becomes "1" after one clock cycle, the 8-bit counter 148 generates an address of "0" through the tri-state buffer 152 and the chip select signal. And light enable signal Is " 0 ", 32-bit data is written to " 0 " of the SRAM 156 through the I / O bus. Thus, the 8-bit counter 148 generates an address of " 11111 " and writes 321 bits of data to the address " 11111 ", thereby completing the write operation of 32x32 bits of data. When data input is completed, the sixth bit signal of the 8-bit counter 148 becomes "1", and the AND gate 157 generates a pulsed execution signal (P _- Execute). The execute state is the D flip-flop 159 and the 8-bit counter when the pulsed execution signal P-Execute is applied to the clear signal terminal CLR and the OR gate 168 of the D flip-flop 159. Clear 166 and input to NOR gate 145 to set 5-bit counter 146 and reset 8-bit counter 148. Also, when applied to the data input signal terminal D of the D flip-flop 132, the PLA2 132 is the control signals of FIG. Occurs. Chip Select Signal Is "0" and the write enable signal is Is " 1 " enables the tri-state buffers 152. When the control signal E0 becomes "1", the 8-bit counter 148 enables the three-state buffers 152 with 5-bit signals of "0". When the control signal E0 becomes "1", the 8-bit counter 148 inputs 5-bit signals of "0" to the SRAM 156 through the tri-state buffy 152. SRAM 156 stores 32-bit data at address "0 " in D flip-flop 160 and shifts when control signal E1 becomes " 1 ". The sixth and seventh bits of the 8-bit counter 148 are in the state of "0" and are applied to the data input terminal D and the clock signal terminal CK of the D flip-flop 159 to generate the control signal S. do. The control signal S is applied to the multiplexer 163 to output a noise canceling tag signal. At this time, chip select signal Becomes "1" and the light enable signal Maintains " 1 " to disable the tri-state buffers 152 and 155. Chip Select Signal And light enable signal When both are in the "0" state, the control signal W becomes "1" to enable the three-state buffers 155. The control signal W also enables the three state buffers 170. The 5-bit output signals " 11111 " of the 5-bit counter 146 are input to the SRAM 156 through the tri-state buffers 155. The SRAM 156 writes the noise canceling tag signal to the SRAM 156 through the tri-state buffer 170 at the address "11111". The noise canceling tag signal is also compared with the center pixel values in the 30 bit comparator 164. If the control signal E2 becomes "1" and the output signal of the 30-bit comparator 164 is "1", the 8-bit counter 166 counts.

If the output signal of the 30-bit comparator 164 is "0", 8 bits 166 are cleared. In noise reduction, four sub cycles are repeated once, but when thinning is performed, 32 bits are sequentially received in 32 three-bit shift registers, and four sub cycles are repeatedly performed until the center pixel is no longer removed. It goes through a series of iterations.

The 9-bit shift circuits 161 repeats 4 sub cycles by the two bit signals cls0 and cls1. In other words, the two bit signals cls0 and cls1 are processed in the left direction when " 0 ", " 1 " in the upper direction, " 10 " A 30 bit comparator 164 is used to determine whether the central pixel is no longer removed. The input data of the 30-bit comparator 164 is the 30-bit signals TAG1 ', TAG2', ... which have passed through 30 central pixels (P1, P2, ....., P30) and the multiplexer 163. If each of the corresponding bits of .TAG30 ') is compared and are all equal, " 1 " is output to increase the 8-bit counter 166 by one. If any one is different, " 0 " is output to clear the 8-bit counter 166. Finally, 4 * 32 times 1 is output from the 30-bit comparator 164 to clear the 8-bit counter 166. Finally, when 4 * 32 times 1 is output from the 30-bit comparator 164 and becomes the 8th bit signal " 1 " of the 8-bit counter 166, the ready-for-out signal is read through the D flip-flop 169. for-Out) becomes "1".

This means that noise reduction and thinning are over. That is, it becomes a ready state for data output. The ready-for-out signal is applied to the clear signal terminal CLR of the D flip-flop to clear the D flip-flop 132.

It is also applied to the NOR gate 145 to set the 5-bit counter 146 and clear the 8-bit counter 148. The data output state (Data-Output-State) is a pulsed data output signal (P-Data-Out) is applied to the data input terminal (D) and the clock signal terminal (CK) of the D flip-flop 134 from the outside, PLA3 135 is the control signal of FIG. Occurs. Chip Select Signal Is "0" and the reset enable signal Is 1, the tri-state buffer 152 is enabled, and when the control signal E0 is " 1 ", a signal of " 0 " is generated.

When the address "0" of the SRAM 156 is applied, 32-bit data stored at the address "0" is output to the outside of the chip through the 32-bit I / 0 bus. When the 8-bit counter 148 outputs "11111", the SRAM 156 outputs 32-bit data stored at the address "11111" and the data output state is completed. When the sixth bit of the 8-bit counter 148 becomes "1", the AND gate 158 generates a pulsed idle signal P-IDLE and returns to an idle state.

The preprocessing circuit according to the present invention takes a lot of time in the process of removing the noise and thinning of the binary image when processed by software. However, the preprocessing circuit can be implemented at high speed by hardware.

It can be widely used in computers that process binary images.

Can be used for high speed font generators.

Claims (32)

A storage means for reading or writing the pixel data, inputting the pixel data from the storage means, and removing noise with respect to the left side, the upper side, the right side, and the lower side while rotating the neighboring pixels adjacent to the center pixel in the 3 * 3 window by 90 degrees; And preprocessing means for performing thinning, and control means for generating a clock signal suitable for said storage means and said preprocessing means. The method of claim 1, wherein the storage means (20) further comprises a first address generating means (30) for reading pixel data, and a second address generating means (40) for writing pixel data. Preprocessing Circuit of Binary Image. 3. The preprocessing circuit of a binary image according to claim 2, wherein an address generated from said first address generating means and said second address generating means (30, 40) has a difference of one. 3. The first address generating means (30) according to claim 2, wherein the first address generating means (30) generates an address for inputting pixel data from the outside into a corresponding address of the storage means, and the noise is removed or thinned by the preprocessing means. A preprocessing circuit for binary images, characterized by generating an address for storing data. The preprocessing circuit of a binary image according to claim 2, wherein the second address generating means (40) generates an address for outputting pixel data to the outside, and generates an address for outputting data to the preprocessing means. . 3. The storage device according to claim 2, wherein the storage means (20) comprises address control means (145, 147, 150, 151, 153, 154,) for controlling the output of the first address and the second address generating means (30, 40). 152, 155, further comprising a binary image pre-processing circuit. The preprocessing circuit of a binary image according to claim 6, wherein the first address and the second address generating means (30, 40) comprise binary ripple counters (146, 147) controlled by a first control signal. The method of claim 1, wherein the preprocessing means is regularly connected to the shift means 160 and the shift means 160 for storing and shifting pixel data from the storage means 20 in response to a second control signal. Noise removal and thinning are performed on the rotating means 161 for rotating the neighboring pixels to the left, the upper side, the right side, and the lower side of the 3 * 3 window by the first signal, and the data output from the rotating means 161. Execution means 162, selection means 163 for selectively outputting the noise canceling or thinning result by a second signal, and storing data from the selection means by the third signal in the storage means. A gating means 170, a comparing means 164 for comparing the data from the selecting means 163 with the central pixel, and a count for counting the number of times of execution and for notifying that the preprocessing is finished. Preprocessing circuit of a binary image, characterized in that it comprises a setting means (166). 10. The preprocessing circuit of a binary image according to claim 8, wherein the shift means (160) consists of three D flip-flops connected in series to an N-bit input / output line. The method of claim 8, wherein the rotating means 161 is the first NMOS transistors for outputting the eight neighboring pixels as it is when the first signal is the first state, the first signal is the second state Second NMOS transistors for rotating the eight neighboring pixels 90 degrees to the right, and third NMOS transistors for rotating the eight neighboring pixels 180 degrees to the right when the first signal is in a third state. And fourth NMOS transistors for rotating the eight neighbors to the right by 270 degrees when the first signal is in the fourth state. The method of claim 8, wherein the execution means 162 comprises one isolated pixel in a 3 * 3 window, one diagonally protruding pixel when two pixels are separated from each other, and one rectangularly protruding pixel. And a thinning circuit which removes a central pixel when the noise removing circuit removes a center pixel and the boundary pixel is not a curved pixel and is not a terminal pixel. 12. The pre-processing circuit of binary image according to claim 11, wherein the noise canceling circuit is composed of PLA. The preprocessing circuit of a binary image according to claim 11, wherein the thinning circuit is composed of PLA. 9. The pre-processing circuit of binary image according to claim 8, wherein the selecting means (163) consists of two CMOS transfer gates. 9. The preprocessing circuit of binary image according to claim 8, wherein the gating means is composed of three state buffers. The method of claim 8, wherein the comparing means 164 is the first PMOS transistors, the second PMOS transistors, and the first NMOS transistors are turned on when the input signal is the first state, the input signal is a second state In this case, the first NMOS transistors turned on, the first NMOS transistors, the second PMOS transistors turned on when the input signal is in the third state, and the first NMOS transistors turned on when the input signal is in the fourth state. And N comparison circuits each consisting of two NMOS transistors. The method of claim 8, wherein the comparing means 164 is a second input signal for generating a control signal for turning on or off the gate of the CMO transmission for outputting the first input signal and the first inverter and the CMOS transmission And N comparison circuits comprising a second inverter for inverting a second input signal for inverting the first input signal when the gate is turned off. 18. The preprocessing circuit of a binary image according to claim 16 or 17, wherein the comparing means (164) further comprises an inverter at an output terminal of the comparing circuits. 18. The preprocessing circuit according to claim 16 or 17, wherein the comparing means (164) outputs a value of 1 when all input signals are the same and a value of 0 when different input signals are different. 9. The pre-processing circuit of binary image according to claim 8, wherein the counting means counts four times the number of addresses. 21. The preprocessing circuit according to claim 20, wherein the counting means (166) comprises a binary ripple counter. The method of claim 1, wherein the control means comprises: first means for generating a clock for data input from the outside, second means for generating a clock for execution of the input data, and outputting the processed data to the outside. And a third means for generating a clock for the binary image preprocessing circuit. 23. The apparatus of claim 22, wherein the first means applies a pulsed data input signal to the data input terminal and the clock signal terminal of the D flip-flop, and is enabled by the output signal of the D flip-flop and output of a 4-bit Mobius counter. And means for generating a first control signal and a signal for controlling the storage means by inputting a signal. 24. The preprocessing circuit of a binary image according to claim 23, wherein said means is comprised of PLA. 25. The output signal according to claim 24, wherein the second means applies a pulsed execution signal to the data input terminal and the clock signal terminal of the D flip-flop, and is enabled by the output signal of the D flip-flop and output signal of the 4-bit Mobius counter. And means for generating first, second and third control signals and a signal for controlling the storage means. 26. The pre-processing circuit of binary image according to claim 25, wherein the means consists of PLA. 23. The output signal according to claim 22, wherein the third means applies a pulsed data output signal to the data input terminal and the clock signal terminal of the D flip flop and is enabled by the output signal of the D flip flop. And means for generating first and seventh signals and a signal for controlling the storage means. 29. The preprocessing circuit of a binary image according to claim 27, wherein said means is comprised of PLA. 28. The method of claim 27, wherein the 4-bit Mobius counter applies a clock signal to the clock signal terminals of the four D flip-flops, connects the output signal of the previous stage to the input terminal of the rear stage and the inverted output terminal signal of the last stage to the first stage. And a 4-bit output signal through the output terminal of each D flip-flop by connecting to the data input terminal of the binary image pre-processing circuit. 23. The method of claim 22, wherein the control means generates an idle signal by applying a pulsed idle signal to a data input terminal and a clock signal terminal of a D flip-flop, and generates an idle signal by applying a pulsed clear signal to a clear signal terminal. And reset means for informing that the operation state is applied by applying a pulsed data input signal to the preset signal terminal. 23. The preprocessing circuit of a binary image of claim 22, wherein the first, second, and third means are enabled sequentially. A preprocessing method of a preprocessing circuit that performs noise reduction and thinning of a picture pattern on a binary image, comprising: a data input step of inputting pixel data from an outside; a neighbor of a neighboring pixel adjacent to a central pixel in a 3 * 3 window A data execution step of performing noise reduction and thinning while rotating the pixels 90 degrees in a clockwise direction, a standby step of preparing data output, and a data output step of outputting data executed externally Pretreatment method on the top.