JPH03100754A - Cpu control system - Google Patents

Abstract

PURPOSE:To take partial charge of a large quantity of information by CPUs to efficiently process the information by interposing dual port RAMs having data channel areas, main RAMs having data channel areas, and sub-RAMs between a main CPU and sub-CPUs. CONSTITUTION:Dual port RAMs 34a to 34n shared among a main CPU 12 and sub-CPUs 22a to 22n, and a main RAM 14 of the main CPU 12, and sub- RAMs 24a to 24n of sub-CPUs 22a to 22n are provided with data channel areas. Completed data from one CPU is stored in dual port RAMs 34a to 34n with numbers of channels in data channel areas as the medium and this data is read in by the other CPU. Thus, a special processing (data check) as conven tional is unnecessary, and hardware and software are simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a control system for a CPU incorporated in a controller or the like that controls the temperature of an extruder or the like.

<Prior Art> In the case of the above-mentioned controller, etc., since the amount of information handled is large, it is necessary to incorporate a plurality of CPUs into the device and operate them independently of each other.

For this reason, conventionally, for example, as shown in FIG.
3. Connect other parts (ROM, I10 board, etc.) 54, and connect the sub CPU 62, sub RAM 63, and other parts (ROM, I10 board, etc.) to the sub data bus 61.
64 is connected, and data exchange between the main data bus 51 and the sub data bus 61 is performed using a dual port RAM.
55 is used.

<Problems to be Solved by the Invention> However, in the case of the control system between the CPUs shown in FIG. Interactions required special processing (eg, data checks).

For example, when the sub CPU 62 stores data 2 bytes at a time in the dual baud RAM 55, taking temperature data of 199°C as an example, it stores 01 in step ■, stores 99 in step ■, and as a result, In step (2), the value 0199 is stored in the dual baud RAM 55.

On the other hand, since the sub CPU 62 and the main CPU 52 each independently process data, the main CPU 52
There is no problem in reading the temperature data as long as 0199 in step (2) is read, but if the main CPU 52 reads the temperature data between the above step and step (2), the data Since the temperature is stored as 0100, there is a possibility that it will be recognized as 100°C. For this reason, it is necessary to read the data multiple times, for example twice, and if the two readings are different, it is necessary to read the data one more time and use the third value (data check).

This process of reading data multiple times is performed by the sub CPU.
The larger the amount of data exchanged between the computer and the main CPU, the more the processing speed of the main CPU decreases.

Furthermore, since the main CPU and sub CPU operate independently of each other, it is necessary for one CPU to monitor the other CPU for malfunctions.

The present invention has been made in view of such conventional problems.

<Means for Solving the Problems> The feature of the present invention is that dual port RAM coexists between the main CPU and one or more sub CPUs.
A data channel area is provided in the main CPU, a data channel area is provided in the main RAM of the main CPU, and a data channel area is provided in the sub RAM of the sub CPU, respectively.
A CPU that performs data input/output between the U and sub CPUs by determining the number of channels in each data channel area.
It is in the U control system.

In the present invention, as described above, the dual-baud RAM having a data channel area, and the main RAM and sub-RAM also having a data channel area are interposed between the main CPU and one or more sub CPUs. With a simple hardware configuration, a large amount of information can be shared between each CPU and processed smoothly and efficiently.

<Embodiment> FIG. 1 shows an embodiment of the CPU control method according to the present invention.

In the figure, 12 is the main CPU 514, the main RAM
, 22a-n are independently controlled by the main CPU 12.
24a to 24a are independent sub CPUs, and 24a-n are sub RAMs.
, 34a-n are dual-baud RAMs shared between the main CPU 12 and each of the sub-CPUs 22a-n.

In the figure, for convenience of explanation, dual baud) RAM 34a
The corresponding storage area 14a of the main RAM 14 is shown enlarged, but other dual port RAM
34b-n, main Rj6M14 storage area 14b-n
The same is true.

In the main RAM 14, there is a sub CPU 2 like this.
Storage areas 14a-n corresponding to 2a-n and storage areas 14x for a large number of data whose input/output is controlled by the main CPU 12 are secured.

Then, the storage area 14a corresponding to the sub CPU 22a
The dual baud) RAM 34a is comprised of an area (upper part in the figure) for reading data from the dual baud RAM 34a, and an area (lower part in the figure) for storing data to be sent to the dual baud RAM 34a.

In addition, the dual port RAM 34a-n is a sub-RA
It corresponds to the number of M24axn, and this sub-RAM24
It has a storage area for data exchange between axn and the main RAM 14.

Furthermore, as is clear from the illustrated dual port RAM 34a, this dual port RAM 34a includes:
It is used when sending data from the sub RAM 24a to the main RAM 14, and is used when sending data from the sub RAM 24a to the main RAM 14.
A data area 51 to which data is written one by one from AM24a in a predetermined order, and a main RAM.
There is a data area 6I-1 which is used when sending data from the main RAM 14 to the sub-RAM 24a, and in which data is written one by one from the main RAM 14 in a predetermined order under the control of the main CPU 12.

In addition, the dual port RAM 34a includes a sub RAM
After data is written from the main RAM 14 to the dual port RAM 34a, the data channel area 1 is where the written data is stored. After data is written from the main RAM 14 to the dual port RAM 34a, the data channel area 1 is where the written data Nα is stored. There is a region 3.

The data channel area 1 corresponds to the data channel area 2 in the main RAMI 4, and the data channel area 3 corresponds to the data channel area 4 in the sub RAM 24a.

Dual port RAM34b~n, sub RAM24b
~ns Main RAM The main RAMs 14b to 14n have a similar configuration.

In the present invention configured as described above, data from, for example, external measuring means is stored in the sub-RAM 24a under the control of the sub-CPU 22a.

After that, the sub CPU 22a performs calculations, controls, etc. based on the data, and at the same time transfers the data to dual baud)R.
Specified data area of AM34a5. ~Write in 7. Further, the number of channels currently written is entered into the data channel area 1.

On the other hand, under the control of the main CPU 12, the dual port R
Specified data area of AM34a5. 7, the number of channels in the own data channel area 2 on the main RAM 14, for example m,
The number of channels in the data channel area l on the dual baud (dual baud) RAM 34a is compared with, for example, l, and the data is read.

The detailed operation during this time is shown in the flowchart of FIG.

This flowchart is basically a program that repeatedly operates every certain fixed period (for example, 200 m5) (however, depending on the load on the main CPU, it may not be executed within this fixed period).

First, in step 1, it is determined whether the number l of channels in data channel area 1 is the same value as the previous sampling. The value of the previous sampling is in the data channel area 2.
Since the number of channels stored in is m, it is a comparison between l and m.

Since the sub CPU 22a always writes data to the dual baud 1-RAM 34a at regular intervals such as 200m5, if the sub CPU 22a is operating normally, the number of channels in the data channel area 1! is sure to be updated, so normally, the answer is NO and the process moves to step 2.

In step 2, the error count value is set to zero (0).

In steps 3 to 7, the latest data in the dual baud RAM 34a is repeatedly read and written to the main RAMI 4 under the control of the main CPU 2.

In steps 3 to 5, the dual port RA to be read this time
Perform calculations to obtain the data area of M34a.

That is, in step 3, 1 is added to the data area m that has been read once before, and in step 4, it is determined whether the addition of 1 exceeds the maximum value n of the data area of the dual baud RAM 34a. If it exceeds, m is set to 1 in step 5. If not, move on to step 6.

In this step 6, the data area m of the dual baud 1-RAM 34a to be read this time determined in steps 3 to 5 above is read, and the data area number that has been read from the data channel area 2 (dual baud) RAM 34a to the main RAM 14a. ) is updated to m.

In step 7, the value of data channel area 2 updated in step 6 (the data area number that has been read from the dual baud RAM 34a to the main RAM 14a) and the value of data channel area l (read from the sub RAM 24a to the dual port RAM 24a) are updated. completed data area number)
If they are the same, it means that all new data on RAM34a (dual baud) has been read.
The process ends at step 11. If it is different, there is new data that has not been read yet, so return to step 3 and repeat steps 3 to 7 until all data is read.

In steps 8 to 1O, abnormality processing is performed in accordance with the flow for performing error processing when the number of channels l in the data channel area 1 is not rewritten. In other words, the number of times YES is determined in step 1 is counted in step 8, and if it exceeds the specified number of times (E) in step 9, it is determined that there is an error such as a failure of the sub CPU, and error processing is performed in step 10. If the specified number of times (E) is not exceeded, the process ends in step 11.

Transfer of data from the main RAM 14a to the sub RAM 24a also uses the number of channels in its own data channel area 4 on the sub RAM 24a, for example m, and the number of channels in the data channel area 3 on the dual port RAM 34a, for example l'. and the same is done.

Next, FIG. 3 shows a specific example in which the CPU 1111 system according to the present invention is applied to a controller for temperature control, etc.

In this controller, 11 is the main data bus of the main system, which includes the main CPU 12, this main CPU
A main ROM 13 stores 12 programs, etc., and a main R stores data, etc. for the main CPU 12.
AM14, various main input boats 161~, 1, various main output boats 17. ~7 etc. are connected respectively.

On the other hand, 21 axn is a sub data bus of a plurality of sub systems a''-n, and these also have sub CPUs 22a-n
, sub ROM 23a-n in which programs etc. of these sub-CPUs 22axn are stored, and sub-CPUs 22a-n.
Sub-RAMs 24a-n in which data etc. for
Various sub-input ports 26 a I#ll ”” n
+#fi, various sub output boats 27a heavy ~, ~n1
~1 etc. are connected respectively.

Between the main data bus 11 of the main system and the sub data buses 21a to 21a to n of the sub system a''-n, the data areas 51#ll+61 to 7, as described above, are provided.
RAMs 34a to 34a, which have data channel areas 1.3, etc. built-in, are connected thereto.

Here, the reason for providing multiple subsystems a''-n is as follows.
This is because, in the case of recent controllers, the amount of data handled has increased dramatically, such as the need to handle a large number of measurement points.

For example, if we take the temperature control of the extruder 40 as shown in FIG. 42 (1) to (7), and a plurality of heaters 43 (1) to 43 (1) to 43 (1) to 42 (7) are used to measure the temperature according to the results. ), it is necessary to heat the desired portions of the extruder 40 in a shared manner.

Therefore, one area is considered to be one channel, and one sub-CPU 22a-n is assigned to, for example, eight channels.

Next, the operation of the controller 41 incorporating the method of the present invention will be explained as follows.

In this controller 41, the main C
The set temperature (
SV), PID constant, time, presence or absence of an alarm, etc. are set, and the contents of these settings are stored in the main RAM 14. Also, the setting values etc. at that time are as follows: Main output port 17.
It is displayed on the front of the instrument through the display unit 7.

The data stored in the main RAM 14 is stored in the main CPU
12 to the dual port RAMs 34a-n, and then to the sub-RAMs 2 of the sub-CPUs 22a-n.
4a-n.

First, in this controller 41, as described above, one sub-system surrounded by the dotted line in FIG. 3 is assigned to a desired part of the extruder 40 as, for example, 8 channels.
Each subsystem operates independently.

For example, in one subsystem surrounded by a dotted line, the subCP
Temperature sensors 42(1)-, 6. Contains data from. For this measured value (pv), for example, 200
Captures each channel once every ms, sub RAM 24
Store it in a. Other subsystems operate similarly.

Data related to temperature also exists in the main RAM 14. For example, setting values (SV), PID constants, etc. are input by key setting of main input ports 161 to 7, stored in main RAM 14, and then written to dual port RAMs 34a to 34n by the action of main CPU 12.

The data in the dual baud 1-RAM 34a-n is taken into the sub-RAM 24a-n by the sub-CPU 22a-n.

The sub CPU 22 uses the measured value (PV), set value (3V), PID constant, etc. stored as described above.
a-n performs PID calculation, calculates the output value, and uses the sub-output capo (MV) as the manipulated variable (MV) 27al~7~nt~
7 and corresponding heaters 43 (1)
~(1), or output an alarm output based on the relationship between the measured value (PV), set value (SV), and alarm set value.

These data are also stored in the sub-RAMs 24a to 24n.

Next, the sub CPUs 22a-n
The data of AM34a=ix is rewritten, that is, calculations are performed based on the input data and the data from the main CPU 12, and the results are stored in the sub RAM 24a-wn. The data is then sent to the dual-baud RAM 34a-n for use in display or the like. This is the main CPU
12 takes in.

In each of the above operations, in principle, the sub-CPU
22a-n and the main CPU 12 are each independent. Therefore, even if the workload of the main CPU 12 increases due to display or key input, the sub CPU 22 will still be able to control the temperature.
This can be done with ample margin due to a-n. If the number of control points increases, it is only necessary to increase the number of subsystems accordingly.

The important work of the main CPU 12 is processing of the above-mentioned display and settings, control operations other than temperature control, and inputting the motor rotation speed and current value of the extruder 40 from the main input ports 16al~, ~n, ~7, etc. analog input, motor starting,
When a digital input such as a stop signal is set by key operation or switch operation, it is also possible to switch the display to various screens and output the output determined by these operations.

Note that although the above embodiment deals with a controller, the present invention is not limited thereto, and can be applied to other devices having similar problems.

<Effects of the Invention> As is clear from the above description, the CPU II according to the present invention
I? One method is a main CPU and one or more sub CPUs.
A data channel area is provided in the dual port RAM shared between the main CPUs.
A data channel area is also provided in the sub RAM of the AM and sub CPU, respectively, and data input/output between the main cpit+ and the sub CPU is performed by determining the number of channels in each data channel area. Using the number of channels in the channel area as an intermediary, for example, the completed data from one CPU side is stored in a dual-baud RAM, and this data is transferred to the other CPU side.
By reading the data on the side, special processing (data check) as in the past becomes unnecessary, and hardware and software can be simplified.

In addition, since it is possible for one CPU to monitor the operation of the other CPU at the same time, if one CPU malfunctions, the output of the adjustment needle will be immediately stopped and no damage will be caused to the system. You can perform processing such as

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the outline of an embodiment of the cPUIIJ111 system according to the present invention, and FIG.
Fig. 3 is a schematic diagram showing an example of a controller to which the CPU1#I (It method in Fig. 1 is applied), Fig. 4 is a flowchart showing the flow for executing the CPU1#I (It method) in Fig. 5 is a schematic diagram showing an example of a conventional CPU control method. In the figure, 1 to 4...data channel area, 5I-1... ...Data area, 6,...Data area, 11...Main data bus, 12...Main CPU. 14...Main RAM. 16,...Main input port, IL -a...Main output boat, 21 axn・
. . . Sub data bus, 22a to n . . . -Sub CPU. 24a-n---Sub RAM. 34a-n...Dual port RAM. 40... Extruder, 41... Controller,

Claims (2)

[Claims] (1) A data channel area is provided in a dual port RAM shared between the main CPU and one or more sub CPUs, and data channel areas are also provided in the main RAM of the main CPU and the sub RAM of the sub CPU, respectively; A CPU control system characterized in that data input/output between the main CPU and the sub CPU is performed by determining the number of channels in each data channel area. (2) A CPU characterized in that it is possible to check whether the main CPU and sub CPU are operating normally by using the data channel area in the dual port RAM.
control method.