JPH0297141A - Transmission system for error correction code - Google Patents

Abstract

PURPOSE:To eliminate the occurrence of jitter accompanied with speed conversion by executing error correction synchronously with the bit speed of a repeating transmission line without speed conversion by an error correction executing means. CONSTITUTION:An error correction word synchronizing circuit 2w and on error correction decoder 2d are provided as operation means which operate syndrome and error in accordance with an error correction logic with respect to each one frame of a reception signal, and an error correction encoder 2e and a bit correcting circuit 2c are provided as correcting means which correct the signal to be transmitted in the next repeating section in accordance with operation results of operation means. In a repeating installation, operation means and correcting means are synchronized with the bit speed of the transmission line, and these means are connected by a signal line having the same bit speed as the transmission line and the speed conversion is not performed between them. Consequently, jitter accompanied with speed conversion does not occur, and this jitter is not accumulated at each time of passing the repeating installation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to wired or wireless digital communication systems.

In addition to a method in which relay devices are cascaded on a transmission path, a digital signal having a frame structure including check bits for error correction is transmitted, and each relay device performs error correction, each relay device By performing error correction and/or separating and inserting additional bits without speed conversion, jitter caused by repeating speed conversion is reduced.

[Conventional technology]

FIG. 2 is a block diagram of the transmission line. As shown in the upper part of FIG.
k)/N times speed conversion is performed, and the error correction encoder 1
A check bit is added by e to perform error correction using a certain logic, resulting in a signal having a frame structure as shown in the lower part of FIG. This signal is transmitted from the transmitting circuit 1t to the transmission path.

A digital signal propagating through a transmission path reaches a receiving device 3 via a plurality of repeating devices 2 connected in series. In the receiving device 3, the signal reproduced by the receiving circuit 3r is transmitted to an error correction word synchronization circuit 3W and an error correction decoder 3d.
Error correction is performed by , and the k check bits are removed. Furthermore, the speed conversion circuit 3S provides N/(N+
k) The speed is doubled to the original speed, and the signal is sent out from the receiving device 3 as output data.

FIG. 4 is a block diagram of a conventional relay device 2. As shown in FIG.

In other words, when performing error correction in the relay device 2, as shown in FIG. The correction is performed and the data signal at the original speed is reproduced using the speed conversion circuit 2S, and the speed conversion circuit 25', which is equivalent to the elements of the transmitter 1 described above, and the error correction encoder 2e are used for this data signal. The configuration is such that a check bit is added to each signal and transmitted to the transmission path of the next relay section.

[Problem that the invention seeks to solve]

This configuration has the advantage that the relay device 2 can use the same elements as the circuits applied to the transmitter 1 and the receiver 3, but the jitter that occurs during speed conversion is added and accumulated each time the relay device passes through the relay device. There were some drawbacks.

The present invention is an improvement on this problem, and aims to provide a relay system in which no speed conversion is required in the relay device and no jitter is accumulated.

[Means for solving problems]

In the relay device of the present invention, the calculation means for calculating errors and the correction means for correcting the signal to be transmitted to the next relay section based on the calculation result of this means are both configured to be synchronized with the bit rate of the transmission path. The two means are characterized in that they are connected by a signal path whose speed is equal to the bit speed of the transmission path.

Further, the relay device of the present invention can be configured to include means for separating or inserting all or part of the additional bits including the housekeeping bits in synchronization with the bit rate of the transmission path.

[Effect]

In the relay device, the means for calculating errors from the received signal from the previous section of the transmission line and performing error correction is synchronized with the bit rate of the relay transmission line, that is, the high bit rate including check bits or additional bits. executed. and,
The signal path between these means also has the bit rate of the relay transmission path, and does not perform speed conversion.

Furthermore, when additional bits including housekeeping bits are transmitted and the relay equipment separates and inserts these additional bits, the means for this operates in synchronization with the bit speed of the transmission path and performs speed conversion. Not performed.

Therefore, jitter associated with speed conversion does not occur. Furthermore, since a circuit associated with speed conversion is not required, the number of components of the relay device is reduced and reliability is improved.

〔Example〕

FIG. 1 is a block diagram of a relay device according to a first embodiment of the present invention. Furthermore, FIG. 2 is a block configuration diagram illustrating a relay transmission line according to an embodiment of the present invention.

In FIG. 2, a human-powered data signal is subjected to speed conversion by a transmitting device 1, and a check bit for error correction is added thereto, and the signal is transmitted to a transmission path. A plurality of relay devices 2 are connected in series to the transmission path. A receiving device 3 is connected to the receiving end of the transmission path, and error correction is calculated using the check bits, speed conversion is performed, and the information bits are restored to their original bit speed and sent out as an output data signal.

The human-powered data signal input to the transmitting device 1 is a digital signal composed of an N-bit frame as shown in the upper row of FIG. A digital signal is structured into a frame and includes within the frame N bits of information bits and N bits of check bits based on predetermined error correction logic.

As shown in FIG. 1, the relay device 2 of the present invention includes an error correction word synchronization circuit 2W and an error correction word synchronization circuit 2W as calculation means for calculating the syndrome and calculating the error according to the error correction logic for each frame of the received signal. An error correction encoder 2 is provided as a correction means for correcting a signal to be transmitted to the next relay section based on the calculation result of the decoder 2d.
e and a bit correction circuit 2C. Here, in the relay device 2 of the present invention, the calculation means (2W, 2d) and the correction means (2e, 2C) are configured to synchronize with the bit rate of the transmission path, and the transmission between these two means is They are connected by a signal path with a speed equal to the bit rate of the path, and no speed conversion occurs between them.

Therefore, no jitter occurs due to speed conversion, and this jitter does not accumulate each time the signal passes through a relay device.

FIG. 5 is a block diagram of a relay device according to a second embodiment of the present invention. As shown in Figure 6, this device transmits q additional bits, including check bits for error correction and bits for supervisory control and other housekeeping, in one frame. Regarding the additional bits of q bits, each relay device 3 separates and inserts them.
It is configured.

That is, compared to the device of the first embodiment explained in FIG.
The difference is that a clock inhibit circuit 21 for detecting the synchronization timing of the additional bits of q bits is provided before the error correction word synchronization circuit 2w. As a result, at the timing of the q-bit additional bit, the error correction word synchronization circuit 2W is disabled, and the bits related to error correction (N and k) excluding the q-bit additional bit from the received signal.
Extract only. This performs syndrome calculation and error correction. Thereafter, a demultiplexing circuit 2m for separating or multiplexing the additional bits (q bits) is provided to obtain a separated signal at a terminal Hi, and to insert an insertion signal from this relay device from a terminal HO. Here, these error correction calculations and execution of error correction are all performed in synchronization with the bit rate of the transmission line, as shown by the timing signal path, and furthermore, the demultiplexing circuit 2m is also synchronized with the bit rate of the transmission line. It will be done as follows. This relay device 2 does not include any speed conversion circuit.

Therefore, no sick occurs due to speed conversion, and the circuit configuration is simplified.

〔Effect of the invention〕

As described above, according to the present invention, speed conversion is not performed even when error correction is performed in the relay device, so that jitter does not occur due to speed conversion and there is no accumulation of this jitter.

Furthermore, even when additional bits including housekeeping bits are transmitted to a frame signal propagating on a transmission path, and these additional bits are separated or inserted at a relay device, speed conversion is not performed in the present invention. No jitter occurs due to speed conversion.

Furthermore, the device of the present invention has the advantage that the reliability of the device is improved because the circuit required for speed conversion is omitted and the number of components of the relay device is reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a relay device according to a first embodiment of the present invention. FIG. 2 is a block diagram of a relay transmission line according to an embodiment of the present invention. FIG. 3 is a frame configuration diagram of a signal transmitted to a relay transmission line in the first embodiment. FIG. 4 is a block diagram of a conventional relay device. FIG. 5 is a block diagram of a relay device according to a second embodiment of the present invention. FIG. 6 is a frame configuration diagram of a signal transmitted to a relay transmission line in the second embodiment. 1... Transmitting device, 2... Relay device, 3... Relay device. Patent applicant: Nippon Telegraph and Telephone Corporation Representative Patent attorney: Naotaka Ide

Claims (1)

[Claims] 1. Connected in cascade on a transmission path on which a digital signal configured as a frame and containing N bits of information bits and k bits of check bits based on a predetermined error correction logic is transmitted within the frame. and a calculation means for calculating an error according to the error correction logic for each frame of the received signal, and a calculation means for correcting the signal to be transmitted to the next relay section based on the calculation result of this means. In an error correction code transmission system including a correction means, the arithmetic means and the correction means are configured to be synchronized with the bit rate of the transmission line, and there is a gap between these two means at a speed equal to the bit rate of the transmission line. A transmission method for error correction codes characterized in that they are connected by a signal path. 2. A transmission path on which a digital signal consisting of a frame and containing N bits of information bits, k bits of check bits based on predetermined error correction logic, and q bits of additional bits including housekeeping bits is transmitted. The relay device includes a cascade-connected relay device, and the relay device includes a calculation means for calculating an error according to the error correction logic for each frame of the received signal, and a calculation means for calculating an error in the next relay section based on the calculation result of this means. In an error correction code transmission system including a correction means for correcting a signal to be transmitted, the calculation means and the correction means are configured to be synchronized with the bit rate of the transmission line, and there is a gap between the two means. The error correction is connected by a signal path having a speed equal to the bit speed, and the relay device is provided with means for separating or multiplexing all or part of the additional bits in synchronization with the bit speed of the transmission path. Code transmission method.