JPH0295280A - Integrated circuit simulator - Google Patents

Abstract

PURPOSE:To eliminate the trouble of setting measuring instruments on a package IC, to find a defect of the package IC efficiently, and to shorten the recovery time for trouble by comparing the output of the package IC with the output of a simulation IC. CONSTITUTION:An IC clip is set on the package IC. Then the simulation IC equal to the package IC is mounted on an IC socket 3. Then pin jacks 2a corresponding to output pins at a terminal part 7 and pin jacks 2b corresponding to the output pins at a terminal part 8 are connected to pin jacks 2c at a terminal part 9 as the input of a digital comparator circuit 6 by jumper lines 13 so as to compare their signals. Further, the output signal of the circuit part 6 has a hazard owing to the circuit delay of signals to be compared, etc., so a control circuit 15 removes the hazard, a latch circuit part 10 latches only a dissidence signal, and the latched signal is displayed at a display circuit part 12.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit simulator for determining the acceptability of an integrated circuit mounted on a printed circuit board when a failure occurs.

[Conventional technology]

Conventionally, when a fault occurs on an S product circuit (IC) mounted on a printed circuit board, investigation to determine whether it is good or bad has been done using measuring instruments such as an oscilloscope or logic analyzer.
The relationship between the input signal and the output signal of the IC is investigated, and whether or not the result matches the normal operation of the IC is investigated to determine whether the IC is good or bad.

[Problem to be solved by the invention]

In the above-mentioned investigation using conventional measuring instruments to determine the quality of the actual device C, the probes of the measuring instrument must be brought into contact with the pins of the IC, which makes setting and operation difficult. There is a drawback. Also,
Even if the relationship between input and output signals is known, determining whether the IC is operating normally depends on the investigator's technical ability and level of understanding of circuit operation. Another drawback is that there is a difference in the number of man-hours required for repair, and work efficiency cannot be improved.

An object of the present invention is to solve the above-mentioned drawbacks of fault investigation of the actual device C, and to provide an input signal to be supplied to the integrated circuit (actual device C) when a failure occurs in the integrated circuit (actual device C) mounted on a printed circuit board. The signal is supplied to a separate simulation integrated circuit (simulation IC), and the actual device C
To provide an integrated circuit simulator that can efficiently investigate faults in a real device C by making it possible to judge whether the real device C is good or bad by comparing the output of the simulation IC and the output of a simulation IC.

[Means to solve the problem]

An integrated circuit simulator (IC simulator) of the present invention includes an IC clip for gripping an integrated circuit mounted on a printed circuit board, and a first terminal having a plurality of pin jacks connected to each pin of the IC clip with a conductive wire. Department and
an IC socket for mounting an integrated circuit for comparative investigation; a second terminal section having a plurality of pin jacks connected to each terminal of the IC socket with conductive wires; and the first terminal section and the second terminal. a switch section having a plurality of switches connected in series between corresponding bin jacks of the section to supply and disconnect signals; and a digital comparator circuit that inputs and compares signals from the first and second terminal sections. a third terminal section that has a bin jack connected to the input pin of the digital comparator circuit section with a conductor wire and can be connected to the first and second terminal sections with a jumper wire; a control circuit section that controls the hazard output of the digital comparator circuit section, a latch circuit section that latches the mismatch output signal sent from the digital comparator circuit section, and a latch circuit section that latches the mismatch output signal latched by the latch circuit section. and a display circuit section for displaying images.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In FIG. 1, all the pins of the IC clip 1 for gripping the actual device C are connected to a conducting wire 11, and the end of the conducting wire 11 is connected to the pin jack 2a of the terminal portion 7. The bin jack 2a is connected to the switch section 4 by a conductor.
is connected to one terminal 5a of each corresponding switch. The other terminal 5b of each switch of the switch section 4 is connected to the corresponding bin jack 2b of the terminal section 8 by a conductive wire, and the bin jack 2b is connected to the simulation I
It is connected to the corresponding pin of the IC socket 3 into which C is installed. On the other hand, the input pin of the digital comparator circuit section 6 is connected to a conducting wire 16, and the end of the conducting wire 16 is connected to the pin jack 2C of the terminal section 9. The output pin of the digital comparator circuit section 6 is connected to the control circuit 15.
The output pin of the control circuit 15 is connected to the input pin of the latch circuit section 10 by a conductor wire, and the output pin of the latch circuit section 10 is connected to the input pin of the display circuit section 12. is connected to by a conductor. Power for the comparator circuit section 6, the control circuit 15, the latch circuit section 10, and the display circuit section 12 is supplied from the power supply terminal section 14.

Next, the operation of the IC simulator configured as described above will be explained.

First, the IC clip 1 is set on an IC to be investigated mounted on a printed circuit board. This allows the pin of the IC clip 1 to be connected to the pin jack 2a corresponding to the terminal section 7.
A signal is sent to Of the signals appearing on the pin jack 2a of the terminal section 7, the switch section 4 closes only the switch corresponding to the input signal of the actual device C and the switch corresponding to the power supply and ground, and closes the switch corresponding to the output signal. Leave it open. The signal, power supply, and ground selected by the switch section 4 are supplied to the IC socket 3 via the terminal section 8 . The IC (simulation IC) installed in the IC socket 3 is equivalent to the IC to be investigated (actual device C) mounted on the printed circuit board. Next, in order to compare the signals of the bin jack 2a corresponding to the output pin in the terminal part 7 and the bin jack 2b corresponding to the output pin in the terminal part 8, the terminal which is the input of the digital comparator circuit part 6 is connected. Part 9 Bin Jack 2c
Connect to with jumper wire 13. Comparator circuit section 6
Since the output signal of 2 has a hazard due to the circuit delay of the signal to be compared, the control circuit 15 eliminates the hazard, only the mismatch signal is latched by the latch circuit section 10, and this latched signal is sent to the display circuit section 12. Display in .

〔Effect of the invention〕

As explained above, by using the IC simulator of the present invention, operations such as setting measuring instruments on the actual device C can be eliminated, and individual differences in the investigator's understanding of circuit operation and ability can be avoided. This has the effect that it is possible to eliminate the influence of the above, to discover defects in ICs mounted on printed circuit boards at an early stage, and to shorten the time required to repair failures.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1...IC clip, 2a, 2b, 2C...bin jack, 3...IC socket, 4...switch part,
5a, 5b...Switch terminal, 6...Digital comparator circuit section, 7, 8, 9...Terminal section, 10...
- Latch circuit, 11, 16... Conductive wire, 12... Display circuit section, 13... Jumper wire, 14... Power supply and demand terminal section, 15... Control circuit.

Claims (1)

[Claims] an IC clip for gripping an integrated circuit mounted on a printed circuit board; a first terminal portion having a plurality of pin jacks connected to each pin of the IC clip with conductive wires;
an IC socket for mounting an integrated circuit for comparative investigation; a second terminal section having a plurality of pin jacks connected to each terminal of the IC socket with conductive wires; and the first terminal section and the second terminal. a switch section having a plurality of switches connected in series between corresponding pin jacks of the section to supply and disconnect signals; and a digital comparator circuit that inputs and compares signals from the first and second terminal sections. a third terminal section that has a pin jack connected to the input pin of the digital comparator circuit section with a conductor wire and can be connected to the first and second terminal sections with a jumper wire; a control circuit section that controls the hazard output of the digital comparator circuit section, a latch circuit section that latches the mismatch output signal sent from the digital comparator circuit section, and a latch circuit section that latches the mismatch output signal latched by the latch circuit section. An integrated circuit simulator comprising: a display circuit section for displaying images;