JPH0294634A - Mos transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain a large current driving capacity and a good characteristic by a method wherein a medium-concentration impurity diffusion region of a double-diffusion source-drain structure is arranged to be adjacent to a high- concentration impurity diffusion region in such a way that the whole of the region is overlapped completely with a gate electrode. CONSTITUTION:A lower-layer gate electrode 3 is formed on a P-type semiconductor substrate 1 via a gate oxide film 2; an upper-layer gate electrode 7 is formed on the lower-layer gate electrode 3. A thickness of the lower-layer gate electrode 3 is thinner than that of the upper-layer gate electrode 7; regions 4a, 4b of a medium-concentration N<-> impurity active layer are formed to be adjacent to N-type high-concentration impurity active layers 7a, 7b in such a way that the respective whole regions are covered with the gate electrode. Accordingly, a charge storage layer is formed, by means of an electric field, in a substrate region situated directly under the gate electrode 3. Thereby, it is possible to suppress a drop in a driving capacity by a parasitic capacitance of the medium- concentration N<-> impurity diffusion regions 4a, 4b; in addition, it is possible to suppress a deterioration in a characteristic by a hot carrier.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS transistor and a method for manufacturing the same, and particularly relates to an improvement in its source/drain structure.

[Conventional technology]

Conventionally, a lightly doped drain (L D
D: Lightly Doped Drain)
Transistors have been announced by TSANG and others (■
EEE ) Landexy 3 Electron Device VOL, t! D-291982CIEEF! Tra
nsaction Electron Devices
VOL, ED-291982)).

FIG. 6 shows an N-channel MOS transistor having this LDD structure. In the figure, l is a P-type semiconductor substrate, 5 and 6 are an N-type drain and an N-type source formed on the surface of the substrate l, The drain 5 is formed by a high concentration N-type impurity diffusion layer 7a and ~1017/cI13 to 10"/ca
The source 6 is made up of a high concentration impurity diffusion layer 7b and the same medium concentration N- type impurity layer 4b as described above. Reference numeral 3 designates a polysilicon bridge 3 formed on a P-type semiconductor substrate 1 with a gate insulating film 2 interposed therebetween, and a side wall made of an oxide film 8 is formed on the side wall of the polysilicon bridge 3. Here, a portion of the N- type impurity diffusion layers 4a, 4b penetrates into the region immediately below the gate electrode 3 made of polysilicon to a depth of several hundred layers from its end.

Next, a method of manufacturing this N-channel LDDMO3 transistor will be explained with reference to FIG.

First, a gate oxide film 2 and a gate electrode 3 made of polysilicon are sequentially formed on a P-type semiconductor substrate 1.
), N-type impurities such as phosphorus or arsenic are applied to the semiconductor substrate 1 using the gate electrode 3 as a mask at ~1013/cm'
A source/drain ion implantation layer 4C is formed by ion implantation at a dose of (FIG. 7(b)).

Next, chemical vapor deposition (CVD)
: Che+*1cal Vapor Deposit
ion) oxidation by the method! Figure 7 (C
1), this is anisotropically etched to leave the oxide film 8a only on the side walls of the gate electrode 3, that is, to form the side wall portion 8 (FIG. 7(d)), the gate electrode 3 and the side wall portion 8 are etched. A high concentration N-type impurity is implanted as a mask.

Thereafter, heat treatment is applied to activate and diffuse the implanted impurities to form the high concentration impurity diffusion layers 7a, 7b and medium concentration impurity diffusion layers 4a, 4b, and finally, as shown in FIG.
) to obtain an impurity profile as shown in

Next, the functions of the conventional LDD structure will be explained using FIG. 6. The source 6 and substrate 1 of the transistor are placed at a potential of, for example, Ov, and the drain 5 is placed at a power supply voltage (for example, 5
V) is given. Therefore, the N-type drain diffusion layer 7a
, 4a and the P-type semiconductor substrate 1, a reverse bias is applied to the P/N junction, and a high electric field is generated.

Such a drain electric field is relaxed as the width of the depletion layer increases.

That is, the radius ω of the depletion layer of the P/N junction is given by,
Here, N is the acceptor concentration, N.

is the donor concentration, εS is the dielectric constant of the semiconductor, q is the amount of charge, and when the N-type impurity concentration is significantly higher than the P-type semiconductor impurity concentration, that is, the width of the time depletion layer ω of N o >> N A is ω== (2εs/qNa), and when the N-type impurity concentration is low and equal to the concentration of the P-type semiconductor substrate, that is, when Na'=No, the width of the space-time depletion layer is ω# (4εs /qNA), and the electric field is lower in the PN junction of the low concentration N-/P- substrate.

Therefore, in the conventional LDD transistor shown in FIG.
The electric field is relaxed by providing the medium concentration N type impurity region 4a between the P/N junction between the substrate 1 and the high concentration N type impurity diffusion M1a.

Next, the operating state of the LDD l-transistor will be explained using FIG. 8.

The transistor operates in the pentode region (Fig. 8(a)) where the drain voltage V is larger than the gate voltage (VD > Va) and when the gate voltage VG is much larger than the drain voltage (Va >> VD ) Tricanal region (Fig. 8(b)
)). In the five-channel region shown in FIG. 8(al), a high-resistance depleted region 10 is formed between the inversion layer 9 and the drain 5 consisting of the N-layer 4a and N'' 7b.

In this case, in addition to the resistance of the channel consisting of the inversion N9,
The resistance of the medium concentration N- layer 4b on the source side, which is a parasitic resistance,
The driving ability of the transistor decreases due to the resistance of the drain-side depletion layer IO and the resistance of the medium-concentration N-layer 4a on the drain side, and in the triode open region, parasitic resistance occurs as shown in FIG. 8(b). The resistance of the source side N- layer 4b and the resistance of the drain side N''[4a reduce the driving ability of the transistor.

[Problem to be solved by the invention]

The conventional LDDMO3 transistor is constructed as described above, and includes a medium concentration N- impurity layer 4a.

Since the transistor 4b is provided at both the source and drain regions, there is a problem in that the parasitic resistance of the MOS transistor becomes large and the current driving ability is reduced.

In addition, in the structure of the drain of the conventional LDDMO3 transistor, hot carriers having energy higher than that in the thermal equilibrium state are generated on the surface of the medium concentration N-type impurity diffusion layer 4a, and the generated hot carriers are transferred to the side wall of the gate electrode 3 of the MOS transistor. The oxide film 8 is injected, and as a result, the surface of the N- region 4a on the drain side is depleted, the resistance of this region increases, and the driving ability of the MOS transistor further deteriorates.

This invention was made in order to solve the above-mentioned problems, and it is possible to alleviate the electric field at the drain part of a MOS transistor, and reduce the driving ability of the MOS transistor in the inter-triode and inter-triode regions. It is an object of the present invention to provide a MOS transistor and a method for manufacturing the same, which can significantly improve the life of the device.

(Means for Solving the Problems) A MOS transistor according to the present invention has a double diffused source/drain structure in which a medium concentration N- impurity diffusion region is doped with a high concentration N° impurity diffusion region so that the entire region completely overlaps with a gate electrode. It is placed adjacent to the area.

[Effect]

In this invention, since the medium concentration N- impurity diffusion region of the double diffused source/drain structure is arranged so that its entire region completely overlaps the gate electrode, the electric field creates a charge storage layer in the substrate region directly under the gate electrode. As a result, it is possible to suppress a reduction in driving ability due to parasitic resistance of the medium concentration N- impurity diffusion region, and furthermore, it is possible to suppress characteristic deterioration due to hot carriers.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an M having an LDD structure according to an embodiment of the present invention.
The cross-sectional structure of an OS transistor is shown, and the same reference numerals as those in FIG. 7 is an upper layer gate electrode made of a high melting point metal film or a high melting point metal silicide film, etc., provided on the lower layer gate electrode 3. Here, the thickness of the lower layer gate electrode 3 is defined as the upper layer gate electrode. * 4 a and 4 b are medium-concentration N- impurity active layers, which are thinner than the electrode 7 , and these regions 4 a and 4 b are N-doped on the drain side and source side so that the entire area is covered with the gate electrode 3, respectively. It is formed adjacent to the high-concentration impurity active layers 7a and 7b.

FIG. 2 is a diagram showing a cross-sectional structure in the main steps of a method for manufacturing an LDDMOS transistor having such a structure.
The manufacturing method will be explained below in order of steps.

First, an element isolation region (not shown) is placed on the semiconductor substrate 1.
After the formation of the oxide film 20. which becomes the gate oxide 112 and the channel implantation to control the threshold voltage. A first conductive film 30 that becomes the lower gate electrode 3. A second conductive film 70 that will become the upper layer gate electrode 7 is sequentially formed by the CVD method (
FIG. 2 (aJ>) Then, after applying a resist 9 and forming a pattern, the second conductive film 70 is anisotropically etched to form a second conductive waist portion (upper layer gate electrode) 7, and then the resist 9 is applied. 9 and the second conductive film portion 7 as a mask.
Medium concentration N- type impurity layers 4a and 4b are implanted with type impurities.
(Figure 2 mountain)).

Thereafter, a second oxide film 80 is formed on the entire surface by the CVD method (FIG. 2(C)), and this oxide film 80 is anisotropically etched to form a second oxide film on the side wall of the second conductive film portion 7. The remaining part of the film (sidewall part) 8 is formed (FIG. 2(dl)).

Next, the first conductive layer 11130 is etched by anisotropic etching using the remaining oxide film 8 and the second conductive film portion 7 as a mask to form the lower gate electrode 3 (FIG. 2(e)).
. Next, using the lower gate electrode 3, the upper gate electrode 7 thereon, and the sidewall portion 8 as masks, N-type impurity ions are implanted to form an N-type high concentration impurity layer. a, 7b are formed (FIG. 2(f)), and finally, after heat treatment is performed, a glabellar insulating film 11 is formed, a contact portion 12 is provided, and a wiring metal 13 is further formed.

Next, the effects will be explained.

In such an LDDMO3 transistor, as shown in FIG. 1, since the N parts 4a and 4b with high resistance are under the gate electrode 3, the diode region, that is, the gate voltage . is the drain voltage■. When it is larger, a charge storage layer is formed in the surface region of the N portions 4a and 4b on the source/drain side due to the electric field from the gate electrode to the substrate, and as a result, the carrier concentration in this portion increases, and the medium concentration N- The parasitic resistance of layers 4a, 4b is reduced.

Also, when operating in the diode region, that is, the drain voltage VD is equal to the gate voltage ■. Even when the potential is higher than , a charge storage layer is formed on the surface of the source side N portion 4b where the potential is kept low by the electric field from the gate electrode to the substrate, the carrier concentration increases and the parasitic resistance decreases.

Figure 3 shows an LDD with a gate oxide film of 10 nm according to this embodiment.
Source-side impurity distribution in the channel direction on the surface of the MO3 transistor (graph B), gate voltage Vc5V,
This graph shows the carrier concentration on the source side (graph A) when the pentode operates when the drain voltage is 5■ and the source voltage is 07.

As can be seen from this figure, a charge storage layer is formed on the surface of the medium concentration N- layer due to the electric field from the gate electrode to the N- region, so the carrier concentration on the surface of the N'' region is one order of magnitude higher than the impurity concentration. The resistance of the N− layer decreases, and in the LDDMO3 transistor of this example, the current drive capability is N”
This is an improvement over conventional LDD structures in which the portion is formed outside the gate.

In addition, FIG. 4 (al indicates the drain characteristics of the conventional LDDMOS transistor, and FIG. 4(b) shows the drain characteristics of the LD according to this embodiment.
It shows the drain characteristics of a DMOS transistor, and here the drain current is plotted in 500 increments on the vertical axis.
As μA, the drain voltage is taken as a scale of 1■ on the horizontal axis, and the gate voltage is set as a parameter from Ov to 5■.
It is changed by v. In addition, in FIG. 4(a), the graphs of gate voltages OV and IV overlap the horizontal axis, and the top graph shows the case where the gate voltage is 5■.
In bl, the graph of the gate voltage Ov overlaps with the horizontal axis.

Comparing these figures, it is clear that the structure of the present LDD transistor improves the driving ability of the transistor.

In other words, in the LDDMO3 transistor, in the drain region where a high electric field is applied, carriers are generated by collision ionization as l Q ”/
(However, in this LDD structure, carriers are generated at the gate electrode 3 as shown in FIG. 5(a).)
While it occurs in the lower part C, in a normal LDD structure, it occurs in the part below the oxide film 8 of the sidewall, as shown in FIG. 5(b).

For this reason, in the conventional structure, the surface of the N-layer 4a on the drain side is depleted by the electrons captured in the sidewall oxide film 8, increasing the parasitic resistance, resulting in deterioration such as a drop in the driving ability of the MOS transistor, especially in the diode region. However, in this LDD transistor, even if electrons are captured in the gate oxide WA2 on the upper part of the N-layer 4a, the gate electrode 3.
Since a charge storage layer is formed on the surface of the N-layer 4a by the electric field from the N-layer 4a, the N-layer 4a is not depleted and the parasitic resistance does not increase and deterioration is less likely to occur.

In addition, in the manufacturing method of this embodiment, by changing the width of the second oxide film (sidewall portion) 8 on the side wall of the second conductive film 7, the length of the N- regions 4a, 4b under the gate electrode 3 can be adjusted. can be easily controlled.

In the above embodiment, the P-type semiconductor substrate l, medium concentration of N
Type impurity active layers 4a, 4b, high concentration N type impurity active layer? Although the LDD structure of the MOS transistor was constructed using a and 7b, the LDD structure may also be constructed using an N-type semiconductor substrate, a medium-concentration P-type impurity active layer, and a high-concentration P-type impurity active layer. .

〔Effect of the invention〕

As described above, according to the present invention, the medium concentration impurity diffusion region of the double diffused source/drain structure is arranged adjacent to the high concentration impurity diffusion region so that the entire region completely overlaps the gate electrode. The electric field caused by this method can suppress the increase in parasitic resistance of the medium-concentration diffusion layer to a small level, and can also significantly reduce the deterioration of device characteristics caused by hot carriers, making it possible to obtain a MOS transistor with large current drive capability and good characteristics. can.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing a MOS transistor according to an embodiment of the present invention, FIG. 2 is a diagram showing a method of manufacturing a MOS transistor according to an embodiment of the present invention, and FIG. 3 is a sectional view of a MOS transistor according to an embodiment of the present invention. A diagram showing impurity distribution and carrier distribution in the channel direction of a transistor, FIG. 4 is a diagram showing the LD of the present invention.
A diagram showing the drain characteristics of the DMO3I-transistor compared with the conventional one, FIG. 5 shows the drain characteristics of the present invention and the conventional LDD
FIG. 6 is a cross-sectional view showing the structure of a conventional LDD MO3 transistor; FIG. 7 is a cross-sectional view showing the conventional manufacturing method of a DD transistor in the order of steps; FIG. 8 is a cross-sectional view for explaining the operation of a conventional DD transistor. 1... Semiconductor substrate, 2... Gate oxide film, 3...
Gate electrode, 4a, 4b... Medium concentration N type impurity active region, 7a, 7b... High concentration N type impurity active layer (drain, source region), 7... Second conductive film part (upper layer gate electrode), 8... second oxide film remainder (sidewall part)
, 10...depletion layer. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 1', 41gr on P3' 1 2, Goome Ahq trap furnace

Claims (2)

[Claims] (1) Provided on a semiconductor substrate via a gate insulating film,
a gate electrode consisting of a lower gate electrode and an upper gate electrode having a narrower width; a first impurity diffusion region disposed on both sides of the lower gate electrode of the semiconductor substrate; A double-diffused source and drain region comprising a second impurity diffusion region having a lower impurity concentration than the first impurity diffusion region and arranged adjacent to the first impurity diffusion region so that the entire region is included in the region. A MOS transistor characterized by: (2) In a method of manufacturing a MOS transistor having a double diffused source/drain structure, a first insulating film and a first conductive film and a second conductive film are sequentially formed on a semiconductor substrate of a first conductivity type. a second step of selectively removing the second conductive film to form an upper layer gate electrode; and implanting a second conductivity type impurity into the semiconductor substrate using the upper layer gate electrode as a mask. A third step is to form a medium concentration impurity diffusion region, and a fourth step is to form a second insulating film over the entire surface and then anisotropically etch it to form a sidewall portion on the sidewall of the upper layer gate electrode. a fifth step of etching the first conductive film using the upper gate electrode and the sidewall portion as a mask to form a lower gate electrode; a fifth step of etching the first conductive film using the upper gate electrode and the sidewall portion as a mask; a sixth step of injecting second conductivity type impurities into the semiconductor substrate using the sidewall portions as a mask to form a high concentration impurity diffusion region.