JPH04239177A - Semiconductor device with field-effect transistor - Google Patents

Semiconductor device with field-effect transistor

Info

Publication number
JPH04239177A
JPH04239177A JP3002293A JP229391A JPH04239177A JP H04239177 A JPH04239177 A JP H04239177A JP 3002293 A JP3002293 A JP 3002293A JP 229391 A JP229391 A JP 229391A JP H04239177 A JPH04239177 A JP H04239177A
Authority
JP
Japan
Prior art keywords
conductivity type
semiconductor layer
source
semiconductor device
soi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3002293A
Other versions
JP2700955B2 (en
Inventor
Tadashi Nishimura
Yasuo Yamaguchi
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3002293A priority Critical patent/JP2700955B2/en
Publication of JPH04239177A publication Critical patent/JPH04239177A/en
Application granted granted Critical
Publication of JP2700955B2 publication Critical patent/JP2700955B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To provide an SOI-MOSFET which has less sidewall leak currents due to a parasitic transistor, an improved withstand voltage between the source and domain regions thereof, and a bidirectionality.
CONSTITUTION: An SOI-MOS transistor includes a first conductivity type semiconductor layer 3, formed in the shape of an island, which is composed of a gate electrode 7, a source region 31, and a drain region 21. The semiconductor layer 3 is surrounded with a first conductivity type polycrystalline silicon layer 5 with a sidewall insulating film 4 interposed therebetween. This sidewall insulating film 4 is provided with openings 41 and 42, at predetermined positions, through which the semiconductor device 3 and the polycrystalline silicon layer 5 are in contact with each other. This arrangement enables the electric potential of the first conductivity type regions inside the semiconductor layer 3 to be controlled independently of the source and domain regions.
COPYRIGHT: (C)1992,JPO&Japio
JP3002293A 1991-01-11 1991-01-11 Semiconductor device with field effect transistor Expired - Fee Related JP2700955B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3002293A JP2700955B2 (en) 1991-01-11 1991-01-11 Semiconductor device with field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3002293A JP2700955B2 (en) 1991-01-11 1991-01-11 Semiconductor device with field effect transistor

Publications (2)

Publication Number Publication Date
JPH04239177A true JPH04239177A (en) 1992-08-27
JP2700955B2 JP2700955B2 (en) 1998-01-21

Family

ID=11525326

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3002293A Expired - Fee Related JP2700955B2 (en) 1991-01-11 1991-01-11 Semiconductor device with field effect transistor

Country Status (1)

Country Link
JP (1) JP2700955B2 (en)

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6064090A (en) * 1996-01-17 2000-05-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a portion of gate electrode formed on an insulating substrate
US6940138B2 (en) 1999-07-16 2005-09-06 Seiko Epson Corporation Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment
JP2009507384A (en) * 2005-09-07 2009-02-19 イノヴァティーヴ シリコン イエスイ ソシエテ アノニム Memory cell having an electrically floating body transistor, memory cell array, and method for operating the memory cell and memory cell array
US8861247B2 (en) 2009-04-27 2014-10-14 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8964479B2 (en) 2010-03-04 2015-02-24 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8964461B2 (en) 2009-07-27 2015-02-24 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8982633B2 (en) 2009-05-22 2015-03-17 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9019759B2 (en) 2010-03-15 2015-04-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9064730B2 (en) 2009-03-04 2015-06-23 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9093311B2 (en) 2009-03-31 2015-07-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9142264B2 (en) 2010-05-06 2015-09-22 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9240496B2 (en) 2009-04-30 2016-01-19 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US9263133B2 (en) 2011-05-17 2016-02-16 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9276000B2 (en) 2007-03-29 2016-03-01 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US9331083B2 (en) 2009-07-10 2016-05-03 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9553186B2 (en) 2008-09-25 2017-01-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device
US10304837B2 (en) 2007-11-29 2019-05-28 Ovonyx Memory Technology, Llc Integrated circuit having memory cell array including barriers, and method of manufacturing same

Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271065B1 (en) * 1996-01-17 2001-08-07 Mitsubishi Denki Kabushiki Kaisha Method directed to the manufacture of an SOI device
US6064090A (en) * 1996-01-17 2000-05-16 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having a portion of gate electrode formed on an insulating substrate
US6940138B2 (en) 1999-07-16 2005-09-06 Seiko Epson Corporation Semiconductor device, semiconductor gate array, electro-optical device, and electronic equipment
US8873283B2 (en) 2005-09-07 2014-10-28 Micron Technology, Inc. Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
JP2009507384A (en) * 2005-09-07 2009-02-19 イノヴァティーヴ シリコン イエスイ ソシエテ アノニム Memory cell having an electrically floating body transistor, memory cell array, and method for operating the memory cell and memory cell array
US10418091B2 (en) 2005-09-07 2019-09-17 Ovonyx Memory Technology, Llc Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US9276000B2 (en) 2007-03-29 2016-03-01 Micron Technology, Inc. Manufacturing process for zero-capacitor random access memory circuits
US10304837B2 (en) 2007-11-29 2019-05-28 Ovonyx Memory Technology, Llc Integrated circuit having memory cell array including barriers, and method of manufacturing same
US9553186B2 (en) 2008-09-25 2017-01-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US9064730B2 (en) 2009-03-04 2015-06-23 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US9093311B2 (en) 2009-03-31 2015-07-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9425190B2 (en) 2009-04-27 2016-08-23 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8861247B2 (en) 2009-04-27 2014-10-14 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9240496B2 (en) 2009-04-30 2016-01-19 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8982633B2 (en) 2009-05-22 2015-03-17 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9331083B2 (en) 2009-07-10 2016-05-03 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8964461B2 (en) 2009-07-27 2015-02-24 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9679612B2 (en) 2009-07-27 2017-06-13 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US9812179B2 (en) 2009-11-24 2017-11-07 Ovonyx Memory Technology, Llc Techniques for reducing disturbance in a semiconductor memory device
US8964479B2 (en) 2010-03-04 2015-02-24 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US9524971B2 (en) 2010-03-15 2016-12-20 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9019759B2 (en) 2010-03-15 2015-04-28 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9142264B2 (en) 2010-05-06 2015-09-22 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9263133B2 (en) 2011-05-17 2016-02-16 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same

Also Published As

Publication number Publication date
JP2700955B2 (en) 1998-01-21

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