JPH0294097A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To simplify a write operation by providing a MOSFET between a power source terminal and a memory transistor (TR), and impressing a prescribed voltage to the gate of the MOSFET according to write information. CONSTITUTION:A write voltage VPP writes the information to a memory TR MC11. The source of the TR MC11 is connected to a ground potential VSS, and a drain is connected through an N-type MOSFET M11 to the write voltage VPP. According to write information D11, a write control circuit WR11 selectively impresses a constant voltage VR11 to the gate of the MOSFET M11. Here, the constant voltage VR11 is lower than the write voltage VPP. Therefore, it is unnecessary to increase the load resistance of the MOSFET M11, even when the characteristic of the TR MC11 in an unwritten condition is changed, the drain voltage at the time of writing is not changed. Consequently, timing regulation is made unnecessary, the circuit is simplified, and the write operation is simplified.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a non-volatile semiconductor memory device, and particularly to a non-volatile semiconductor device having a non-volatile semiconductor memory element in which information can be electrically written and a write circuit therefor. Regarding storage devices.

[Conventional technology]

2. Description of the Related Art Conventionally, as a nonvolatile semiconductor memory element in which information can be electrically written, there is an MO8 field effect transistor (hereinafter referred to as a memory transistor) having a two-layer gate structure of a floating gate and a control gate. FIG. 7(a) is a sectional view of this memory transistor, FIG. 7(b) is its symbol diagram, and FIG. 7(C) is its characteristic diagram. This memory transistor has a source 72 and a drain 73 formed by an N-type diffusion layer on a P-type substrate 71, and a floating gate electrically insulated from the outside by an insulating layer on the P-type substrate 71. 74 and a control gate 75 for switching this memory transistor. This memory transistor is said to be in a non-programmed state when the floating gate 74 is in an electrically neutral state, as shown in FIG. 7(C).
Low control gate voltage ■o1 for example 2
The control gate 75 and the drain 73 become conductive at (3).
When a high voltage, for example 12.5 V, is applied to the floating gate 74, electrons are injected into the floating gate 74, and the threshold voltage of the memory transistor seen from the control gate 75 is not high. Control gate pressure Ut as high as V
If Gs, for example, 7■ is not applied, it will not become conductive. Information can be stored using this change in threshold voltage.

FIG. 5 is a circuit diagram showing a conventional write circuit for the memory transistor shown in FIG. The north of the memory transistor MC, , is connected to the ground potential 55, and the drain is connected to an N-type field effect transistor (hereinafter referred to as MO8FET) M3. It is connected to the write voltage VFP via.

N-type daypre 2737MO8FETMs1 and N-type MO8
An inverter circuit INVsz is constructed with FET M52, the write data D51 is connected to the input terminal, and the output (D5l)pp is an N-type MOS FET Mss.
connected to the gate. When performing 1-inclusion of information,
When the complimentary data I)st is set to low level, the output (D51) PP of the inverter circuit INVs1, that is, the N type M
A write voltage vpp is applied to the gate of the O8FETM53, and the N-type MOS FET Mss becomes conductive. At this time, the gate X5 of the memory transistor MC51
Since a high voltage is also applied to the memory transistor MCss, a high voltage is applied to the gate and drain of the memory transistor MCss, and information is stored by injecting electrons into the floating gate.

Next, a description will be given of the integration characteristics of this memory transistor.

FIG. 6(a) shows the memory transistor MC shown in FIG.
5, the voltage at the drain a5 of the memory transistor MC51 in FIG.
5 is plotted on the horizontal axis, and current 5 flowing through the memory transistor MC51 is plotted on the vertical axis. Here, N type MOS F E
When the load characteristics of T Mss are set as shown by the solid line 60a, VP is applied to the gate of N-type MOS FET Mss.
Since P is applied, the memory transistor MC51
When no current flows through (Is=O), the voltage Vas(
Is=O) is expressed by the following equation (1), where VTN53 is the threshold voltage in consideration of the back bias characteristics of the N-type MO8FETMss.

Vas (Is=0)=Vpp-VTN53
- =ll) If the voltage-current characteristic of the memory transistor MC51 in the non-writing state is represented by the solid line 61a, then the voltage VaS at the drain of the memory transistor MC51 in the initial state when the memory transistor MCsl is programmed is represented by the solid line 60a. At the voltage VW61a indicated by the intersection with the solid line 61a, at this time, the memory transistor MC
At 5tK, current IW61a flows and electrons are injected into the floating gate. When the memory transistor MCsl enters the write state, its voltage-current characteristic changes as shown by the dotted line 63a K, and the voltage at the drain of the memory transistor MC5z also changes to vw.
63a. However, in actual non-volatile semiconductor memory devices, memory transistors are arranged in a matrix and one row line and one column line are selected from among a plurality of column lines connecting the drains of the memory transistors. Since the memory transistors arranged at the intersections are selected for writing, the drains a5 of the memory transistors MC+ and l shown in FIG. The gates of these unselected memory transistors are at the same level as VSS. Here, when there is a memory transistor in the VC write state among the unselected number of memory transistors connected to the drain a5 of the memory transistor MC5x, the floating gate of the memory transistor in the write state is charged to a negative potential. However, when a high voltage is applied to the drain, a high electric field is generated in the depletion layer at the end of the drain, causing avalanche breakdown. The drain voltage VBD at this time is shown in Figure 6 (
The voltage of a) is lower than vPPVTN53, and 7w63
When a is also low, holes generated by this avalanche breakdown are injected into the floating gate of the memory transistor in the write state, neutralizing the electrons already injected into the floating gate, and increasing the gate of the memory transistor in the write state. Because of the inconvenience of lowering the threshold voltage, N-type MO8FETM53 is generally used as shown in Figure 6(b).
The load characteristic is set as shown by the solid line 60b, so that the intersection point of the voltage-current characteristic 63b of the write state and the load characteristic 60b does not become higher than VED.

[Problem to be solved by the invention]

In order to prevent the occurrence of avalanche breakdown, the conventional write circuit described above uses an N-type MO8FET as shown in FIG.
Since the load resistance of M53 is set large, Fig. 6(b)
If the current-voltage characteristics of a memory transistor in a non-written state change as shown by the solid line 62b due to variations in the manufacturing stage, as shown in K, when attempting to write information to this memory transistor, the voltage will be applied to the drain. V
Since only a low voltage such as wszb is applied, the writing speed deteriorates, and in the worst case, writing becomes impossible. Also, even if the load resistance of N-type MOS FET Mss is set thick (Vpp VTNS3
)>VBD, it is necessary to make timing adjustments such as applying a voltage to the drain after the gate of the selected memory transistor is set to a high voltage, which has the drawback of complicating the circuit.

An object of the present invention is to provide a constant voltage generating circuit that generates a constant voltage lower than the write voltage, and to set the drain voltage of the memory transistor during writing using the output voltage of this constant voltage generating circuit. It is an object of the present invention to provide a nonvolatile semiconductor memory device that prevents avalanche breakdown of a memory transistor in an unselected write state, does not cause deterioration in write speed, and does not require timing adjustment during write.

[Means to solve the problem]

A nonvolatile semiconductor memory device of the present invention includes a power supply terminal to which a voltage is supplied, a nonvolatile semiconductor memory element in which information can be written electrically, and the nonvolatile semiconductor effect transistor.
A constant voltage generation circuit that generates a constant voltage lower than the voltage supplied to the power supply terminal; and a voltage applied to the MO8 field effect transistor by selectively applying the output voltage of the constant voltage generation circuit according to write information. It is constructed by having a containment control circuit for controlling the control circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

The source of memory transistor MCII is at ground potential V
The drain of SS is connected to the write voltage VPP via an N-type MOS FET Mlt. The constant voltage generation circuit VCONII generates a constant voltage VR that is lower than the write voltage VPP.
II, and the write control circuit WR11 generates the write information D.
11, a constant voltage VRII is selectively applied to the gate of the N-type MOS FET Mu.

Next, the write characteristics of the write circuit of the present invention will be explained. Second
The figure is a voltage-current characteristic diagram during writing of the memory transistor MCII shown in FIG. 1, where =9=voltage (al) of the drain al of the memory transistor MCII shown in FIG. 1 is plotted on the horizontal axis;

The vertical axis represents the current 11 flowing in the graph. Here N type MO8
When the load characteristics of FETMII are set as shown by the solid line 20, a constant voltage VRII is applied to the gate of the N-type transistor MC.
,.

When the K current is not flowing (11=O), the memo IJ
) Voltage Va x at drain at of transistor MC11
(I 1 = O) is expressed by the following equation (2), where VTNII is the threshold voltage in consideration of the back bias characteristics of the N-type MOS FET Ml+.

Vat(11=O)=Vgu VTNII
--(2) Assuming that the voltage-current characteristic of the memory transistor MCu in the non-writing state is the solid line 21, the voltage V at the drain of the memory transistor MC, , in the initial state when writing to the memory transistor Me, ,
al is the voltage VW2 indicated by the intersection of solid line 20 and solid line 21
1, and at this time, the memory transistor MC1x has a current I
W21 flows and electrons are injected into the floating gate.

−■〇− When the memory transistor MCII enters the write state,
The voltage-current characteristic changes to the dotted line 23, and the voltage at the drain of the memory transistor MCu also becomes VwzsKi.

Furthermore, in an actual nonvolatile semiconductor memory device, memory transistors are arranged in a matrix, with a plurality of row lines serving as common gate electrodes for the memory transistors arranged in the row direction, and a plurality of row lines serving as common gate electrodes for the memory transistors arranged in the column direction. By selecting one row line and one column line from among the plurality of column lines whose drains are connected, the memory transistor arranged at the intersection is selected and the 1-in operation is performed.
Memory transistor MC shown in FIG.

The drains of a plurality of unselected memory transistors (not shown in the figure) are connected to the drain a1 of , and the level of the gates of these plurality of unselected memory transistors is set to VSS. Here memory transistor MC
Among the unselected memory transistors connected to the drain a1 of o, there is a memory transistor in a written state, and a high voltage is applied to the drain of this memory transistor in a written state, resulting in shear balanche breakdown. Let VBD be the voltage generated by (VR
If the output voltage VRII of the constant voltage generation circuit VCONII is set to satisfy <VBD, avalanche breakdown will not occur.

FIG. 3 is a circuit diagram showing the embodiment of FIG. 1 in detail.

Multiple memory transistors MCa□1, MC31□
~MC:mn are arranged in a matrix, and connect the drains of the memory transistors arranged in the column direction to a plurality of row lines x3□, X32~Xsm, which serve as common gate electrodes of the memory transistors arranged in the row direction. A plurality of column lines D31. D32 to D3n, the row line controls the switching of the memory transistor by the row selection signal from the row decoder XD3, and the column line controls the switching of the memory transistor by the row selection signal from the row decoder
Column selection N-type MO8FETM whose switching is controlled by column selection signals 5Y32 to 5Yin from D3
Yst, selected by MY3z~MY3n, column selection N-type MOS FET MYal, MYsz~MY
The drains of 3n are commonly connected to the sense amplifier circuit SA.
3, and is also connected to the write voltage Vpp via the N-type MOS FET Mss. Furthermore, P-type MO
SF ET Mst.

Mn2 are connected in series, P type MOS FET M
The source of sl is set to the write voltage VPP, and the P-type MOS F
E T The drain and gate of Mn2 are connected to the power supply voltage VC.
Connect to C to configure a constant voltage generation circuit VCON31, and connect to P
Type MO8FETM33 and N type MOS FET MB2
The output voltage VR31 of the constant voltage generation circuit VCON31 is connected to the source of the P-type MO8FETM33, and the write information D31 is output to the input of the write control circuit W'R31. The gate of the N-type MOS FET M2S is connected to.

For example, when writing to the memory transistor MC311, the row decoder
and column selection N type MO by column decoder YD3.
By selecting S F E T MY31, the row line x3
1 and the column line D31 is selected. Next, by setting the write information D31 to low level, the N-type MOS FET M2
The output voltage VR31 of the constant voltage generation circuit VCON31 is applied to the gate of the memory transistor MC31 through the P-type M and OS FET MB2, and the N-type MO8-13=FETM becomes conductive. Writing is performed by applying a high voltage to the gate and drain. Here, constant voltage generation circuit VCO
The output voltage VR31 of N31 is P type MOS FET
Mst.

The threshold voltage of Ml, respectively, is VTP31 r VT
Assuming P32, it is possible to set the voltage range to the following equation (3) by changing the gate length and gate width as is well known.

(VPP-l VTP311) >VR31> (
VCC+IVTP321) --(3) Then, write voltage Vp is applied to the gate of column selection N-type MO3FET MY31.
The voltage VDst(Ins
t=O) Ha, N m MOS FET Mss t
D The threshold voltage considering the Hyck bias characteristics is VT
When N35 is used, the voltage range is expressed by the following equation (4).

(Vpp-IVTP311-VTN35)>VD31(
ID31=O)>(V cc +IVTP l-VTN
35) --(4) where V
pp=12V, VCC=5V, VT
P31 = VTp32 = -I V , VTN35 =
When IV is assumed, the voltage range of Vn:++, (Inxx=0) is expressed by the following equation (5).

10V>MC3t (ID31=0)>5V
=-(5) ft-V shown in Figure 2
Since RII VTNII can be set to any voltage in the range from iov to 5■, a high voltage is applied to the drain 1ζ of the memory transistor in the write state, and the voltage VBD at which avalanche breakdown occurs is also MC3t (I
D31 = O) 't: Can be set low. Therefore, to prevent avalanche breakdown from occurring, N-type MO8FETM35 and column selection N-type MO
S F E T MY31'+ MY32~MYsn
Since there is no need to set the load resistance large, for example, even if the voltage-current characteristic of the memory transistor in the non-writing state changes from the solid line 21 to the solid line 22 in FIG. Since the drain voltage changes to VW22 with a small change, there is little deterioration in writing speed.

FIG. 4 is a circuit diagram of another embodiment of the present invention.

In order to realize a nonvolatile semiconductor memory device with a t-bit configuration, memory transistors arranged in a matrix are arranged in t blocks Mk<1. Divided into MA42 to MA4t, column selection N type MO8FET M in each block.
Y411, MY412 to MY4In, sense amplifier circuits 5A41, 5A42 to 5A4t, and write voltage V
N-type MOS FET provided between PP and the drain of column selection N-type MO8FET M41, M42~
M41 and write control circuits WR4 to WR4t are provided. Furthermore, by providing one constant voltage generating circuit VCON41 and connecting its output voltage VR41 to each write control circuit wR41, wR42 to WR4t, the same effect as the embodiment shown in FIGS. 1 and 3 can be obtained. can get. Also, since it is only necessary to provide one constant voltage generation circuit,
When realizing a circuit on a semiconductor substrate, an increase in space due to providing a constant voltage generating circuit can be suppressed.

〔Effect of the invention〕

As explained above, the present invention provides a power supply terminal to which a write voltage is supplied for writing information to the memory transistor J3;
A MOSFET provided between the memory transistor and this power supply terminal, a constant voltage generation circuit that generates a constant voltage lower than the write voltage, and an output voltage of the constant voltage generation circuit that selectively changes the output voltage of the constant voltage generation circuit according to the write information. By providing a write control circuit that applies to the gate of the MO8FET, even if a high voltage is applied to the drain of a memory transistor in a non-selected write state during a write operation, the memory Since the drain voltage of the transistor can be set low, the load resistance formed by the MOSFET provided between the write voltage and the memory transistor does not need to be set so large.
Even if the voltage-current characteristics of the memory transistor in the non-written state change due to variations in the manufacturing stage, the drain voltage during writing does not change much, so there is little deterioration in writing speed. There is no need for timing adjustment such as applying a high voltage to the drain after applying a high voltage to the drain, which has the effect of simplifying the circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a characteristic diagram showing write characteristics of the present invention, FIG. 3 is a circuit diagram showing the block diagram shown in FIG. 1 in detail, and FIG. This figure is a circuit diagram of another embodiment of the present invention, FIG. 5 is a circuit diagram of a conventional write circuit, FIGS. 6(a) and (b) are both characteristic diagrams of the write circuit of FIG. 5, and FIG. (a), (b) and (C) are respectively cross-sectional views of an MO8 field effect transistor having a two-layer gate structure used in a nonvolatile semiconductor memory device;
They are a symbol diagram and a characteristic diagram. VCONII・VCON31・VCON41'-'
'Constant voltage generation circuit・WRll +WR31+WR41～
WR4t...Write control circuit, SA3, 5k
41~5k4t----Sense 77 circuit, MC
o+MC311~MC3Inn・MC5t-・・・・・・
memory transistor. =18

Claims (1)

[Claims] In a semiconductor memory device using a non-volatile semiconductor memory element as a storage medium in which information can be written electrically, a power supply terminal to which a voltage for writing information to the non-volatile semiconductor memory element is supplied and the non-volatile semiconductor a MOS field effect transistor provided between the drain of the storage element, a constant voltage generation circuit that generates a constant voltage lower than the voltage supplied to the power supply terminal, and the constant voltage generation circuit according to write information. a write control circuit that selectively applies an output voltage of the MOS type field effect transistor to the gate of the MOS field effect transistor.