JPH1064289A - Non-volatile memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile memory by preventing the voltage drop of a selected word line due to current flowing into a non-selected word line on writing and by preventing a writing speed from decreasing. SOLUTION: In a column decoder of a non-volatile memory, a first reference voltage signal is applied to a transistor 7 that is connected between an internal generation voltage line PM and a word line 2 and a second reference voltage signal is applied to a transistor 9 being connected between the internal generation voltage line PM and a word line 3. At the time of writing data, when the word line 2 is selected, the first reference voltage signal, becomes a reference voltage and the second reference voltage signal becomes VPM by address signal A0, thus turning on the transistor 7, turning off the transistor 9, and preventing a steady current that flows to the non-selected word line 3 from flowing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile memory, and more particularly, to a nonvolatile memory having a row decoder for selecting a memory cell according to a reference voltage and an address.

[0002]

2. Description of the Related Art FIG. 3 is a sectional view showing a structure of a memory cell. First, the basic operation of writing will be described using this. The cell of the nonvolatile memory is formed on a P-type semiconductor substrate 94 and has an N-type diffusion layer 92 as a drain and an N-type diffusion layer 93 as a source. These N-type diffusion layers 9
A tunnel oxide film 95 is formed on P-type semiconductor substrate 94 between 2 and 93, a floating gate 91 is formed on tunnel oxide film 95, and an oxide film 96 is formed on floating gate 91. A control gate 90 is formed on the film 96. A nonvolatile memory has a large number of memory cells arranged in a matrix, and data is written to and read from memory cells selected by a row decoder and a column decoder. To write data into the memory cell, a high voltage is applied to the control gate 90 and the drain diffusion layer 92, and a channel current flows from the drain diffusion layer 92 to the source diffusion layer 93 with the source diffusion layer 93 grounded. To generate hot electrons, and the hot electrons are injected into the floating gate 91 through the tunnel oxide film 95. This data writing raises the threshold value of the memory cell from 2V to about 6V. Reading of data from the non-volatile memory is performed using a change in the threshold value of the selected memory cell.

Next, a data writing operation of a conventional nonvolatile memory will be described with reference to a circuit diagram.

[0004] As shown in FIG. 4, a circuit configuration of a conventional nonvolatile memory is schematically represented by a large number of memory cells 50, 51, 52, 53,.
, A row decoder 1 for selecting a specific row (word lines 2 and 3) in the memory cell array 63, and a column decoder 54 for selecting a specific column (bit lines 61 and 62). VPM generation circuit 84 for generating a voltage VPM used for the operation of row decoder 1 and the like and a reference voltage
And a reference voltage generating circuit 4, a write circuit 55 for writing data to a memory cell selected by the row decoder 1 and the column decoder 54, and a sense amplifier 56 for reading data from the selected memory cell. It is configured to have.

In the memory cell array 63, memory cells 50, 51, 52, 53,...
Of the cells belonging to the same row are connected to word lines 2 and 3, and the drains of the cells belonging to the same column are connected to bit lines 61 and
62. The bit lines 61 and 62 are connected to the write circuit 55 and the sense amplifier 56 via N-channel transistors 57 and 58, and apply column select signals 59 and 60 from the column decoder 54 to the N-channel transistor 5
7 and 58, the bit lines 61,
There are 62 selections.

The row decoder 1 includes address signals A0, A1
And a two-input NAND 22 having an address signal A0
19, and a two-input N which receives an address signal A1 and an output signal 20 of the inverter 19 as inputs.
The address signal is decoded by AND21 and the source is V
DD, P-channel transistor 1 having gate connected to output signal 17 of 2-input NAND 22 and drain connected to contact 25
3, an N-channel transistor 12 whose source is GND, whose gate is the output signal 17, and whose drain is connected to the contact 25.
And the control signal 6 as a gate input, the N-channel transistor 11 connected to the contact 25 and the word line 2, and the gate is connected to the reference voltage signal 5 and the output signal 17, respectively. The bit line 2 is driven by the P-channel transistors 7 and 8 connected in series to the source, the source is DD, and the gate is the output signal 1 of the two-input NAND 21.
8, the P-channel transistor 14 whose drain is connected to the contact 26, the source is GND, the gate is the output signal 18,
An N-channel transistor 15 having a drain connected to a contact 26, a control signal 6 as a gate input, an N-channel transistor 16 connected to the contact 26 and the word line 3, and a gate connected to a reference voltage signal 5 and an output signal 18, respectively. The bit line 3 is configured to be driven by the internally generated voltage line PM and the P-channel transistors 9 and 10 connected in series to the word line 3.

The reference voltage signal line 5 in the row decoder 1 is connected to the output of the reference voltage generation circuit 4. The reference voltage generation circuit 4 includes an internally generated voltage line PM, a resistance element 29 connected to the reference voltage signal 5, The resistance element 23 connected to the voltage signal 5 and the contact 28, the source is GND, and the gate is the control signal 2
4. An N-channel transistor 27 whose drain is connected to the contact 28.

The internally generated voltage line P in row decoder 1
M is connected to the output of a VPM generation circuit 84. The VPM generation circuit 84 has a control signal 80 as a gate input, and gates a P-channel transistor 81 connected to the voltage VPP and the internally generated voltage line PM, and a control signal 82. It is constituted by a P-channel transistor 83 that is connected to the voltage VDD and the internally generated voltage line PM. Voltage VD
D is about 5V. On the other hand, the voltage VPP is a power supply that supplies a voltage applied to the control gate of the memory cell at the time of writing to the memory cell, and a voltage of about 10 V, which is sufficiently higher than the voltage VDD, is supplied.

Next, the write operation will be described.
It is assumed that data is written to the memory cell transistor 50.

First, selection of a bit line will be described.
The column select signals 59 and 60 are set to low level and high level, respectively, and the N-channel transistors 57 and 58 are turned off and on, respectively, to activate the bit line 62. A write voltage to be supplied to the drain of the memory cell is output from the write circuit 55, and is output via the N-channel transistor 58.
This write voltage is supplied to the bit line 62.

Next, selection of a word line will be described. At the time of writing to the memory cell, the control signals 80 and 82 are set to low level and VPP, respectively, so that the P-channel transistors 81 and 83 are turned on and off, respectively. Therefore, the voltage is supplied from the VPP to the internally generated voltage line PM. You. This voltage value is represented as VPM.

The potential of the reference voltage signal 5 is supplied from an internally generated voltage line PM, and the control signal 24 is set to a high level.
When the channel transistor 27 is turned on, the potential is determined by the resistance ratio of the resistance elements 29 and 23. Here, the potential of the reference voltage signal 5 is set to be lower as the P-channel transistors 7 and 9 are turned on, and set to a potential of about 9 V so as to minimize the on-current of the P-channel transistors 7 and 9.

When writing to the memory cell transistor 50, the address signals A0 and A1 are input at a high level so as to select the word line 2, and the two-input NAND2
2 becomes low level, the P-channel transistors 13 and 8 are turned on, and the N-channel transistor 1 is turned on.
2 is off. Here, by setting the control signal 6 to the high level, the word line 2 is charged to VPM via the P-channel transistors 7 and 8, and the N-channel transistor 11 has the contact 25, the control signal 6 having the high level and the word Line 2 is turned off by VPM.

Next, the potential of the unselected word line 3 is
It becomes low level by the following operation. Address signal A0
Is high, the output signal 20 of the inverter 19
Is low level, the output signal 18 of the two-input NAND 21 becomes high level, the P-channel transistor 14 is turned off, and the N-channel transistor 15 is turned on. Also,
The P-channel transistor 9 is turned on by the reference voltage signal 5, and the P-channel transistor 10 has the output signal 18, which is the gate input, at a high level, but sufficiently lower than VPM supplied to the source via the P-channel transistor 9. ON because of voltage, N-channel transistor 1
5 and 16 are turned on because the output signal 18 and the control signal 6 are high level. Therefore, a current constantly flows from the internally generated voltage line PM to GND, and the current value is determined by the on-resistance of the P-channel transistors 9 and 10 and the N-channel transistors 15 and 16. At this time, the on-state current of the P-channel transistor 9 is set to be as small as possible by the reference voltage signal 5, so that the on-state resistance of the P-channel transistor 9 is compared with the on-state resistance of the N-channel transistors 15 and 16. It is sufficiently large, and the potential of the word line 3 becomes low level.

As described above, at the time of writing to a memory cell, VPM is applied to the selected word line and the other unselected word lines are at the low level. Current flows. This current is VPP
, And flows through all non-selected word lines, so that the total current value increases. When the total current value increases, VPM becomes V
It will be lower than PP.

Next, the decrease in the potential of the VPM will be described with reference to FIG. FIG. 5 equivalently shows a path flowing from PPP to P-channel transistors 7, 8, 9, and 10 from P-channel transistor 81 through internally generated voltage line PM. 4, a resistor R1 is an on-resistance of the P-channel transistor 81 of FIG. 4, and a resistor R2 is a P-channel transistor 7 connected to the selected word line 2.
The on resistance 8 and the resistance R3 represent the on resistances of the P-channel transistors 9 and 10 and the N-channel transistors 15 and 16 connected to the unselected word line 3. Here, the current that constantly flows through the unselected word lines is defined as I3. Since the word line selected at the time of writing is one in all the word lines, the total number of non-selected word lines excluding the one is n,
Assuming that the current flowing from the VPP is I1, the current I1 is n times the current I3. The VPM applied to the selected word line can be expressed by the following equation.

VPM = VPP-R1 × I1 = VPP-R
1 × (I3 × n) Therefore, increasing the memory cell capacity means increasing the number of word lines. Therefore, in a large-capacity nonvolatile memory, the number n of non-selected word lines increases, so that the VPP of the VPM increases.
The voltage drop from.

When the number n of the non-selected word lines increases, as a method of suppressing the decrease in the VPM, it is conceivable to reduce the resistance R1 and the current I3. The size of the P-channel transistor 81 must be increased in proportion to the total number n of the unselected word lines. To reduce the current I3 that increases the chip area, the output voltage of the reference voltage signal 5 must be increased. However, it is difficult to realize the P-channel transistor 7 connected to the selected word line 2 because there is a limit when considering that the P-channel transistor 7 must be turned on reliably.

[0019]

As described above, the conventional non-volatile memory has a problem that the current consumption at the time of writing increases because a steady current flows through the non-selected word lines. In addition, due to the increase in the number of word lines due to the increase in the memory cell capacity, the number of non-selected word lines at the time of writing increases, the total current constantly flowing through the many word lines increases, and the voltage of the selected word lines decreases. There has been a problem that the voltage becomes lower than the expected voltage and the writing speed is reduced.

An object of the present invention is to reduce a current constantly flowing through an unselected word line. In addition, an increase in the number of word lines accompanying an increase in memory cell capacity prevents an increase in current flowing through all non-selected word lines at the time of writing, prevents a selected word line voltage from lowering, and thereby prevents a writing speed from lowering. It is in.

[0021]

According to the present invention, a voltage supply transistor circuit for supplying a voltage to a control gate of a memory cell at the time of writing to a memory cell is provided by a nonvolatile memory having a row decoder having the number of rows of a memory cell matrix. In a nonvolatile memory, a voltage supply transistor circuit is divided into a plurality of blocks, and a nonvolatile memory is obtained in which the voltage supply capability of the voltage supply transistor circuit in each block can be controlled according to an address.

The voltage supply transistor circuit includes a transistor having a gate receiving a control voltage in series, and the voltage supply capability can be controlled by the control voltage. Further, the voltage supply capability of the voltage supply transistor circuit can be reduced by the voltage supply transistor circuit when a memory cell to which a voltage is supplied to the control gate is not selected by an address.

According to the present invention, the word line selected by the address or the word line of the selected block includes:
A current flows constantly, but no current flows through unselected word lines or word lines of unselected blocks. This makes it possible to reduce the total current flowing through the unselected word lines irrespective of the number of unselected word lines, thereby preventing a voltage drop on the selected word lines.

[0024]

Next, embodiments of the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a schematic diagram of a circuit showing a configuration of a nonvolatile memory according to a first embodiment of the present invention. FIG.
, The same reference numerals are given to the same parts as those in the conventional example in FIG.

In the present embodiment, the reference voltage generating circuit 4 of the conventional circuit configuration is configured to generate a plurality of reference voltages controlled by addresses. That is, the reference voltage generating circuit 4 is a two-input NAN that receives the control signal 24 and the address signal A0 as inputs.
D108, the inverter 110 having the gate input of the output signal 109 of the two-input NAND, and the inverter 1
An N-channel transistor 27 having a gate receiving the output 111 of the N-channel transistor 10, a resistor 23 connected to the drain of the N-channel transistor 27 at a contact 28, and a resistor 29 connected between the resistor 23 and the internally generated voltage line PM. Including
A portion for generating a first reference voltage on a reference voltage signal line 5 connected to a connection point between the resistors 23 and 29, and a two-input NAND 104 having a control signal 24 and an output signal 20 as gate inputs
And an inverter 106 having an output signal 105 of the two-input NAND 104 as a gate input, and an inverter 10
6, an N-channel transistor 103 whose drain is connected to the contact 112 and whose source is connected to GND, the resistor 102 connected to the contact 112,
A portion including a resistance element 101 connected between the internally generated voltage line PM and the resistor 102, and generating a second reference voltage on a reference voltage signal line 100 connected to a connection point between the resistors 101 and 102; have.

Next, the write operation of this embodiment will be described.

When writing data to the memory cell transistor 50, the address signal A0 and the control signal 24 are at high level, the output signal 109 is at low level, the output signal 111 is at high level, and the reference voltage signal line 5 is connected to the reference voltage signal line 5. And a voltage of about 9 V is output, and VPM is applied to the selected word line 2.

On the other hand, since the output signal 20 is at a low level, the output signal 105 is at a high level, the output signal 107 is at a low level, and the reference voltage signal 100 is at VPM.
Therefore, the P-channel transistor 9 connected to the unselected word line 3 is turned off, and the N-channel transistors 15, 1
Since 6 is on, the unselected word line 3 goes low, but there is no steady current flowing through the unselected word line 3 because the P-channel transistor 9 is off.

Although there are two word lines in FIG. 1, there are actually many word lines, and transistors 7 and
8 and transistors 9 and 10 for voltage supply. These voltage supply transistors are divided into blocks for each of a plurality of word lines, and a reference voltage is supplied from the reference voltage generation circuit 4 'for each block. Of course, a reference voltage corresponding to the number of word lines is generated from the reference voltage generation circuit 4 ', and a reference voltage of 9 V is applied only to the voltage supply transistor connected to the word line having the selected memory cell. May be provided with a VPM reference voltage.

As described above, a word line unit or a word line of a row is divided into blocks, and the reference voltage signal lines (5, 100) are divided in units of the blocks. By selecting the address to output the VPM or the reference voltage, the steady current flowing through the unselected word line can be eliminated or limited to only one block including the selected word line. Therefore, even when the number of word lines increases as the number of memory cells increases, the steady current flowing through the unselected word lines does not increase.

For example, when it is desired to double the number of word lines, the voltage supply transistor circuits of the transistors 7, 8, 9 and 10 of the row decoder 1 are divided into two blocks, and the reference voltage from the reference voltage generation circuit 4 '. By dividing the signal into two, one block receives the reference voltage and the other block receives the VPM from the reference voltage signal line (5, 100). The total current flowing through the word line does not change. Therefore, it is possible to suppress an increase in the voltage drop of the selected word line.

Even if the number of word lines does not increase, the voltage supply transistor circuits of the transistors 7, 8, 9 and 10 of the row decoder 1 are divided into certain blocks, and if the reference voltage is divided, a non-selected word line can be obtained. Since the flowing steady current is reduced, the reduction in VPM can be further suppressed and the power consumption can be reduced.

Here, the optimum number of block divisions of the row decoder may be determined in consideration of an allowable voltage drop of the selected word line and an increase in chip area due to an increase in the number of elements of the reference voltage generation circuit.

FIG. 2 is a schematic diagram of a circuit showing a configuration of a nonvolatile memory according to a second embodiment of the present invention.

In the present embodiment, the reference voltage generating circuit 4 ″ includes the resistor 29 connected to the internally generated voltage line PM and the contact 204, the resistor 23 connected to the contact 204 and the contact 28, and the drain connected to the contact 28. Gate is control signal 2
4. N-channel transistor 27 whose source is connected to GND, and whose gate inputs are control signal 24 and address signal A0
, A P-channel transistor 207 whose source is the internally generated voltage line PM, whose gate is connected to the contact 205 and whose drain is connected to the contact 206, whose drain is the contact 206, whose output is the output signal 212 of the two-input NAND 214, and whose source is GND , An N-channel transistor 211 having a source connected to the internally generated voltage line PM, a gate connected to the contact 206, a drain connected to the contact 205, an inverter 213 having the output signal 212 as a gate input, and a drain connected to the contact 205. The gate is the output signal 210 of the inverter 213 and the source is G
An N-channel transistor 209 connected to ND, a contact 206 is used as a gate input, a P-channel transistor 200 connected to the contact 204 and the reference voltage signal line 100, and a contact 205 is used as a gate input, and an internally generated voltage line PM and a reference voltage signal line 100 are used. P-channel transistor 2 connected to
01 and the P-channel transistor 20 connected to the contact 204 and the reference voltage signal line 5 using the contact 205 as a gate input.
2 and the contact 206 as a gate input, and the internally generated voltage line P
M and a P-channel transistor 203 connected to the reference voltage signal line 5.

When writing data to the memory cell transistor 50, the address signal A0 is at the high level and the control signal 24 is at the high level. Therefore, the output signal 212 of the two-input NAND 214 is at the low level, and the output signal 210 of the inverter 213 is at the high level. , N-channel transistors 209 and 211 are turned on and off, respectively. Here, the contact 205 becomes low level, the P-channel transistor 207 turns on, the contact 206 turns to VPM, and the P-channel transistor 208 turns off. Also, the contact 204
Since the control signal 24 is at a high level, the potential becomes about 9 V, which is the reference voltage.
Since 6 is low level and VPM, P channel transistors 200 and 201 are off and on, respectively, and P channel transistors 202 and 203 are on and off respectively. As a result, the reference voltage is output to the reference voltage signal line 5, and VPM is output to the reference voltage signal line 100.

Therefore, the P-channel transistor 7 connected to the selected word line 2 is turned on, and supplies VPM to the word line 2. Further, the P-channel transistor 9 connected to the unselected word line 3 is turned off, and the word line 3 becomes low level, but no steady current flows.

Although the preferred embodiments have been described above, the present invention is not limited to these embodiments, and various modifications are possible.

For example, when the voltage of the power supply VDD is 5 V and the power supply V
The PP voltage is set to 10 V and the reference voltage is set to 9 V. These voltages can be appropriately selected as long as the values can satisfy the writing characteristics. The resistance element used in the reference voltage generation circuit is , Can be replaced with a transistor.

[0041]

According to the present invention, a voltage supply transistor circuit for supplying a voltage to a control gate of a memory cell when writing to a memory cell is provided in a nonvolatile memory having a row decoder having the number of rows of a memory cell matrix. By dividing into a plurality of blocks and allowing the voltage supply capability of the voltage supply transistor circuit of each block to be selected according to the address, even if the number of word lines increases with the increase in the memory cell capacity, An increase in the total amount of current flowing through the selected word line can be prevented, and accordingly, a voltage drop of the selected word line can be suppressed. In addition, the writing speed does not decrease due to the increase in the memory cell capacity.

Even if the number of word lines does not increase, the voltage supply transistor circuit of the row decoder is divided into certain blocks, and the voltage supply capability of the voltage supply transistor circuit is controlled for each block, so that the non-selected word line Since the total amount of the steady current flowing through the word line decreases, the voltage drop of the selected word line can be further suppressed, and the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a nonvolatile memory according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the nonvolatile memory of the present invention.

FIG. 3 is a cross-sectional view illustrating a structure of a memory cell transistor.

FIG. 4 is a circuit diagram showing a configuration of a conventional nonvolatile memory circuit.

FIG. 5 is a diagram equivalently showing a steady current flow path at the time of writing in a conventional nonvolatile memory.

[Explanation of symbols]

1 row decoder 2,3 word line 4,4 ', 4''reference voltage generating circuit 5,100 reference voltage signal line 6,24,80,82 control signal 7,8,9,10,13,14,81, 83,200,
201, 202, 203, 207, 208 P-channel transistors 11, 12, 15, 16, 27, 57, 58, 103,
209, 211 N-channel transistor PM Internally generated voltage line 17, 18, 20, 105, 107, 109, 111,
210, 212 Output signal 19, 106, 110, 213 Inverter 21, 22, 104, 108, 214 2-input NAN
D 23, 29, 101, 102 Resistance 50, 51, 52, 53 Memory cell 54 Column decoder 55 Write circuit 56 Sense amplifier 59, 60 bit select signal 61, 62 bit line 63 Memory cell array A0, A1 Address signal

Claims (8)

[Claims] 1. A memory cell array in which memory cells are arranged in rows and columns, and a voltage supply transistor circuit that supplies a voltage to a control gate of the memory cell when writing data to the memory cell, according to the number of the rows. A nonvolatile memory comprising a row decoder having a plurality of blocks, wherein the voltage supply transistor circuit is divided into a plurality of blocks, and a voltage supply capability of the voltage supply transistor circuit in each block is controlled according to an address applied to the row decoder. A nonvolatile memory characterized in that it is made possible. 2. The voltage supply transistor circuit supplies a high-level voltage when included in a block of a voltage supply transistor circuit that supplies a voltage to a control gate of a memory cell selected by the address.
2. The nonvolatile memory according to claim 1, wherein a low-level voltage is supplied when not included in a block of a voltage supply transistor circuit that supplies a voltage to a control gate of a memory cell selected by the address. Sex memory. 3. The voltage supply transistor circuit according to claim 1, wherein the voltage supply transistor circuit includes a switching transistor which performs a switching operation by receiving a control voltage at a gate, and supplies a voltage to a control gate of a memory cell selected by the address. When included in a block, the switching transistor has a low resistance, and when not included in a block of a voltage supply transistor circuit that supplies a voltage to a control gate of a memory cell selected by the address, the switching transistor has a high resistance. The nonvolatile memory according to claim 1, wherein: 4. The nonvolatile memory according to claim 1, wherein each of said blocks includes a plurality of said voltage supply transistor circuits. 5. The nonvolatile memory according to claim 1, wherein each of said blocks includes one of said voltage supply transistor circuits. 6. A plurality of voltage supply transistors for supplying a voltage to a control gate of a nonvolatile memory cell according to a control voltage applied to the gate when writing data to the nonvolatile memory cell, wherein the plurality of voltage supply transistors are provided. Wherein the control voltage is applied to each block of the voltage supply transistor, and the applied control voltage can be selected according to an address applied for selecting the nonvolatile memory cell. memory. 7. The control voltage, when being included in a block of a voltage supply transistor that supplies a voltage to a control gate of a nonvolatile memory cell selected by the address, turns on the voltage supply transistor. 7. The voltage according to claim 6, wherein the voltage is a voltage that turns off the voltage supply transistor when the voltage supply transistor is not included in a block of a voltage supply transistor that supplies a voltage to a control gate of the nonvolatile memory cell selected by the address. Non-volatile memory. 8. The nonvolatile memory according to claim 6, wherein the number of blocks of the voltage supply transistor is two.