JPH0292554U

JPH0292554U -

Info

Publication number: JPH0292554U
Application number: JP17127088U
Authority: JP
Priority date: 1988-12-28
Filing date: 1988-12-28
Publication date: 1990-07-23

Description

[Brief explanation of drawings]

第１図は本考案の第１の実施例に係る受信機を
示す外観図、第２図は同実施例の受信機内部の回
路構成を示すブロツク図、第３図は同実施例で採
用した送信信号フオーマツトを示す図、第４図は
データの種類とレース識別コードとの関係を示す
図、第５図は第２図中のＲＡＭ１３の主要内容を
示す模式構成図、第６図は上記実施例の全体的な
処理動作を示すフローチヤート、第７図は第６図
中の受信データ取り込み処理（ステツプａ_１３）
を具体的に示すフローチヤート、第８図は第６図
中のキー処理（ステツプａ_５）を具体的に示すフ
ローチヤート、第９図は第８図中のその他のキー
処理（ステツプｃ_１１）において枠指定キーＳ_４を操作した際の処理を具体的に示すフローチヤー
ト、第１０図はキー操作による表示部２の表示の
切り換わりを示す図、第１１図は本考案の第２の
実施例に係る受信機を示す外観図、第１２図は同
実施例におけるＲＡＭ１３の主要内容を示す模式
構成図、第１３図、第１４図及び第１５図は同実
施例における受信データ取り込み処理、全体的な
キー処理、及びデータ種類指定キーＳ_７を操作し
た際のキー処理を具体的に示すフローチヤート、
第１６図はキー操作による表示部２の表示の切り
換わりを示す図、第１７図は本考案の他の実施例
に係る受信機内部の回路構成の一部を示すブロツ
ク図、第１８図は上記他の実施例で採用した送信
信号フオーマツトを示す図である。２……表示部、４……受信回路、５……入力同
期回路、６……ＢＣＨ誤り訂正回路、７……プリ
アンブル検出回路、８……同期コード検出回路、
９……Ｓ−Ｐ変換回路、１０……受信タイミング
制御回路、１１……ＣＰＵ、１３……ＲＡＭ、１
４……演算回路、１５……表示バツフア、１６…
…表示ドライバ、２１……ＩＤ−ＲＯＭ、２２…
…アドレス一致検出回路、Ｋ……レース識別コー
ドレジスタ、Ｓ……タイマレジスタ、Ｌ……受信
可否フラグ、Ｃ……枠指定ポインタ、Ｒ……レー
ス結果レジスタ、Ｘ……オツズレジスタ、Ｙ……
体重レジスタ、Ｚ……重馬場レジスタ、Ｄ……種
類指定ポインタ、Ｑ_１……１枠レジスタ、Ｑ_２…
…２枠レジスタ、Ｑ_３……３枠レジスタ、Ｓ_１…
…レース指定キー、Ｓ_２……サーチキー、Ｓ_３…
…データ種類指定キー、Ｓ_４……枠指定キー、Ｓ
_６……枠指定キー、Ｓ_７……データ種類指定キー
。 Fig. 1 is an external view showing a receiver according to the first embodiment of the present invention, Fig. 2 is a block diagram showing the internal circuit configuration of the receiver of the same embodiment, and Fig. 3 is a diagram showing the receiver according to the first embodiment. Figure 4 is a diagram showing the transmission signal format, Figure 4 is a diagram showing the relationship between data types and race identification codes, Figure 5 is a schematic configuration diagram showing the main contents of the RAM 13 in Figure 2, and Figure 6 is a diagram showing the above implementation. A flowchart showing the overall processing operation of the example, FIG. 7 is the received data import process (step _a13 ) in FIG.
8 is a flowchart specifically showing the key processing (step _a5 ) in FIG. 6, and FIG. 9 is a flowchart specifically showing the key processing (step _c11 ) in FIG. 8. Frame designation key S ₄ 10 is a flowchart specifically showing the processing when operating the , FIG. 10 is a diagram showing switching of the display on the display unit 2 by key operation, and FIG. FIG. 12 is a schematic configuration diagram showing the main contents of the RAM 13 in the same embodiment, and FIGS. 13, 14, and 15 show received data import processing, overall key processing, and A flowchart specifically showing the key processing when operating the data type specification key _S7 ,
FIG. 16 is a diagram showing switching of the display on the display section 2 by key operation, FIG. 17 is a block diagram showing a part of the circuit configuration inside the receiver according to another embodiment of the present invention, and FIG. FIG. 7 is a diagram showing a transmission signal format adopted in the other embodiment. 2... Display unit, 4... Receiving circuit, 5... Input synchronization circuit, 6... BCH error correction circuit, 7... Preamble detection circuit, 8... Synchronization code detection circuit,
9...S-P conversion circuit, 10...Reception timing control circuit, 11...CPU, 13...RAM, 1
4...Arithmetic circuit, 15...Display buffer, 16...
...Display driver, 21...ID-ROM, 22...
...Address match detection circuit, K...Race identification code register, S...Timer register, L...Reception availability flag, C...Frame designation pointer, R...Race result register, X...Otsuzu register, Y...
Weight register, Z... Heavy Baba register, D... Type designation pointer, Q ₁ ... 1 frame register, Q ₂ ...
...2-frame register, Q ₃ ...3-frame register, S ₁ ...
...Race specification key, _S2 ...Search key, _S3 ...
…Data type specification key, S ₄ …Frame specification key, S
₆ ...Frame specification key, _S7 ...Data type specification key.

Claims

[Scope of Claim for Utility Model Registration] (1) Race specifying means for specifying a desired race from among a plurality of races; receiving means for receiving various data related to the race; and among the data received by the receiving means, storage means for storing only various data related to the race designated by the race designation means for each type; runner designation means for designating a desired runner from among a plurality of runners for the designated race; , editing means for extracting and editing only data regarding the runner specified by the runner specifying means from among all the data stored by type in the storage means; and displaying the data edited by the editing means. A receiver comprising display means for displaying. (2) race designation means for designating a desired race from among a plurality of races; reception means for receiving various data regarding the race; a storage means for storing only various data related to the race for each runner; a data type specifying means for specifying a desired type of data from among multiple types of data related to the race; The present invention is characterized by comprising: editing means for extracting and editing only data of the type specified by the data type specifying means from among all the data; and display means for displaying the data edited by the editing means. receiver.