JPH0292549U - - Google Patents
Info
- Publication number
- JPH0292549U JPH0292549U JP17126588U JP17126588U JPH0292549U JP H0292549 U JPH0292549 U JP H0292549U JP 17126588 U JP17126588 U JP 17126588U JP 17126588 U JP17126588 U JP 17126588U JP H0292549 U JPH0292549 U JP H0292549U
- Authority
- JP
- Japan
- Prior art keywords
- data
- display
- match
- receiver
- error
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 9
- 238000013500 data storage Methods 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例に係る受信機を示す
外観平面図、第２図は本実施例の受信機内部の回
路構成を示すブロツク図、第３図は本実施例で採
用した送信信号フオーマツトを示す図、第４図は
第２図中のＲＡＭ１１の主要内容を示す模式構成
図、第５図は第２図中のＲＡＭ１５の主要内容を
示す模式構成図、第６図は本実施例の全体的な処
理動作を示すフローチヤート、第７図は第６図中
の受信データ取り込み処理（ステツプａ１３）を
具体的に示すフローチヤート、第８図及び第９図
は第６図中のキー処理（ステツプａ５）のうち、
読み出しキーＳ１の操作時と確認キーＳ２の操作
時のそれぞれの処理を具体的に示すフローチヤー
ト、第１０図はＲＡＭ１５に各レースの予測デー
タが記憶された場合の一例を示す図、第１１図は
ＲＡＭ１１に受信データが記憶された場合の一例
を示す図、第１２図はＲＡＭ１５に各レース毎の
払い戻し金額データが記憶された場合の一例を示
す図、第１３図は読み出しキーＳ１と確認キーＳ
２の操作に基づく表示部２の表示状態の切り換わ
りを示す図、第１４図は本考案の他の実施例に係
る受信機内部の回路構成の一部を示すブロツク図
、第１５図は上記他の実施例で採用した送信信号
フオーマツトを示す図である。
２……表示部、４……受信回路、５……入力同
期回路、６……ＢＣＨ誤り訂正回路、７……プリ
アンブル検出回路、８……同期コード検出回路、
９……Ｓ−Ｐ変換回路、１０……受信タイミング
制御回路、１１……受信データ記憶用のＲＡＭ、
１２……ＲＡＭ制御部、１３……ＣＰＵ、１５…
…予想データ記憶用のＲＡＭ、１６……演算回路
、１７……表示バツフア、１８……表示ドライバ
、２１……ＩＤ−ＲＯＭ、２２……アドレス一致
検出回路、Ｎ……受信データレジスタ、Ｄ……結
果データ記憶部、Ｅ……配当データ記憶部、Ｆ…
…誤りなしフラグ、Ｍ……予想データレジスタ、
Ｇ……予想データ記憶部、Ｈ……購入金額記憶部
、Ｉ……払い戻し金額記憶部、Ｊ……的中フラグ
、Ｒ１〜Ｒ１０……予想本数レジスタ、Ｃ……レ
ース指定レジスタ、Ｐ……表示ポインタ、Ｓ……
タイマレジスタ、Ｌ……受信可否フラグ、Ｓ１…
…読み出しキー、Ｓ２……確認キー、Ｓ３……デ
ータ入力キー、Ｓ４……レースキー、Ｓ５……エ
ンターキー。
Fig. 1 is an external plan view showing a receiver according to an embodiment of the present invention, Fig. 2 is a block diagram showing the internal circuit configuration of the receiver of this embodiment, and Fig. 3 is a transmitter employed in this embodiment. 4 is a schematic configuration diagram showing the main contents of RAM 11 in FIG. 2, FIG. 5 is a schematic configuration diagram showing the main contents of RAM 15 in FIG. 2, and FIG. 6 is a diagram showing the main contents of RAM 15 in FIG. 2. A flowchart showing the overall processing operation of the example, FIG. 7 is a flowchart specifically showing the received data importing process (step a13 ) in FIG. 6, and FIGS. 8 and 9 are in FIG. Of the key processing (step a5 ),
10 is a flowchart specifically showing the respective processes when operating the read key S1 and when operating the confirm key S2 . FIG. FIG. 11 is a diagram showing an example of the case where received data is stored in the RAM 11, FIG. 12 is a diagram showing an example of the case where the payout amount data for each race is stored in the RAM 15, and FIG. 13 is a diagram showing an example of the case where the received data is stored in the RAM 15. and confirmation key S
FIG . 14 is a block diagram showing a part of the circuit configuration inside the receiver according to another embodiment of the present invention, and FIG. FIG. 7 is a diagram showing a transmission signal format adopted in another embodiment. 2... Display unit, 4... Receiving circuit, 5... Input synchronization circuit, 6... BCH error correction circuit, 7... Preamble detection circuit, 8... Synchronization code detection circuit,
9... S-P conversion circuit, 10... Reception timing control circuit, 11... RAM for storing received data,
12...RAM control unit, 13...CPU, 15...
...RAM for storing predicted data, 16... Arithmetic circuit, 17... Display buffer, 18... Display driver, 21... ID-ROM, 22... Address match detection circuit, N... Reception data register, D... ...Result data storage section, E...Payout data storage section, F...
...No error flag, M...Expected data register,
G... Forecast data storage unit, H... Purchase amount storage unit, I... Refund amount storage unit, J... Hit flag, R1 to R10 ... Expected number of tickets register, C... Race designation register, P ...Display pointer, S...
Timer register, L...Reception availability flag, S1 ...
...read key, S2 ...confirmation key, S3 ...data input key, S4 ...race key, S5 ...enter key.
Claims (1)
を入力する入力手段と、 該入力手段で入力された複数の予想データを記
憶する記憶手段と、 該記憶手段に記憶された複数の予想データを同
時に表示する表示手段と、 実際のレース結果を示す結果データを受信する
受信手段と、 該受信手段で受信された結果データと前記記憶
手段に記憶されている予想データとの一致を判別
する一致判別手段と、 前記表示手段によつて表示されている複数の予
想データのうち、前記一致判別手段により結果デ
ータとの一致が判別された予想データを、その他
の予想データとは表示態様を異ならせて表示させ
る表示制御手段とを備えたことを特徴とする受信
機。 (2) 前記受信手段は受信データの誤りを検出す
る誤り検出手段を有し、該誤り検出手段で受信デ
ータに誤りが無いと判別された時だけ、該受信デ
ータを取り込んで前記表示手段に表示させること
を特徴とする請求項(1)記載の受信機。 (3) 前記受信手段は受信データの誤りを検出す
る誤り検出手段を有し、該誤り検出手段で誤りの
確率の高いデータが検出された時は、該データの
誤りの確率が高いことを前記表示手段で明示する
ことを特徴とする請求項(1)記載の受信機。 (4) 前記受信手段は一連の結果データの受信が
完了する毎に受信完了信号を出力し、前記一致判
別手段及び前記表示制御手段を動作させることを
特徴とする請求項(1)乃至(3)のいずれか１つに記
載の受信機。 (5) 前記入力手段によるキー入力があつた時は
、該キー入力に基づく処理を他の処理よりも優先
させることを特徴とする請求項(1)乃至(4)のいず
れか１つに記載の受信機。[Scope of Claim for Utility Model Registration] (1) An input means for inputting a plurality of prediction data predicting the result of a race, a storage means for storing a plurality of prediction data inputted by the input means, and the storage means. Display means for simultaneously displaying a plurality of stored prediction data; Receiving means for receiving result data indicating actual race results; and Result data received by the receiving means and prediction data stored in the storage means. a match determination means for determining a match with the result data; and a match determination means for determining a match with the result data from among the plurality of predicted data displayed by the display means, the predicted data that is determined to be a match with the result data by the match determination means, and other predicted data. A receiver comprising display control means for displaying a display in a different manner from the receiver. (2) The receiving means has an error detection means for detecting errors in the received data, and only when the error detection means determines that there is no error in the received data, the received data is captured and displayed on the display means. The receiver according to claim (1), characterized in that: (3) The receiving means has an error detection means for detecting errors in the received data, and when the error detection means detects data with a high probability of error, the above-mentioned method indicates that the probability of error in the data is high. 2. The receiver according to claim 1, wherein the information is clearly indicated by display means. (4) Claims (1) to (3) characterized in that the receiving means outputs a reception completion signal every time the reception of a series of result data is completed, and operates the coincidence determining means and the display control means. ). (5) According to any one of claims (1) to (4), when a key input is made by the input means, processing based on the key input is given priority over other processing. receiver.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988171265U JP2525255Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
| US07/456,852 US5212636A (en) | 1988-12-28 | 1989-12-26 | Radio receiver capable of confirming gambling results |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988171265U JP2525255Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0292549U true JPH0292549U (en) | 1990-07-23 |
| JP2525255Y2 JP2525255Y2 (en) | 1997-02-05 |
Family
ID=31462946
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988171265U Expired - Lifetime JP2525255Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2525255Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60262272A (en) * | 1984-06-08 | 1985-12-25 | Omron Tateisi Electronics Co | Portable share rate data receiver |
| JPS62186357A (en) * | 1986-02-13 | 1987-08-14 | Fujitsu Ltd | Method for payment processing of pari-mutuel ticket |
-
1988
- 1988-12-28 JP JP1988171265U patent/JP2525255Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60262272A (en) * | 1984-06-08 | 1985-12-25 | Omron Tateisi Electronics Co | Portable share rate data receiver |
| JPS62186357A (en) * | 1986-02-13 | 1987-08-14 | Fujitsu Ltd | Method for payment processing of pari-mutuel ticket |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2525255Y2 (en) | 1997-02-05 |
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