JP2525255Y2 - Receiving machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a receiver that can wirelessly receive the results of various races such as horse racing, bicycle racing, boat racing, and auto racing.

[Prior art and its problems]

Conventionally, as a means for knowing the result of the race as described above, there is a means for receiving and listening to a short-wave broadcast that is being played in the stadium to notify the race result with a dedicated receiver. .

However, in this case, there are the following problems. (1) Since the above-mentioned receiver only unidirectionally emits sounds and voices like a general radio, there is a possibility that a necessary race result may be missed. (2) The race result cannot be known until the shortwave broadcast announcer speaks. (3) Since the race results cannot be stored in the above receiver, if you want to know the race results before this time, you have to go to the place where it is posted. is there.
(4) Outside the stadium, the above shortwave broadcast cannot be received, and unless the desired race is broadcast on a general radio or television, the result of the race cannot be immediately known. When I wanted to know the result, I had to know it by a service phone or a newspaper.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to enable the player to immediately know the result of the race, and also to easily know whether or not his / her prediction was correct. It is to provide a receiver.

[Points of the invention]

According to the present invention, in order to achieve the above-mentioned object, the race result data transmitted by radio is received and immediately (automatically without key operation), immediately compared with predicted data stored in advance, and matched. In this case, the prediction data is displayed in a different display form from the other prediction data.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is an external plan view showing a receiver according to an embodiment of the present invention. The receiver according to the present embodiment is lent out in a racetrack, and is configured to be able to receive race result data transmitted from a predetermined transmitting station in the racetrack.

In FIG. 1, a display unit 2 composed of a liquid crystal display device or the like for displaying expected data and result data of a race is disposed above a front portion of a receiver main body 1. And
Various keys S _{1 to} S ₅ are arranged below the display unit 2. Here, the key S ₁ is the expected data and the purchase price data of the race are stored in the read key for displaying is switched for each race. Key S _2, when the expected data of the race has been hit, is a confirmation key for displaying the refund amount of money or the like. Key S ₃ is a data input key for inputting various types of data such as the expected data and the purchase price, ten-key "0" to "9", Enki "¥", hyphen key "(-)", arithmetic key “×”, “Δ”, “−”, “+”, “=”, etc. are included. Key S _4, when you enter the expected data and the purchase price is a race key to specify what number of race. Key S ₅ is a enter key for storing the input data in the above key S _3, S _4. For example,
Enter “1-5” in the winning streak (combination of 1st and 2nd) in the “Race 1” forecast, and enter the purchase price as “1000”
If you want to enter the circle ", sequentially," 1 "," S ₄ ",
"1", "(-)", "5", "$", "1",
"0", "0", "0" may be key operation as "S _5". Further, the side surface portion of the receiver main body 1, the power supply on to the circuit portion related only to the receiving operation, the main switch S ₆ to perform off is provided.

FIG. 2 is a block diagram showing a circuit configuration inside the receiver of the present embodiment.

In the figure, an antenna 3 is for receiving a radio signal transmitted from a predetermined transmitting station in a racetrack to notify a race result. The receiving circuit 4 is a circuit that detects a signal received from the antenna 3, further amplifies and demodulates the signal, and outputs the digital signal as serial digital data. The code format of the signal transmitted from the transmitting station is, for example, as shown in FIG. 3, and the receiving circuit 4 outputs the corresponding digital data. That is, as shown in FIG. 3 (a), the code format of the transmission signal is such that a preamble signal A consisting of a repetition of "1" and "0" is arranged first, followed by a batch signal B. ing. The preamble signal A is a signal for causing the receiver to recognize that data will be sent from now on and for input synchronization. Batch signal B, and the head of the synchronization code SC, Figure 3 ten code W corresponding to each of the first race result data as shown in (b) until the result data of the 10 race ₁ to W- _{It consists of 10} . Any of these codes W ₁ to _W-10, as shown in FIG. 3 (c), race results (e.g., in consecutive wins "1
Codeword X ₁ showing the -6 ", etc.), consist codeword X ₂ Metropolitan showing a dividend amount. And these 2
Each of the two codewords X ₁ and X ₂ is composed of an identification flag a, a data bit b, a BCH parity c, and an even parity d. Here, the identification flag a is
This flag is used to identify whether the next data bit b indicates the race result data or the payout amount data.
Indicates the payout amount data. BCH parity c
Is a bit for detecting and correcting an error occurring inside the code. The even parity d is a bit indicating whether the total number of bits representing “1” among the bits from the beginning to the end is odd or even. By checking the even parity d, it is possible to determine whether a bit is missing or added.

Next, returning to FIG. 2, the input synchronization circuit 5 is a circuit for synchronizing a signal output from the reception circuit 4 with an internal clock. The signal synchronized by the input synchronization circuit 5 is input to a BCH error correction circuit 6, a preamble detection circuit 7, and a synchronization code detection circuit 8. The BCH error correction circuit 6 uses the BCH parity c shown in FIG.
Is a circuit that performs error detection and correction of a received signal based on Specifically, if the number of erroneous bits among the bits from the identification flag a to the BCH parity c is less than a predetermined number, the erroneous bit data is corrected to regular data, and the number of erroneous bits is equal to or more than the predetermined number or the parity becomes even parity d. This circuit determines that there is an error only when there is an error. The preamble detection circuit 7 is a circuit that detects the preamble signal A shown in FIG. 3A from the received signal. The synchronization code detection circuit 8 is a circuit for detecting the synchronization code SC shown in FIG. 3A from the received signal. Also, SP
The conversion circuit 9 is a circuit that converts the serial digital signal, whose error has been corrected by the BCH error correction circuit 6, into parallel data. The reception timing control circuit 10 sends a command signal for writing received data to the RAM 11 to the RAM control unit 12 based on the detection signals from the preamble detection circuit 7 and the synchronization code detection circuit 8 and the like. When the data writing is completed, a completion signal is sent to the CPU 13, and furthermore, the operation of each of the circuits 5 to 9 on the receiving side is inhibited only during the period when the reception inhibition signal is output from the CPU 13.

The RAM 11 is a readable and writable memory for storing the parallel reception data sent from the SP conversion circuit 9, and has a configuration as shown in FIG. In the figure, a reception data register N is composed of a plurality of storage areas N ₀ , N ₁ , N ₂ ... For storing reception data corresponding to each race. The respective storage areas are a result data storage section D for storing race result data, a payout data storage section E for storing payout amount data, and an error-free flag F for storing whether or not these data are error-free. It is composed of The error-free flag F stores "1" when the BCH error correction circuit 6 shown in FIG. 2 determines that there is no error in the data based on the BCH parity c and the even parity d in FIG. 3C. When it is determined that there is an error, "0" is stored.

Next, returning to FIG. 2, the RAM control unit 12 gives data write and read command signals to the RAM 11 in accordance with commands from the CPU 13 and the reception timing control circuit 10, and also writes addresses of the RAM 11 at the time of writing and reading. The circuit to be specified. CPU13 the key S ₁ to S ₅ shown in FIG. 1
Based on a key input signal from the key input unit 14 including, for example, a completion signal output from the reception timing control circuit 10,
A central processing unit that executes various processes.For example, the race prediction data input from the key input unit 14 is stored in the RAM 15 or the race result data stored in the RAM 11 described above is fetched and the prediction data is stored. Then, processing such as changing the display mode of the display unit 2 based on the determination result is performed.

The RAM 15 stores a key input section based on a command from the CPU 13 described above.
This is a readable and writable memory for storing expected data and the like input from 14 and has a configuration as shown in FIG. In the figure, a prediction data register M has a plurality of storage areas M ₀ , M ₁ , M ₂ for sequentially storing prediction data (not limited to one), purchase price data and the like of each race from the first race. , Etc., and the respective storage areas are a prediction data storage section G for storing prediction data, a purchase price storage section H for storing purchase price data, and a case where the prediction is successful (the prediction data is A refund amount storage unit I for storing refund amount data (in the case of coincidence) and a hit flag J for storing "1" when a prediction is hit.

The expected number registers R _{1 to} R ₁₀ are the first
Scales from the race to the tenth race, a register for storing the predicted the number per each race (the number of expected data), enter key S ₅ with respect to race specified by race key S ₄ when entering the expected data The number is set according to the number of times the operation is performed. The race designation register C is a register for designating one of the first to tenth races in the processing of the CPU 13 described later. The display pointer P is used to designate data to be displayed on the display unit 2 from a plurality of data stored in the storage areas M ₀ , M ₁ , M ₂ ,. It is a pointer. The timer register S is a register used as a 10-second timer, for example, and receives the above-mentioned reception inhibition signal (see FIG. 2) when a key is operated.
It is for outputting for only 10 seconds. The reception enable / disable flag L is a register that stores "1" when a key operation is performed and stores "0" when the timer register S times out. A reception inhibition signal is output, and the reception operation is inhibited. The working register K is a register used for various processing and for temporarily storing data.

Next, returning to FIG. 2, the arithmetic circuit 16 calculates, based on the order from the CPU 13, the reimbursement amount in the race for which the prediction was successful based on the purchase amount and the payout amount, or calculates the sum of the purchase amount in all the races. This is a circuit for calculating the total refund amount. The display buffer 17 is a memory for temporarily storing pattern data for display given from the CPU 13, and the display driver 18 stores the data stored in the display buffer 17 in the display unit 2 (shown in FIG. 1). The same circuit is displayed. The oscillator 19 is a circuit that outputs a reference clock signal having a constant period. The timing signal output circuit 20 divides the frequency of the reference clock signal to a predetermined frequency, and
This is a circuit that outputs a timing signal for controlling each circuit including the CPU 10 and the CPU 13 in time series.

Next, the main processing operations of this embodiment will be described with reference to FIGS.
This will be described with reference to FIG. FIG. 6 is a flowchart showing the overall processing operation of this embodiment, and FIG.
Flowchart illustrating reception data acquisition processing in figure (step a ₁₃₎ Specifically, Figure 8 and Figure 9 is confirmed at the time of operation of the read key S ₁ of the key processing in FIG. 6 (step a ₅₎ flowchart illustrating the respective process when key S ₂ operation Specifically, FIG. 10 RA for the expected data storage
FIG. 11 is a diagram showing an example when predicted data of each race is stored in M15, FIG. 11 is a diagram showing an example when received data is stored in the RAM 11 for storing received data, and FIG. 12 is a diagram for storing predicted data. FIG. 13 is a diagram showing an example in which refund amount data for each race is stored in the RAM 15 of FIG.
₁ is a diagram showing the switching of the display state of the display unit 2 based on the operation of the confirmation key S _2.

First, in FIG. 6, a halt state is normally set (step a ₁ ). If a key input signal is sent due to some key operation, a key interrupt process is performed (step a ₂ ). Subsequently, "1" is set in the receiving availability flag L of RAM 15 (step a _3). As a result, the CPU 13 shown in FIG.
A reception prohibition signal is sent to 0, and the operation of each of the circuits 5 to 9 on the reception side is prohibited. Thereafter, clears the timer register S (Step a _4), performs a key process corresponding to the operation key (Step a _5). This key process, depending on which key among the key S ₁ to S ₅ shown in FIG. 1 is operated, and performs a process corresponding to each. For example, as described above, when a series of operations of the race key S ₄ , the data input key S ₃ , and the enter key S ₅ are performed, the predicted data for each race (for example, “1-3 )) And the purchase price data (for example, “1000 yen”) are stored in the prediction data register M of the RAM 15 in order from the first race as shown in FIG. The example in FIG. 10 shows four races for Race 1, Race 2, Race 3, and Race 4, respectively.
The figure shows a case where one, one, three, and one predictions are made. In this case, the expected number registers R _{1 to} R ₁₀ store the expected number of data for each race. Also,
The process when the read key S ₁ and confirmation key S ₂ is operated will be described later based on FIG. 8 and FIG. 9.

On the other hand, in the halt state (step a ₁ ),
For example, if a clock signal is output every second, a timer interrupt process is performed (step a ₆ ). Subsequently, whether "1" to the receiving availability flag L has been stored, i.e., it determines whether the received inhibit signal by the key operation has been performed is output (step a _7). If L
If = 1, the timer register S is incremented by one (step a ₈ ), and it is determined whether or not the content has reached 10 seconds (step a ₉ ). The contents of the timer register S, since it is cleared in step a ₄ when the key interrupt, counting from zero starts here, S =
The count continues until 10 seconds. When it becomes S = 10 seconds, by setting "0" to the receiving availability flag L, it cancels the received inhibit signal (Step a _10). Thus, no matter which key is operated, the receiving operation is prohibited for 10 seconds after the operation. For example, the input of the above-described prediction data is performed by sequentially operating a plurality of keys, but in order to prevent reception interruption between each key operation, the next key must be operated within 10 seconds. I just need.

When 10 seconds elapse after the key operation, the reception prohibition signal is released as described above, and reception becomes possible. The received data is stored in the reception data register N of the reception data storage RAM 11 in order from the first race, as shown in FIG. 11, for example. In FIG.
₀ , N ₁ , N ₂ , and N ₃ store received data relating to the first, second, third, and fourth races, respectively. The result data storage unit D of each storage area stores race result data (for example, “ 1-6 "), the payout amount data per 100 yen (for example," 750 "or the like) is stored in the payout data storage unit E, and the presence / absence data of the error is stored in the error-free flag F (if there is no error," 1 ", and" 0 "if an error occurs).
When the operation of storing the received data in the RAM 11 is completed in this way, a completion signal is sent from the reception timing control circuit 10 to the CPU 13 as shown in FIG. Therefore, in the halt state (step a ₁ ), when this completion signal is sent, reception completion interrupt processing is performed (step a ₁₁ ). Subsequently, “0” is set in the reception possibility flag L.
There whether it is stored, i.e. to determine whether the received inhibit signal by older than 10 seconds from the key operation is released (step a _12), if if L = 0, receives the next step Turning to the data capture process (step a _13). This reception data capturing process will be specifically described below with reference to FIG.

In FIG. 7, first, the display pointer P of the RAM 15 is set to "0", so that the expected data register M
Specifies the data contained in the first storage area M ₀ (step b _1), followed by setting to "1" to the race designation register C, and specifies the first race (step b _2). Then, among the expected number registers R _{1 to} R ₁₀ ,
A register corresponding to the race designated by C (for example, if C = 1, a register R ₁ corresponding to the first race)
It is determined whether or not there is data in
₃ ). If not contain data, incremented by one race designation register C (Step b _4), or the contents thereof whether 10 or less, that is, specify one of the race from the first race until the 10 race to determine whether (step b _5). If C> 10, the subsequent processing is terminated, while if C ≦ 10, the above step b ₃
Return to That is, the above step b ₃ ~b _5, first
It is checked whether any of the races from the race to the tenth race has predicted data set in advance.

In step b _3, if there is data in the expected number register corresponding to the race specified in C, from RAM11 (see FIG. 11) for receiving data storage, the C
Receiving data corresponding to the specified race in (result data, award data, and whether data of the error) capturing (Step b _6). Then, among the captured received data, to determine whether data stored in the error-free flag F is "1" or not, i.e. there is no error in the result data and the payout data (step b _7).

If F = 1, among the predicted data corresponding to the race specified by C, the predicted data specified by the display pointer P is the result data of the fetched received data. Is determined (step b ₃ ). If they match, a refund amount is calculated based on the purchase amount data and the dividend amount data (step b ₉ ), and then the calculated refund amount data is designated by the above P. while set to refund the storage unit I of the storage area, and sets "1" to the neutral flag J corresponding thereto (step b _10).
If they do not match, these processes are not performed.

On the other hand, if F = 0 in step b _7, that is, when the data has an error sets a specific code in the refund storage unit I of the storage area specified by P (step b _11).

Thereafter, by incrementing the display pointer P by one, the next expected data in the expected data register M is designated (step b ₁₂ ), and it is determined whether or not the data is data of the next race (step b). ₁₃ ). This determination is made by whether or not exceeding the total estimated number of values of the display pointer P is stored until the expected number register specified in the race designation register C from the expected number register R _1. Also if the data of the next race, repeats the processing of step b ₇ ~b ₁₁ for the data, if the data of the next race, by specifying the next race returns to step b ₄ From above is repeated. That is, for data of all races, each race, repeats the processes of steps b ₇ ~b _11.

According to the reception data fetching process described above, for example, C
There Specifies first race, if P designates the storage area M ₂ of the expected data register M, is expected data "1-6" in the storage area M ₂ shown in FIG. 10, FIG. 11 Since the result matches the result data “1-6” in the storage area N ₀ of the first race shown in (b), the prediction was correct. In this case, the processing in steps b ₉ and b ₁₀ as shown in FIG. 12, "750 refund storage unit I of the storage area M ₂
“0” (= 1000 × 750 ÷ 100) is stored, and “1” is stored in the hit flag J. This is, C designates the third race, when even the P specifies a storage region M ₆ of the expected data register M, it can be said as well. C designates the fourth race, and P designates the storage area M of the prediction data register M.
If you specify a _8, since "0" to the fourth error-free storage area N ₃ race flag F shown in FIG. 11 is stored, in step b ₁₁ in this case, the 12 as shown in FIG, refund storage unit I of the storage area M ₈
Is stored with the specific code "FFFFFF". The specific code is not limited to the example shown in FIG. 12, and may be any data that is not used as ordinary numerical data or data that can clearly identify an error.

Then, among the key processing shown in FIG. 6 (step a _5), the processing in the case of operating the read key S _1, on the basis of FIG. 8, specifically described below.

In FIG. 8, first, the race designation register C is set to 1
The next race is designated by counting up by one (step c ₁ ). Then, it is determined whether or not the content of C is 10 or less, that is, whether or not any of the races from the first race to the tenth race is designated (step c).
₂ ). Here, if C ≦ 10, the expected number register R _1-
Of R _10, determines whether the data in the register corresponding to the race, which is specified in the above C is on (step c _3). If it contains data, the flow returns to the step c _1. That is, the above step c ₁ to c _3,
It is checked whether or not there is a race for which prediction data is set in advance among the races from the first race to the tenth race.

In step c _3, if there is data in the expected number register corresponding to the race specified in C is expected among the storage areas of the data register M, the first prediction data corresponding to the race specified above C Is set to the display pointer P at the address of the storage area containing the character (step c ₄ ). Subsequently, the specific code (“FFFF” in FIG. 12) is stored in the refund amount storage unit I of the storage area designated by P.
FF ”) is stored (step c).
_5), if the specific code is stored, performs specific code display processing for informing the error data (step c _6). On the other hand, in step c _5, unless the specific code is stored in the refund storage unit I, whether now, "1" to the center flag J storage area specified by P is set discriminated (Step c ₇ )
If it is set, a flushing display process is performed to notify that the prediction was successful (step c ₈ ). Also,
In step c _7, if "1" is not set to the hit flag J, a still lit display in place of the flushing indication (step c _9).

After performing any one of the display processes in steps c ₆ , c ₈ , and c _{9 on} the data designated by the display pointer P, by incrementing P by one, the expected data register M The data of the next storage area is designated (step c ₁₀ ). Subsequently, it is determined whether or not the designated data is the data of the next race (step c ₁₁ ). If it is not the data of the next race, the process returns to the step c ₅ . The subsequent processing ends. That is, the process of step c ₄ to c _11, all the data for one race worth, is displayed collectively in any display mode, respectively.

On the other hand, if C> 10 in step c _2, the sum of the refund amount and purchase amount in all races, respectively (step c _12), and displays the calculation result on the display unit 2 (step c _13). After that, "0" is set in the race designation register C, and the process is terminated.

In the key processing by more read key S ₁ of the operation, each time the read key S ₁ is being operated, as in the FIG. 13 display example a to e, the expected data and the purchase amount data for each race They are displayed one by one. At this time, if the specific code is not stored in the refund amount storage unit I and the hit flag J is not set to “1”,
Normal still lit display is performed (see step c ₉₎
However, in other cases, the display mode changes as follows. That is, when the specific code is stored in the refund amount storage unit I, the specific display is performed such that the display data is surrounded by a frame as shown in a display example d (steps c ₅ and c _6). reference). As a result, since the race result data corresponding to the displayed data has an error and it is impossible to determine whether or not the prediction is actually correct, it is better to check the display data again. This can be notified to the user.
Also, if "1" is set in the center flag J, for example, as shown in display example a and c, only the data being hit is flushed displayed (indicated by a broken line) (step c ₇ , see c _8).

Furthermore, even though for example the expected data is not only stored to the fourth race, when the read key S ₁ is being operated five times is switched to the display example e of the total amount from the display example d of the fourth race (see step c _12, c _13). In this display example e, the total purchase amount is 12000 yen (“OUT-1200
0 ") and the total refund amount is ¥ 16000 (" IN-160
00 ") and have a profit of 4000 yen (" +40
00 "). When further read key S ₁ is being operated in the display state, again, the display returns to Example a first race (see step c _14, c _1, etc.).

Then, in the display state by the operation of the read key S ₁ described above, the process in the case of operating the confirmation key S _2, on the basis of FIG. 9 will be specifically described below.

In FIG. 9, first, among the storage areas of the prediction data register M, the address of the storage area containing the first prediction data corresponding to the race designated by the race designation flag C is set to the display pointer P. (Step d ₁ ). Subsequently, a specific code (“FFFFF” in FIG. 12) is stored in the refund amount storage unit I of the storage area designated by P.
F ”) is stored (step d ₂ ), and if there is a specific code, it is a specification for notifying that it is not known whether the prediction of the race was successful and the amount of the refund is not known. A code is displayed (step d ₃ ).

On the other hand, in step d _2, if specific code to refund the storage unit I is not stored, a "1" to the center flag J for the specified Tare storage area P to determine whether it is set (step d ₄ ), if set, flashing display of the race result and the payout amount, and the purchase amount and the refund amount (step d ₅ ).

Further, in step d _4, if "1" is not set to the hit flag J, the display pointer P 1
By counting up, the data of the next storage area is designated (step d ₆ ), and it is determined whether or not the data is the data of the next race (step d ₇ ). if,
When it is not data of the next race, returns to the step d _2,
The same processing as above is repeated. On the other hand, in the case of the data of the next race, the race result and the payout amount, and the purchase amount and the refund amount (whichever Is also lit statically (step d ₈ ).

According to the key processing by the above-described operation of the confirmation key S _2,
When controlling the confirmation key S ₂ in batch display state for each race (display example a~d reference in FIG. 13) by the read key S ₁ described above, if the specific above batch display similar to the display example d when the code display of "??????" is displayed, for example, as the display example i (see step d _2, d _3). This makes it possible to clearly indicate that reliable information has not been obtained as to whether or not the prediction of the race was correct and the amount of the refund. Further, when the above-mentioned batch display includes a flashing display indicating a predictive hit as in display examples a and c, only the data relating to the hit race result is flashing displayed as in display examples f and h. You. For example, in display example f, the race result is “1-6”, the dividend amount per 100 yen is 750 yen (“750”), and the purchase amount for this prediction is 1000 yen (“OUT -1000 ") for which the refund amount is
7500 yen ("IN-7500"). When the batch display does not include the flashing display or the specific code display as in the display example b, the result of the race (“2-8”) and the payout amount (“12
00 "), the purchase amount (" OUT-0 ") and the refund amount (" IN-0 ") are steadily lit.

As described above, according to the present embodiment, it is possible to immediately know the result of the race by radio, and by flashing the display that the user's prediction was successful and the amount refunded by the prediction. You can easily find out. In addition, when the probability of an error in the received data is high, the specific code is displayed, so that the reliability of the displayed content is high.

The receiver of the above embodiment is used by lending from a racetrack, and a transmission signal from a racetrack is unconditionally received by all receivers. By contract with a pager company, a message regarding the race result may be individually sent to the outside of the racetrack. To achieve this, between the BCH error correction circuit 6 and the SP conversion circuit 9 in the circuit configuration shown in FIG. 2, an ID-ROM 21 and an address coincidence detection circuit 22 are connected as shown in FIG. And the format of the transmission signal may be changed as shown in FIG.

That is, in FIG. 15, the batch signal B includes a synchronization code SC and a plurality of codewords Y ₁ , Y ₂ , Y _2, ..., And each of the code words Y ₁ , Y ₂ , Y _3. Is followed by an identification flag z, followed by an address code and message data. The identification flag z is set to “0” when the next data following it is an address code, and is set to “1” when it is message data. The address code is a code corresponding to its own calling number, and the message data includes race result data and payout data as in the configuration of FIG. 3 (c). In this example, 2
One codeword forms data for one race.

In FIG. 14, the ID-ROM 21 is a read-only memory that stores its own address in advance. The address match detection circuit 22 detects whether or not the address code (see FIG. 15) included in the received data matches the own address stored in the ID-ROM 21. A match detection signal is sent to the conversion circuit 9 and S
This is a circuit that enables the operation of the -P conversion circuit 9. With such a circuit configuration, it is possible to capture only the message data transmitted to itself and display various data in the same manner as in the above-described embodiment.

Although each of the above-described embodiments has been described by taking the case of horse racing as an example, it is needless to say that the present invention can be applied to other races such as a bicycle race, a boat race, and an auto race.

In addition, the display mode when the prediction was correct was set to the flashing display, and the display mode when there was erroneous data was set to the frame display, but the display mode was not limited to this example. Any display mode can be used as long as it can surely notify that there is error data.

[Effect of the invention]

As described above, according to the present invention, if the prediction data is input before the start of the race, the result of the race is transmitted wirelessly after the end of the race (automatically without any key operation). 2), it is possible to know the result of the race, and to easily know from the display that the race prediction was successful.

[Brief description of the drawings]

FIG. 1 is an external plan view showing a receiver according to one embodiment of the present invention, FIG. 2 is a block diagram showing a circuit configuration inside the receiver of this embodiment, and FIG. 3 is a transmission adopted in this embodiment. FIG. 4 is a diagram showing a signal format, FIG. 4 is a schematic configuration diagram showing main contents of the RAM 11 in FIG. 2, FIG. 5 is a schematic configuration diagram showing main contents of the RAM 15 in FIG. 2, and FIG. FIG. 7 is a flowchart showing the overall processing operation of the example, FIG. 7 is a flowchart specifically showing the reception data fetching process (step a ₁₃ ) in FIG. 6, and FIGS. 8 and 9 are keys in FIG. (step a ₅₎ out of, confirmed when reading the key S ₁ operation key S ₂
FIG. 10 is a flowchart specifically showing each process at the time of the operation, FIG. 10 is a diagram showing an example when predicted data of each race is stored in the RAM 15, FIG. 11 is a case where received data is stored in the RAM 11 shows an example, FIG. 12 shows an example of a case where the amount of refund data for each race in RAM15 is stored, the display portion 2 FIG. 13 is based on the read key S ₁ and the operation of the confirmation key S ₂ FIG. 14 is a diagram showing switching of display states, FIG. 14 is a block diagram showing a part of a circuit configuration inside a receiver according to another embodiment of the present invention, and FIG. 15 is a transmission signal adopted in the above other embodiment. It is a figure showing a format. 2 display unit 4 reception circuit 5 input synchronization circuit
6 BCH error correction circuit 7 Preamble detection circuit 8 Sync code detection circuit 9 SP conversion circuit 10 Reception timing control circuit 11 RAM for receiving data storage 12 RAM control unit, 13 CPU, 15 RAM for storing predicted data, 16 arithmetic circuit, 17 display buffer, 18 display driver, 21 ID-ROM, 22 Address match detection circuit, N ... Reception data register, D ...
... Result data storage unit, E ... Payout data storage unit, F ...
No error flag, M: expected data register, G: expected data storage unit, H: purchased amount storage unit, I: refund amount storage unit, J: hit flag, R _{1 to} R _10: expected number register, C ...... race designation register, P ...... display pointer, S ...... timer register, L ...... reception possibility flag, S ₁ ...... read key, S ₂ ...... confirmation key, S ₃ ......
Data input key, S ₄ … race key, S ₅ … enter key.

Claims (5)

(57) [Scope of request for utility model registration] An input means for inputting a plurality of prediction data for predicting a race result in advance, a storage means for storing a plurality of prediction data input by the input means, and a plurality of predictions stored in the storage means Display means for simultaneously displaying data; receiving means for receiving result data indicating actual race results; immediately after reception by the receiving means, the received result data and the result data are stored in the storage means. A coincidence determining means for determining a match with the expected data; and, among a plurality of pieces of expected data displayed by the display means, the expected data for which the match with the result data is determined by the match determining means are used as other expected data. And a display control means for displaying the display in a different manner. 2. The receiving means has an error detecting means for detecting an error in the received data. The receiving means fetches the received data only when the error detecting means determines that there is no error in the received data. 2. The receiver according to claim 1, wherein the information is displayed on the receiver. 3. The receiving means has error detecting means for detecting an error in the received data. When data having a high error probability is detected by the error detecting means, the error probability of the data is high. The receiver according to claim 1, wherein is displayed on the display means. 4. The apparatus according to claim 1, wherein said receiving means outputs a reception completion signal every time a series of result data has been received, and operates said coincidence determination means and said display control means. A receiver according to any one of the preceding claims. 5. The reception according to claim 1, wherein when a key input is made by said input means, a process based on said key input is prioritized over other processes. Machine.