JPH0292551U - - Google Patents
Info
- Publication number
- JPH0292551U JPH0292551U JP17126788U JP17126788U JPH0292551U JP H0292551 U JPH0292551 U JP H0292551U JP 17126788 U JP17126788 U JP 17126788U JP 17126788 U JP17126788 U JP 17126788U JP H0292551 U JPH0292551 U JP H0292551U
- Authority
- JP
- Japan
- Prior art keywords
- data
- result
- notification
- receiving
- ram
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 9
- 238000013500 data storage Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
Description
第１図は本考案の一実施例に係る受信機を示す
外観平面図、第２図は本実施例の受信機内部の回
路構成を示すブロツク図、第３図は本実施例で採
用した送信信号フオーマツトを示す図、第４図は
第２図中のＲＡＭ１１の主要内容を示す模式構成
図、第５図は第２図中のＲＡＭ１５の主要内容を
示す模式構成図、第６図は本実施例の全体的な処
理動作を示すフローチヤート、第７図は第６図中
の受信データ取り込み処理（ステツプａ１３）を
具体的に示すフローチヤート、第８図及び第９図
は第６図中のキー処理（ステツプａ５）のうち、
読み出しキーＳ１の操作時と確認キーＳ２の操作
時のそれぞれの処理を具体的に示すフローチヤー
ト、第１０図はＲＡＭ１５に各レースの予測デー
タが記憶された場合の一例を示す図、第１１図は
ＲＡＭ１１に受信データが記憶された場合の一例
を示す図、第１２図はＲＡＭ１５に各レース毎の
払い戻し金額データが記憶された場合の一例を示
す図、第１３図は読み出しキーＳ１と確認キーＳ
２の操作に基づく表示部２の表示状態の切り換わ
りを示す図、第１４図は本考案の他の実施例に係
る受信機内部の回路構成の一部を示すブロツク図
、第１５図は上記他の実施例で採用した送信信号
フオーマツトを示す図である。
２……表示部、４……受信回路、５……入力同
期回路、６……ＢＣＨ誤り訂正回路、７……プリ
アンブル検出回路、８……同期コード検出回路、
９……Ｓ−Ｐ変換回路、１０……受信タイミング
制御回路、１１……受信データ記憶用のＲＡＭ、
１２……ＲＡＭ制御部、１３……ＣＰＵ、１５…
…予想データ記憶用のＲＡＭ、１６……演算回路
、２１……スピーカ駆動回路、２２……スピーカ
、２３……ＩＤ−ＲＯＭ、２４……アドレス一致
検出回路、Ｎ……受信データレジスタ、Ｄ……結
果データ記憶部、Ｅ……配当データ記憶部、Ｆ…
…誤りなしフラグ、Ｍ……予想データレジスタ、
Ｇ……予想データ記憶部、Ｈ……購入金額記憶部
、Ｉ……払い戻し金額記憶部、Ｊ……報音済フラ
グ、Ｋ……的中フラグ、Ｒ１〜Ｒ１０……予想本
数レジスタ、Ｃ……レース指定レジスタ、Ｐ……
表示ポインタ、Ｓ……タイマレジスタ、Ｌ……受
信可否フラグ、Ｓ１……読み出しキー、Ｓ２……
確認キー、Ｓ３……データ入力キー、Ｓ４……レ
ースキー、Ｓ５……エンターキー。
Fig. 1 is an external plan view showing a receiver according to an embodiment of the present invention, Fig. 2 is a block diagram showing the internal circuit configuration of the receiver of this embodiment, and Fig. 3 is a transmitter employed in this embodiment. 4 is a schematic configuration diagram showing the main contents of RAM 11 in FIG. 2, FIG. 5 is a schematic configuration diagram showing the main contents of RAM 15 in FIG. 2, and FIG. 6 is a diagram showing the main contents of RAM 15 in FIG. 2. A flowchart showing the overall processing operation of the example, FIG. 7 is a flowchart specifically showing the received data importing process (step a13 ) in FIG. 6, and FIGS. 8 and 9 are in FIG. Of the key processing (step a5 ),
10 is a flowchart specifically showing the respective processes when operating the read key S1 and when operating the confirm key S2 . FIG. FIG. 11 is a diagram showing an example of the case where received data is stored in the RAM 11, FIG. 12 is a diagram showing an example of the case where the payout amount data for each race is stored in the RAM 15, and FIG. 13 is a diagram showing an example of the case where the received data is stored in the RAM 15. and confirmation key S
FIG . 14 is a block diagram showing a part of the circuit configuration inside the receiver according to another embodiment of the present invention, and FIG. FIG. 7 is a diagram showing a transmission signal format adopted in another embodiment. 2... Display unit, 4... Receiving circuit, 5... Input synchronization circuit, 6... BCH error correction circuit, 7... Preamble detection circuit, 8... Synchronization code detection circuit,
9... S-P conversion circuit, 10... Reception timing control circuit, 11... RAM for storing received data,
12...RAM control unit, 13...CPU, 15...
...RAM for storing expected data, 16... Arithmetic circuit, 21... Speaker drive circuit, 22... Speaker, 23... ID-ROM, 24... Address match detection circuit, N... Reception data register, D... ...Result data storage section, E...Payout data storage section, F...
...No error flag, M...Expected data register,
G: Expected data storage unit, H: Purchase amount storage unit, I: Refund amount storage unit, J: Reported flag, K: Hit flag, R1 to R10 : Expected number of books register, C...Race designation register, P...
Display pointer, S...Timer register, L...Reception availability flag, S1 ...Read key, S2 ...
Confirmation key, S3 ...Data input key, S4 ...Race key, S5 ...Enter key.
Claims (1)
入力する入力手段と、 該入力手段で入力された複数の予想データを記
憶する記憶手段と、 実際のレース結果を示す結果データを受信する
受信手段と、 該受信手段で受信された結果データと前記記憶
手段に記憶されている予想データとの一致を判別
する一致判別手段と、 該一致判別手段により一致が判別された時に、
予想が的中したことを報知する報知手段とを備え
たことを特徴とする受信機。 ２ 前記報知手段は音で報知することを特徴とす
る請求項(1)記載の受信機。 ３ 前記報知手段による報音は最初の１回のみで
あることを特徴とする請求項２記載の受信機。[Scope of Claim for Utility Model Registration] 1. An input means for inputting a plurality of prediction data predicting the result of a race, a storage means for storing a plurality of prediction data inputted by the input means, and an indication of the actual race result. a receiving means for receiving result data; a match determining means for determining whether the result data received by the receiving means matches the expected data stored in the storage means; and a match is determined by the matching determining means. Sometimes,
1. A receiver comprising a notification means for notifying that the prediction is correct. 2. The receiver according to claim 1, wherein the notification means provides notification by sound. 3. The receiver according to claim 2, wherein the notification means makes a sound only once at the beginning.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988171267U JP2525256Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
| US07/456,852 US5212636A (en) | 1988-12-28 | 1989-12-26 | Radio receiver capable of confirming gambling results |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988171267U JP2525256Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0292551U true JPH0292551U (en) | 1990-07-23 |
| JP2525256Y2 JP2525256Y2 (en) | 1997-02-05 |
Family
ID=31462950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988171267U Expired - Lifetime JP2525256Y2 (en) | 1988-12-28 | 1988-12-28 | Receiving machine |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2525256Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60262272A (en) * | 1984-06-08 | 1985-12-25 | Omron Tateisi Electronics Co | Portable share rate data receiver |
| JPH07120378A (en) * | 1993-10-21 | 1995-05-12 | Toyota Motor Corp | Testing method for adhesion property of film |
-
1988
- 1988-12-28 JP JP1988171267U patent/JP2525256Y2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60262272A (en) * | 1984-06-08 | 1985-12-25 | Omron Tateisi Electronics Co | Portable share rate data receiver |
| JPH07120378A (en) * | 1993-10-21 | 1995-05-12 | Toyota Motor Corp | Testing method for adhesion property of film |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2525256Y2 (en) | 1997-02-05 |
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