JPH0292230U

JPH0292230U -

Info

Publication number: JPH0292230U
Application number: JP36289U
Authority: JP
Priority date: 1989-01-06
Filing date: 1989-01-06
Publication date: 1990-07-23

Description

[Brief explanation of drawings]

第１図および第２図が本考案に関し、第１図は
本考案によるＣＭＯＳシユミツトトリガ回路の実
施例の回路図、動作波形図およびトランジスタの
動作状態図表、第２図は本考案の異なる実施例の
回路図およびトランジスタの動作状態図表である
。第３図以降は従来技術に関し、第３図は従来の
シユミツトトリガ回路の回路図、第４図はその動
作波形図である。図において、１ｐ，１ｎ：第１の入力トランジスタ、２ｐ，
２ｎ：第２の入力トランジスタ、３ｐ，３ｎ：帰
還トランジスタ、４：インバータ、５：ノアゲー
ト、６：アンドゲート、５ａ，６ａ，７：インバ
ータ、１０ｐ：一方の回路部、１０ｎ：他方の回
路部、ａ〜ｄ：シユミツトトリガ回路の動作状態
を区分する期間、Ｅ：電源点の一方、ｈ：高い方
の動作しきい値、ｌ：低い方の動作しきい値、Ｓ
ｉ：入力信号、Ｓｏ：出力信号、Ｖ：電源点の他
方、である。 1 and 2 relate to the present invention; FIG. 1 is a circuit diagram, operating waveform diagram, and transistor operating state diagram of an embodiment of a CMOS shot trigger circuit according to the present invention; FIG. 2 is a diagram of a different embodiment of the present invention; 2 is a circuit diagram and a chart of operating states of transistors. FIG. 3 and subsequent figures relate to the prior art. FIG. 3 is a circuit diagram of a conventional Schmitt trigger circuit, and FIG. 4 is an operating waveform diagram thereof. In the figure, 1p, 1n: first input transistor, 2p,
2n: second input transistor, 3p, 3n: feedback transistor, 4: inverter, 5: NOR gate, 6: AND gate, 5a, 6a, 7: inverter, 10p: one circuit section, 10n: other circuit section, a to d: period for classifying the operating state of the Schmitt trigger circuit, E: one of the power supply points, h: higher operating threshold, l: lower operating threshold, S
i: input signal, So: output signal, V: other power point.

Claims

[Scope of utility model registration request]

One and the other channel-shaped circuit sections each containing a first and second input transistor and a feedback transistor are connected in series between a pair of power supply points, and an output signal is taken out from the interconnection point of both circuit sections. , the first input transistor and the feedback transistor are connected in series in one circuit section and in parallel in the other circuit section, and the second input transistor is connected to the series circuit including the first input transistor and the feedback transistor. are connected in parallel and in series for parallel circuits, and the input transistor and the feedback transistor are connected to a common gate to provide complementary signals of the input signal and the output signal, respectively, and the inputs of the first and second input transistors are connected to each other in series. C with different operating thresholds for signal values
MOS Schmitt trigger circuit.