JPH02912Y2 - - Google Patents

Info

Publication number
JPH02912Y2
JPH02912Y2 JP4635383U JP4635383U JPH02912Y2 JP H02912 Y2 JPH02912 Y2 JP H02912Y2 JP 4635383 U JP4635383 U JP 4635383U JP 4635383 U JP4635383 U JP 4635383U JP H02912 Y2 JPH02912 Y2 JP H02912Y2
Authority
JP
Japan
Prior art keywords
transistor
base drive
chip
emitter
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP4635383U
Other languages
English (en)
Japanese (ja)
Other versions
JPS59152746U (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1983046353U priority Critical patent/JPS59152746U/ja
Publication of JPS59152746U publication Critical patent/JPS59152746U/ja
Application granted granted Critical
Publication of JPH02912Y2 publication Critical patent/JPH02912Y2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Bipolar Transistors (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
JP1983046353U 1983-03-30 1983-03-30 パワ−トランジスタの素子構造 Granted JPS59152746U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983046353U JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Publications (2)

Publication Number Publication Date
JPS59152746U JPS59152746U (ja) 1984-10-13
JPH02912Y2 true JPH02912Y2 (enExample) 1990-01-10

Family

ID=30176908

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983046353U Granted JPS59152746U (ja) 1983-03-30 1983-03-30 パワ−トランジスタの素子構造

Country Status (1)

Country Link
JP (1) JPS59152746U (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011254013A (ja) * 2010-06-03 2011-12-15 Panasonic Electric Works Co Ltd 半導体装置およびこれを用いた半導体リレー

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011254013A (ja) * 2010-06-03 2011-12-15 Panasonic Electric Works Co Ltd 半導体装置およびこれを用いた半導体リレー
WO2011151682A3 (ja) * 2010-06-03 2012-01-26 パナソニック電工株式会社 半導体装置およびこれを用いた半導体リレー

Also Published As

Publication number Publication date
JPS59152746U (ja) 1984-10-13

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