JPH0290223A - A/d conversion unit for sequencer - Google Patents

Abstract

PURPOSE:To eliminate the need for the generation of an input signal which can not be used for sequence control by controlling a switch element by a CPU and applying an A/D flag for controlling data access to a sequencer A/D conversion unit to a sequencer CPU unit based on a switching output. CONSTITUTION:In an A/D conversion unit I, a CPU 5 controls a relay RY through a latch circuit 13 and a photocoupler 14 and turns on a relay contact (r) in the case of turning on an A/D flag, and at the time of turning off the A/D flag, turns off the relay contact (r). When the relay contact (r) is turned on, current for emitting a light emitting diode LED1 in a photocoupler 15 on the input unit II side flows, a phototransistor PT1 is turned on and an 'L' signal is inputted to an input unit internal circuit 16 as an X0 input and fetched into the sequencer CPU unit as an A/D flag. Consequently, it is unnecessary to generate an input signal which can not be used for sequence control.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion unit for a sequencer.

[Prior Art] Fig. 4 shows a circuit of a conventional example, which the present inventor has already filed as Japanese Patent Application No. 63-94037. In this conventional example, the A/D conversion process shown in the flowchart of Fig. 5 is conduct.

In this conventional example, the CPU 5 controls each part and performs signal processing according to a program stored in the program memory 6. After the power is turned on, the shared memory 4 is cleared and the A/D The flag is turned off, and then the mode is determined by the CPU 5. This mode includes A/D conversion processing for each channel! @(A/D conversion characteristics, A
/D conversion value data average processing specification) SET
A for each channel set to mode and SET mode
A/D converter 1 cyclically A/D converts each analog input based on the A/D conversion processing format.
There is a RUN mode in which converted data is stored in the shared memory 4 via the latch circuit 2 and data bus 3.

If the mode determination is SET mode, the A/D flag is turned off and the above-mentioned SET mode processing is performed. Also, in RUN mode, the A/D flag is determined from on to off.
If it is off, each analog input is A/D converted once for each channel by the A/D converter 1, and this A/D converted data is stored in the shared memory 4 via the latch circuit 2 and data bus 3. , if it is on, it is based on the A/D conversion processing form for each input channel set in SET mode <:
Performs A/D conversion processing.

Here, the operation of the A/D conversion unit is controlled by the sequencer CPU.
Unit control is independent, so the A/D conversion unit is ready for A/D conversion data access from the sequencer CPU unit (access to shared memory 4 from the sequencer CPU unit). It is necessary to make it clear to the sequencer CPU unit whether the This signal is "rA/D flag" in the flowchart of FIG.

In other words, the conventional A/D conversion unit has its own input signal for the sequencer CPU unit, and one of these input signals By loading it into the CPU for the sequencer and executing the sequence program as shown in Figure 6, the CPU for the sequencer
Valid A/D conversion data was given to the sequencer CPU unit for A/D conversion data access from the U unit. The rREADJ command shown in FIG. 6 is a sequence control application command that reads the shared memory 4 on the A/D conversion unit from the sequencer CPU unit, and is an "XO" command.
indicates the READ instruction execution condition.

In addition, 7 in FIG. 4 indicates the C8 signal of the latch circuit 2, the C8 signal of the shared memory 4, and the C8 signal of the program memory 6 based on the address data input from the CPU 5 through the address bus 8.
Address decoder for creating 8 signals and CK times signal of buffer circuit 8, 9 is C for sequencer
This is an address decoder for creating the ε1 signal of the shared memory 4, which is the OE multiplied signal of the buffer circuit n8, based on the address data given from the PU unit through the address bus 10. The buffer circuit 12 is a buffer circuit for providing the above-mentioned "A/D flag" to the sequencer CPU unit via the data bus 11. shared memory 4
Reading and writing of data to and from the RD double signal of the CPU 5 and the WT double signal from the CPU unit for the sequencer
This is done by the PURD signal and the CPUWT signal, respectively.

[Problems to be Solved by the Invention] By the way, since the minimum data unit for input signal processing of the sequencer CPU unit is 16 bits, the conventional A/
The D conversion unit has 16 points of input signals to the sequencer CPU unit, but of the 16 points, only one point ()l) of "rA/D flag" is valid as a white signal, and the remaining 15 points (Xi...) was merely to reduce the number of input contacts that can be controlled by the sequencer.

The present invention was made in view of the above-mentioned problems, and its purpose is to transmit the rA/D flag to the sequencer CPU without creating input contacts that the sequencer cannot control.
A that can be given as an input signal to the unit
/D conversion unit.

[Means for Solving the Problems] The present invention includes a CPU that performs signal processing, and an A/D system that converts analog values into
An A/D converter to be converted, a shared memory that is accessible from both the sequencer CPU unit and the CPU and for exchanging A/D conversion data between the sequencer CPU unit, and a switch element controlled by the CPU. It is characterized by having the following.

[Function] The sequencer A/D conversion unit of the present invention uses the above A/D flag for controlling data access from the sequencer CPU unit to the sequencer A/D conversion unit according to the operating state. By controlling the switching elements with the CPU and providing the switching output to the sequencer CPU unit, it is no longer necessary to generate input signals that cannot be used for sequence control.

[Example] The present invention will be explained below with reference to Examples.

FIG. 1 shows a circuit of one embodiment, in which a latch circuit 13 is provided on the A/D conversion unit side to give the rA/D flag to the sequencer CPU unit;
When the output of becomes "L", the light emitting element LED emits light and the phototransistor PT.

is turned on, the relay RY connected between the power input terminal T and the common terminal T2 via the phototransistor Pro of the photocoupler 14, and the signal output terminal T and the common terminal T2. One solution is to provide an A/D flag output means consisting of the relay contact r of the connected relay RY in place of the conventional buffer circuit 12 and address decoder circuit 9, and as shown in FIG. A light emitting diode LED is installed between the power supply output terminals T and ' and the input terminal
Photocoupler 14 connected in the forward direction with respect to the input power supply
The power output terminal TI' is connected to the power input terminal T1 of the sequencer A/D conversion unit I, and the common terminal COM connected to the ground is connected to the A/D converter unit I. Connect to common terminal T2 of D conversion unit ■, and input terminal x0 to A/D
It is connected to the signal output terminal T of the conversion unit ■.

Therefore, in the A/D conversion unit I, when turning on the "rA/D flag" in the flowchart of FIG.
The relay RY is controlled through the latch circuit 13 and the photocoupler 14 to turn on the relay contact r, and when the rA/D flag is turned off, the relay contact r is turned off.

Therefore, when the relay contact r turns on, a light emitting current flows through the light emitting diode LED of the photocoupler 15 on the side of the input unit ■, turning on the phototransistor PT, and an “L” signal enters the internal circuit 16 of the input unit as X0 input. Furthermore, it is taken into the sequencer CPU unit as an rA/D flag.

In this way, the "rA/D flag" can be given from the sequencer A/D conversion unit I to the sequencer CPU unit (2) without specially generating an input signal that cannot be used for sequence control.

Incidentally, as shown in FIG. 3, a semiconductor switching element such as a transistor Tr may be used instead of the relay RY.

[Effects of the invention] The present invention uses a cPU that performs signal processing and an A/D converter that processes analog values.
An A/D converter to be converted, a shared memory that is accessible from both the sequencer CPU unit and the CPU and for exchanging A/D conversion data between the sequencer CPU unit, and a switch element controlled by the CPU. The A/D flag for controlling data access from the sequencer CPU unit to the sequencer A/D conversion unit according to the operating state is controlled by the CPU, and the switching output is used for the sequencer. Since it is given to the CPU unit,
It is not necessary to generate an input signal that cannot be used for sequence control as in the conventional method, and furthermore, there is an effect that a circuit such as an address decoder circuit required for processing a sequencer input signal from a sequencer CPU unit is not required.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a main part of the same as above, Fig. 3 is a circuit diagram of a main part of another embodiment of the invention, and Fig. 4 is a conventional example. 5 is a flowchart for explaining the operation of the same as above, and FIG. 6 is a diagram for explaining the same program as above, 1 is an A/D converter, 4 is a shared memory, 5 is a CPU, 13 is a latch circuit, RY is a relay, 14 is a photocoupler, and r is a relay contact. Agent: Patent Attorney Ishi 1) Voluntary action to amend Figure 716 procedure) 1. Indication of the case Showa 63 Patent Application No. 241740 2. Name of the invention A/D conversion unit for sequencer 3. Person making the amendment Relationship with the case Patent applicant address: 1048 Kadoma, Kadoma City, Osaka Prefecture Name (58
3) Matsushita Electric Works Co., Ltd. Representative Toshio Miyoshi 4 Agent postal code 530 Address 1-12-17-5 Umeda, Kita-ku, Osaka City Date of amendment order 6 Number of claims increased by amendment None 7. Subject of amendment Specification

Claims (1)

[Claims] (1) The CPU that performs signal processing, the A/D converter that converts analog values into A/D, and the sequencer CPU unit that can be accessed from both the CPU unit and the above CPU, and A/D conversion data can be exchanged between the sequencer CPU unit. An A/D flag is provided with a shared memory for communication and a switch element controlled by the CPU, and is used to control data access from the sequencer CPU unit to the sequencer A/D conversion unit depending on the operating state. An A/D conversion unit for a sequencer, characterized in that the switching output of the switch element is applied to a CPU unit for a sequencer.