JPH0594547A - Microprocessor - Google Patents

Abstract

PURPOSE:To prevent one address bus out of an address bus for specifying I/O addresses and an address bus for specifying memory addresses from being influenced by the other memory bus generating a fault by independently setting up respective address buses. CONSTITUTION:An address bus switching part 4 is connected to the post stage of an address control part 1, and when an instruction decoded by an instruction decoding part 2 is an I/O instruction, the decoding part 2 generates a status signal 5 to the switching part 4 to switch an address bus to an I/O-only address bus 6 and a memory access-only address bus 7. If a fault is generated, whether the fault is generated in I/O part or a memory access part can easily be distinguished.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor, and more particularly to a microprocessor having a control mechanism for external peripheral devices.

[0002]

2. Description of the Related Art In a conventional microprocessor,
The address bus required for specifying the memory address at the time of memory access is exactly the same as the address bus specifying the I / O address to the peripheral device connected to the microprocessor. .. Therefore, in the case of controlling the peripheral device, a circuit for determining which is by referring to a signal indicating whether the address bus indicates a memory address or an I / O address. Configuration required.

[0003]

As described above, in the conventional microprocessor, the address bus for specifying the memory address and the address bus for specifying the I / O address are the same. If the error occurs, there is a drawback in that the error spreads to the memory relationship even though the failure has occurred in the I / O relationship.

An object of the present invention is to provide a microprocessor which solves the above problems.

[0005]

In order to achieve the above object, a microprocessor according to the present invention has a memory access dedicated address bus and an I / O control dedicated address bus, which are controlled separately. It is a thing.

Further, if the decoded instruction is an I / O instruction, the address bus is switched between the I / O dedicated address bus and the memory access dedicated address bus.

[0007]

In the present invention, the address bus for I / O control and the address bus for memory access are separated, and each is controlled separately.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 is an address control unit, 2 is an instruction decoding unit, 3 is an instruction execution unit, 3 is an address bus switching unit, 5 is a status signal, 6 is an I / O control dedicated address bus, and 7 is a memory access dedicated address. The bus 8 is an instruction execution end signal.

The status signal 5 is output from the instruction decoding unit 2 and is input to the address bus switching unit 4 and simultaneously output to the outside of the microprocessor.

The instruction execution end signal 8 is output from the instruction execution section 3 and input to the address bus switching section 4.

In FIG. 1, the microprocessor enters an instruction decoding cycle and recognizes that the instruction to be decoded by the instruction decoding section 2 is an I / O control instruction. The status signal 5 has a low level when it is recognized as an I / O control command, and has a high level for other commands. This signal is also transmitted outside the microprocessor. The peripheral device can know the execution of the I / O instruction by this signal.

When the instruction decoding unit 2 recognizes that the instruction to be decoded is an I / O control instruction, the state signal 5 is set to low level. The status signal 5 is input to the address bus switching unit 4, and based on this signal, the address bus switching unit 4 sets the address bus input or output to the address control unit 1 to the I / O dedicated address bus 6 and the memory access dedicated address. Switch to bus 7.

When the I / O control instruction is executed in the instruction executing section 1 and is completed, an instruction execution end signal 8 is output, and the instruction decoding section 2 receives the status signal 5 by this signal.
To high level. In this state, the address bus switching unit 4 switches the address bus to the memory access dedicated address bus 7.

The address bus switching unit 4 has a signal state holding function, and holds the state of the I / O control dedicated address bus 6 or the memory access dedicated address bus 7 before switching by this function. In this way, even if the address bus switching unit 4 switches the address bus, the effect that the address bus becomes high impedance with respect to the memory or peripheral device connected to the invalid address bus is prevented. ..

[0016]

According to the present invention, the address bus to the peripheral device of the microprocessor and the address bus to the memory are separated, and the influence of the fault occurring in the peripheral device affects the memory access to cause the secondary fault. It is possible to prevent it. Further, when a failure occurs, there is an effect that the failure location can be easily identified according to the failure situation.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

[Description of Codes] 1 address control unit 2 instruction decoding unit 3 instruction execution unit 4 address bus switching unit

Claims (2)

[Claims] 1. An address bus dedicated to memory access and I / I
A microprocessor having an O control-dedicated address bus and controlled separately. 2. The address bus is switched between an I / O dedicated address bus and a memory access dedicated address bus if the decoded instruction is an I / O instruction. Microprocessor.