JPH028977U - - Google Patents

Info

Publication number
JPH028977U
JPH028977U JP1988086505U JP8650588U JPH028977U JP H028977 U JPH028977 U JP H028977U JP 1988086505 U JP1988086505 U JP 1988086505U JP 8650588 U JP8650588 U JP 8650588U JP H028977 U JPH028977 U JP H028977U
Authority
JP
Japan
Prior art keywords
memory
circuit section
wiring board
printed wiring
memory card
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988086505U
Other languages
Japanese (ja)
Other versions
JPH081110Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988086505U priority Critical patent/JPH081110Y2/en
Priority to EP19890907813 priority patent/EP0379592A4/en
Priority to PCT/JP1989/000643 priority patent/WO1990000117A1/en
Publication of JPH028977U publication Critical patent/JPH028977U/ja
Application granted granted Critical
Publication of JPH081110Y2 publication Critical patent/JPH081110Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａは本考案の一実施例におけるＩＣメモ
リーカードの一部を切欠いた斜視図、第１図ｂは
同じく部分断面図、第２図は同じく電気回路のブ
ロツク図、第３図は同じくメモリーＬＳＩチツプ
の積層状態を示す斜視図である。 １……ケース、２……プリント配線板、３……
メモリー回路部、４……コントロール回路部、５
……外部インターフエース回路部、６……メモリ
ーＬＳＩチツプ、９……電池、１０……絶縁材、
１１……電極、１２……導体リード。 Figure 1a is a partially cutaway perspective view of an IC memory card according to an embodiment of the present invention, Figure 1b is a partial sectional view, Figure 2 is a block diagram of the electric circuit, and Figure 3 is the same. FIG. 2 is a perspective view showing a stacked state of memory LSI chips. 1... Case, 2... Printed wiring board, 3...
Memory circuit section, 4... Control circuit section, 5
...External interface circuit section, 6...Memory LSI chip, 9...Battery, 10...Insulating material,
11...electrode, 12...conductor lead.

Claims (1)

【実用新案登録請求の範囲】 (1) メモリー回路部、コントロール回路部、外
部インターフエース回路部とから構成されるプリ
ント配線板と、前記プリント配線板を収納するケ
ースとを備え、前記メモリー回路部を構成するメ
モリーＬＳＩチツプの電極に、導体リードを接合
するとともに、前記プリント配線板に前記メモリ
ーＬＳＩチツプを、複数個積層して搭載したこと
を特徴とするＩＣメモリーカード。 (2) メモリー回路部をバツクアツプする電池を
内蔵した実用新案登録請求の範囲第１項記載のＩ
Ｃメモリーカード。 (3) 積層したメモリーＬＳＩチツプの間に、絶
縁材が挿入されている実用新案登録請求の範囲第
１項記載のＩＣメモリーカード。[Claims for Utility Model Registration] (1) A printed wiring board comprising a memory circuit section, a control circuit section, and an external interface circuit section, and a case housing the printed wiring board, the memory circuit section An IC memory card characterized in that conductor leads are bonded to electrodes of memory LSI chips constituting the IC memory card, and a plurality of the memory LSI chips are stacked and mounted on the printed wiring board. (2) I as stated in paragraph 1 of the utility model registration claim, which has a built-in battery for backing up the memory circuit section.
C memory card. (3) The IC memory card according to claim 1, wherein an insulating material is inserted between the stacked memory LSI chips.
JP1988086505U 1988-06-29 1988-06-29 IC memory card Expired - Lifetime JPH081110Y2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP1988086505U JPH081110Y2 (en) 1988-06-29 1988-06-29 IC memory card
EP19890907813 EP0379592A4 (en) 1988-06-29 1989-06-28 Ic memory card
PCT/JP1989/000643 WO1990000117A1 (en) 1988-06-29 1989-06-28 Ic memory card

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988086505U JPH081110Y2 (en) 1988-06-29 1988-06-29 IC memory card

Publications (2)

Publication Number Publication Date
JPH028977U true JPH028977U (en) 1990-01-19
JPH081110Y2 JPH081110Y2 (en) 1996-01-17

Family

ID=31311144

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988086505U Expired - Lifetime JPH081110Y2 (en) 1988-06-29 1988-06-29 IC memory card

Country Status (1)

Country Link
JP (1) JPH081110Y2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080232A (en) * 1983-10-11 1985-05-08 Nippon Telegr & Teleph Corp <Ntt> Lsi chip mounting card
JPS60129897A (en) * 1983-12-19 1985-07-11 Sony Corp Miniature electronic device
JPS60189860U (en) * 1984-05-25 1985-12-16 オムロン株式会社 Current transformer output circuit
JPS62179993A (en) * 1986-02-04 1987-08-07 カシオ計算機株式会社 Electronic card

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6080232A (en) * 1983-10-11 1985-05-08 Nippon Telegr & Teleph Corp <Ntt> Lsi chip mounting card
JPS60129897A (en) * 1983-12-19 1985-07-11 Sony Corp Miniature electronic device
JPS60189860U (en) * 1984-05-25 1985-12-16 オムロン株式会社 Current transformer output circuit
JPS62179993A (en) * 1986-02-04 1987-08-07 カシオ計算機株式会社 Electronic card

Also Published As

Publication number Publication date
JPH081110Y2 (en) 1996-01-17

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