JPH0288985A - False signal generator - Google Patents

Abstract

PURPOSE:To obtain false signals of a stable level by receiving plural delayed outputs by giving plural kinds of delay time to false digital random signals after the random signals are shifted and shaping waveforms of the delayed outputs corresponding to each channel. CONSTITUTION:A false random binary sequence generation circuit 1 generates a false random binary sequence in accordance with the clock of a clock generation circuit 7 and a shift register 2 is shifted one bit by one bit by the clock of the circuit 7 and shifts digital random signals. Thus prescribed delay time is given to the false digital random sequence and each delayed signal is subjected to waveform shaping and low-pass filtration. Therefore, the circuit can be digitized and the problem of the signal level variation at the time of setting the delay time can be removed in principle.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pseudo signal generator, and more particularly to a pseudo signal generator that simulates an output electrical signal of an underwater acoustic receiver.

(Prior Art) Conventionally, a device that generates a pseudo signal that simulates the output signal of an underwater acoustic receiver uses an analog random noise signal.

An example of this type of pseudo signal generator is shown in FIG. 3! ! N delay times are set for the input signal by the delay element 9, and the signals delayed by each time are subjected to impedance matching by the amplifier circuit 10. The N delayed signals thus obtained are respectively taken out as pseudo signals of channels CHI to CHH. The extraction of this channel signal is performed by operating the switching circuit 11 in response to a switching signal from the switching control circuit 12.

(Problems to be Solved by the Invention) The conventional device described above delays the analog random signal from the random noise generating circuit in an analog manner using a delay element, and then switches the M extended signal using an analog switch. Therefore, an amplifier circuit or the like was required to correct the attenuation of the delay element and perform input/output impedance matching. Furthermore, since analog signal processing is used, an additional AMP circuit is required in principle for the number of delay elements or delay stages, resulting in a disadvantage that the circuit configuration becomes complicated. To avoid this drawback, if the amplifier circuit is omitted,
If the delay amount setting is changed, the attenuation amount will change, making it impossible to obtain a stable pseudo signal level.

(Means for Solving the Problems) A pseudo signal generation device according to the present invention includes a pseudo random signal generation circuit that generates a pseudo digital random signal, and a pseudo random signal that shifts the pseudo digital random signal and outputs it after giving a plurality of delay times. a shift register that receives multiple delayed outputs from this shift register and performs a switching operation to take out the delayed output corresponding to each channel; a waveform shaping circuit that shapes the output of this switching circuit into a waveform; The device includes a low-pass filter that passes low-frequency components of the output of the shaping circuit, and a switching control circuit that controls the switching operation of the switching circuit.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a pseudo signal generating circuit according to the present invention.

Pseudo-random binary sequence generation circuit 1 is tarock generation circuit 7
A pseudo-random binary sequence is generated in response to a clock from the shift register 2 and is supplied to the shift register 2.

The shift register 2 is shifted bit by bit by the tarlock from the tarlock generating circuit 7, and shifts the digital random signal. The shift register 2 has a multi-stage shift configuration, and the output from each stage is a signal obtained by delaying the input signal by the corresponding time.6 In this embodiment, the shift register has an N-stage configuration, and N outputs (N (delayed output) are supplied to N switching circuits 3(1) to 3(N), respectively. The switching circuits 3(1) to 3(N) are switched and controlled by a switching signal from the switching control circuit 6, and supply each delayed output to the corresponding waveform shaping circuits 4(1) to 4(N). The waveform shaping circuits 4(1) to 4(N) correspond to the corresponding switching circuits 3(1) to 3.
Converts the delayed signal (unipolar digital signal) from (N) into a bipolar signal that changes between positive and negative. Low pass filter (
LPF) 5(1) to 5(N) are the corresponding waveform shaping circuits 4
The low frequency components of the bipolar signals sent from (1) to 4(N) are allowed to pass. The signals from the low-pass filters 5(1) to 5(N) thus obtained are transmitted to channels CHI to CHI.
This becomes a HH pseudo signal.

The digital random signal generated by the pseudo-random binary sequence generation circuit 1 passes through the waveform shaping circuit 4 and the low-pass filter 5, and by setting the random sequence sufficiently long and the clock frequency sufficiently high, a random signal can be obtained. For example, when the pseudo signal is 15KH2 and the clock frequency is IOMH2, a random noise signal with a pseudo-random binary sequence length of <2"-1) is obtained. This pseudo-random binary sequence signal is shifted and delayed by the shift register 2. The output delayed by the necessary time is selected by the switching circuit N3, and then passed through the waveform shaping port 840-pass filter 5 to generate a pseudo signal of random noise having the necessary delay time between each channel.

(Effects of the Invention) As explained above, the present invention provides a digital pseudo-random binary sequence with a predetermined delay time using a shift I register,
By waveform shaping and low-pass filtering each delayed signal, it is possible to digitize the circuit, making it possible to theoretically eliminate the problem of signal level fluctuations when setting the delay time, and simplifying the circuit configuration. It becomes possible to do so.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a pseudo signal generating device according to the present invention, and FIG. 2 is a block diagram of a conventional pseudo signal generating device. l... Pseudo random binary sequence generation circuit, 2... Shift register, 3... Switching circuit, 4... Waveform shaping circuit, 5... Low pass filter, 6... Switchability circuit, 7
...Re-lock generation circuit. 8... Random noise generation circuit 9... Delay element, 0... Amplifying circuit, 1... Switching circuit, 2... Switching control circuit.

Claims (1)

[Claims] a pseudo-random signal generation circuit that generates a pseudo-digital random signal; a shift register that shifts the pseudo-digital random signal and outputs it after giving a plurality of delay times; and receiving a plurality of delayed outputs from the shift register;
a switching circuit that performs a switching operation to take out a delayed output corresponding to each channel; a waveform shaping circuit that shapes the output of the switching circuit; a low-pass filter that passes a low frequency component of the output of the waveform shaping circuit; 1. A pseudo signal generating device comprising: a switching control circuit that controls switching operation of a switching circuit.