JPH0288184U - - Google Patents

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Publication number
JPH0288184U
JPH0288184U JP16697388U JP16697388U JPH0288184U JP H0288184 U JPH0288184 U JP H0288184U JP 16697388 U JP16697388 U JP 16697388U JP 16697388 U JP16697388 U JP 16697388U JP H0288184 U JPH0288184 U JP H0288184U
Authority
JP
Japan
Prior art keywords
fixed distance
distance scale
generation circuit
rom
reference clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16697388U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16697388U priority Critical patent/JPH0288184U/ja
Publication of JPH0288184U publication Critical patent/JPH0288184U/ja
Pending legal-status Critical Current

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  • Radar Systems Or Details Thereof (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による固定距離目
盛発生回路のブロツク図、第2図はこの考案の一
実施例である表示器に示された固定距離目盛の図
、第3図は従来の固定距離目盛発生回路のブロツ
ク図、第4図は従来の表示器に示された固定距離
目盛の図である。図において、1は基準クロツク
発生回路、4はビデオ増巾器、5はスイープ作成
回路、6は基準クロツク信号、7は表示用クロツ
ク信号、8は混合ビデオ信号、9はレーダトリガ
信号、10はスイープビデオ信号、11はレーダ
ビデオ信号、13は並列出力カウンタ、14は固
定距離指定回路、15はROM、16はD/Aコ
ンバータ、17はROMアドレス、18は固定距
離データ、19は距離目盛データ、20は固定距
離目盛、21は輝度の高い固定距離目盛を示す。
なお、図中、同一符号は同一、又は相当部分を示
す。
Fig. 1 is a block diagram of a fixed distance scale generation circuit according to an embodiment of this invention, Fig. 2 is a diagram of a fixed distance scale shown on a display according to an embodiment of this invention, and Fig. 3 is a diagram of a conventional fixed distance scale generation circuit. A block diagram of a fixed distance scale generation circuit, FIG. 4, is a diagram of a fixed distance scale shown on a conventional display. In the figure, 1 is a reference clock generation circuit, 4 is a video amplifier, 5 is a sweep generation circuit, 6 is a reference clock signal, 7 is a display clock signal, 8 is a mixed video signal, 9 is a radar trigger signal, and 10 is a sweep. 11 is a radar video signal, 13 is a parallel output counter, 14 is a fixed distance designation circuit, 15 is a ROM, 16 is a D/A converter, 17 is a ROM address, 18 is fixed distance data, 19 is distance scale data, 20 is a fixed distance scale, and 21 is a high brightness fixed distance scale.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] PPI表示器において、基準クロツクと、アド
レスを指定するためのカウンタと、目盛データを
記憶するためのROMとを備えたことを特徴とす
る固定距離目盛発生回路。
A fixed distance scale generation circuit for a PPI display, comprising a reference clock, a counter for specifying an address, and a ROM for storing scale data.
JP16697388U 1988-12-24 1988-12-24 Pending JPH0288184U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16697388U JPH0288184U (en) 1988-12-24 1988-12-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16697388U JPH0288184U (en) 1988-12-24 1988-12-24

Publications (1)

Publication Number Publication Date
JPH0288184U true JPH0288184U (en) 1990-07-12

Family

ID=31454846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16697388U Pending JPH0288184U (en) 1988-12-24 1988-12-24

Country Status (1)

Country Link
JP (1) JPH0288184U (en)

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