JPH0287830A - Capacitive keyboard - Google Patents

Abstract

PURPOSE:To shorten the processing time by giving a hysteresis to a reaction voltage at the time of boosting the depression signal from a key matrix to a prescribed voltage in the case of depression of a key in the key matrix synchronous with the address signal supplied from an external device and using a RAM to change this hysteresis. CONSTITUTION:When a capacitive key C in a key matrix 3 is depressed synchronously with the address signal supplied from a host computer, a key depression signal is outputted correspondingly to this address signal. A hysteresis is given to the reaction voltage at the time of boosting the depression signal from the key matrix 3 to a prescribed voltage, and a RAM 9 is used to change this hysteresis, and then, the key depression signal is outputted to the host computer after being sampled twice. Consequently, chattering is prevented, and reaction is possible only in the transmission time of each circuit. Thus, the processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a capacitive keyboard using capacitive switches that detect key operations based on changes in capacitance.

(Prior Art) Conventionally, for example, a large number of keys are arranged in a plane, predetermined characters such as alphabets, numbers, symbols, codes, etc. are assigned to these keys, and the above-mentioned keys that are set in advance are moved when these keys are operated. A so-called keyboard is known that sends out coded signals corresponding to characters.

As a structure of such a keyboard, a capacitive keyboard using capacitive keys with good durability and excellent key touch has been put into practical use (Japanese Patent Application Laid-Open No. 59-1999).
65348, JP-A-60-181815).

In this capacitive keyboard, changes in capacitance between electrodes due to key operations are boosted to a predetermined voltage by a sense amplifier to obtain an on/off signal for the key.

That is, a sense amplifier converts a capacitance change between the electrodes due to a key operation into a voltage change, amplifies it to a predetermined voltage, and outputs this amplified output as a key press sensing signal.

In such a capacitive keyboard, a C for controlling the key switches is installed on the keyboard circuit board.
It is composed of a PU (central processing unit), etc.

However, with a capacitive keyboard configured by a CPU, processing time (calculation time) is required for key detection and key address requests from the host computer.
However, the processing time was several m5ec, which resulted in a long processing time.

This is particularly problematic when a fast response from the host computer is required.

(Problems to be Solved by the Invention) As described above, it is an object of the present invention to provide a capacitive keyboard that eliminates the drawback that processing time is long and can shorten processing time.

[Structure of the Invention] (Means for Solving the Problems) The capacitive keyboard of the present invention has a key matrix in which capacitive keys are provided at the intersections of a matrix composed of a plurality of rows and columns, and an address signal sequentially supplied from an external device. a first output circuit that outputs a selection signal for selecting the row and column of the key matrix according to the key matrix; a switch, a sense amplifier that converts the signal from the analog switch into a voltage signal, and boosts the voltage value to a predetermined voltage when the voltage signal is greater than or equal to the first voltage value or the second voltage value; and the external device described above. a detection circuit that detects a change in the address signal from the detection circuit; a second output circuit that outputs a sampling pulse in response to the detection signal from the detection circuit; and a timing pulse output in response to the sampling pulse from the second output circuit. a third output circuit that outputs an output; a first holding circuit that holds the output of the sense amplifier in response to a sampling pulse from the second output circuit; and a first holding circuit that clears the output in response to a detection signal from the detection circuit; When a timing pulse is supplied from the third output circuit, the address signal from the external device is stored in accordance with the content held by the first holding circuit, and the same address signal as this address signal is output from the external device. a storage circuit that outputs data when supplied from the device; a second holding circuit that holds data output from the storage circuit in response to a detection signal from the detection circuit; a fourth output circuit that compares the data held by the first holding circuit with the data held by the first holding circuit and outputs a key press signal to the external device when they match; and a fourth output circuit that is supplied from the storage means It is comprised of a changing means for changing the reaction voltage of the sense amplifier from a first voltage value to a second voltage value in accordance with data.

(Operation) According to the present invention, when a key in a key matrix is pressed in synchronization with an address signal supplied from an external device, a key press signal is output in response to the address signal. , hysteresis is provided in the reaction voltage when boosting the press signal from the key matrix to a predetermined voltage,
By changing this hysteresis using RAM, the key press signal is output to the external device after sampling twice.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a capacitive keyboard according to the present invention, in which an address decoder (first output circuit) 1.2,
Key matrix 3, analog switch 4.5, amplifier circuit (sense amplifier) 6, FF circuit for holding amplifier output (
1st holding circuit) 7.1 FF for holding pre-scan data
Circuit (second holding circuit) 8, static RAM (R
AM, memory circuit) 9, NAND circuit 10. Address change point detection circuit (detection circuit) 11, delay circuit 12, FF circuit control timing pulse output circuit 13, sampling pulse output circuit (second output circuit) 14, and timing pulse output circuit (third output circuit) circuit) 15.

When the address decoder 1 is supplied with the sampling signal from the sampling pulse output circuit 14, the address decoder 1 reads each row of the key matrix 3, that is, the drive line 3a%... The address decoder 2 outputs a drive signal to each column of the key matrix 3, that is, the sense line 3b, .
・Turns on analog switch 4.5 corresponding to . The address decoder 1.2 is, for example, a TTL
(LS145).

The key matrix 3 includes a plurality of rows (drive lines) 3a1... and columns (sense lines) 3b,...
A capacitive key C1... whose capacitance changes with each key operation is provided at the intersection of the keys C1 and C1. One end of the drive line 3a, . . . has a resistor Ra, .
The negative ends of the sense lines 3b, . . . are connected to a resistor R (not shown) through the respective resistors R.
b, . . . are connected to a power source (not shown).

The structure of the above-mentioned capacitive key C1... is such that a fixed electrode is provided with a movable electrode that can be moved toward and away from the fixed electrode by pressing the key, and one electrode is connected to a row and the other electrode is connected to a column. It has become. When the capacitive key C is released from the pressed state, the capacitance Ii
(key voltage) gradually decreases.

The analog switch 4.5 switches the key matrix 3 in response to a signal supplied from the address decoder 2.
By turning on the switches corresponding to each column, that is, the sense lines 3b, . . . , the sense lines 3b, as shown in FIG. 2(f).

. . to the amplifier circuit 6. The analog switch 4.5 is, for example, a CMOS (4
066 or 4051).

The amplifier circuit 6 converts the signal supplied from the analog switch 4.5 into a voltage signal, that is, a key press minute signal, and when this key press minute signal is below a first voltage value or below a second voltage value, (I first voltage value 1>1 second voltage value 1), which outputs a key press signal as shown in FIG. 2 (g) amplified to the logic circuit voltage level (predetermined voltage; 5V) It is. This key press signal is output to the FF circuit 7 when a sampling pulse is supplied from the sampling pulse output circuit 14.

When "0" is supplied to the terminal STB, the amplifier circuit 6 outputs the key press signal amplified to the voltage level of the logic circuit when the key press minute signal is less than the first voltage value, and outputs the key press signal amplified to the voltage level of the logic circuit. When "1" is supplied to , when the key press minute signal is less than the second voltage value, a key press signal amplified to the voltage level of the logic circuit is output. As a result, even if the key voltage drops when the capacitive key C is about to be released from its pressed state, resulting in a small voltage change (within the hysteresis voltage level), a boosted signal will be output in response. It has become.

The FF circuit 7 is an FF circuit for holding the amplifier output, and is cleared in response to a timing pulse from the FF circuit control timing pulse output circuit 13, and receives a key press signal from the amplifier circuit 6 as shown in FIG. It is held as shown in (h).

The FF circuit 8 is an FF circuit for holding data before one scan, and is latched in response to a timing pulse from the FF circuit control timing pulse output circuit 13, and outputs data from the RAM 9 as shown in FIG. It is to be held as shown in k). The FF circuit 7.8 is configured by, for example, TTL (LS74).

When a timing pulse is supplied from the timing pulse output circuit 15, the RAM 9 responds to an address signal from the host computer as shown in FIG. 2(m) in response to the output of the FF circuit 7. A flag "1" is set in the area, and when the address corresponding to the area where the flag is set, that is, the same address signal as the above address signal is supplied (after one scan), the "1" signal is sent to the amplifier circuit 6. At the same time as outputting to terminal 5TB- of
It is output to the data input end of the FF circuit 8.

Further, instead of setting a flag, the RAM 9 may store the address as it is and compare the stored address with the same address (after one scan).

The NAND circuit 10 outputs a key press signal to a host computer (not shown) as shown in FIG. 2(1) in response to the held output of the FF circuit 7.8, and When a "1" signal is supplied from 7.8, a "0" signal is output as a key press signal.

As a result, the host computer
When a “0” signal is supplied as a key press signal from
The press of the corresponding capacitive key C is determined based on the address signal being output at that time.

The address change point detection circuit 11 detects the change point of an address signal supplied from a host computer (not shown), and includes a latch circuit 16 that latches the address signal, and a latch circuit 16 that latches the address signal and the host computer. E to compare with the address signal from the computer
It is constituted by an OR circuit 17. That is, when the latched contents of the latch circuit 16 and the address signal from the host computer do not match, a change point detection signal as shown in FIG. 2(C) is output to the delay circuit 12 and a timing pulse for controlling the FF circuit. It is configured to output to the circuit 13. The latch circuit 16 is reset by the set output of the sampling pulse output circuit 14. The upper latch circuit 16 is constituted by, for example, TTL (L9373), and the above E
The OR circuit 17 is constituted by, for example, TTL (.LS266).

In order to prevent noise during switching by the analog switch 4.5, the delay circuit 12 converts the change point detection signal from the address change point detection circuit 11, that is, the EOR circuit 17, as shown in FIG. 2(d). The delayed signal is output to the sampling pulse output circuit 14. The delay circuit 12
For example, the EOR circuit 18 and the resistor R1 are used as an inverting circuit.
, R2, and a capacitor C1.

The timing pulse output circuit 13 for controlling the FF circuit is
The address change point detection circuit 11, that is, the EOR circuit 17
A timing pulse as shown in FIG. 2(i) is output based on the change point detection signal from the FF circuit 7.8, and this timing pulse is output to the clock terminal of the FF circuit 7.8. . The timing pulse output circuit 13 for controlling the FF circuit may be used as an EOR circuit as an inverting circuit, for example.
It is composed of a circuit 19, resistors R3 and R4, and a capacitor C2.

In response to the signal from the delay circuit 12, the sampling pulse output circuit 14 outputs a signal as shown in FIG. 2(e).
This sampling pulse is outputted to the input terminal of the timing pulse output circuit 15, the data terminal D1 of the address decoder 1, and the gate terminal of the amplifier circuit 6.

The FF circuit control timing pulse output circuit 13 and the sampling pulse output circuit 14 are connected to a capacitor Ca and a resistor Re for pulse width adjustment (pulse width adjustment is performed using their time constants), respectively.

The timing pulse output circuit 15 outputs a timing pulse as shown in FIG. 2(j) in response to the sampling pulse from the sampling pulse output circuit 14, and this timing pulse is transmitted to the
9 is output. The sampling pulse output circuit 14 and the timing pulse output circuit 15 are configured by, for example, TTL (LS123).

Note that the address signals supplied from the host computer may be supplied in order or may be supplied at random.

Next, the operation in such a configuration will be explained.

For example, a case will be described in which the capacitive key C corresponding to the A address (key A) is pressed. That is, as shown in FIG. 2(b), key A is pressed, and the host computer (not shown) sends the message (
As shown in a), the A address is sent to address decoder 1.
2, the RAM 9, and the address change point detection circuit 11. Then, the address change point detection circuit 11, ie, the EOR circuit 17, outputs an address change point detection signal as shown in FIG. 2(c) to the delay circuit 12. As a result, the delay circuit 12 outputs a signal as shown in FIG. 3(d) to the sampling pulse output circuit 14. Then, the sampling pulse output circuit 14 outputs a sampling pulse as shown in FIG. 2(e) to the gate terminal of the amplifier circuit 6 and the data terminal of the address decoder 1.

As a result, the address decoder 1 outputs a drive signal from a predetermined drive line 3a in accordance with the address, and the address decoder 2 turns on the analog switch 4 or 5 corresponding to the predetermined sense line 3b.

Then, in response to the press of the key A, the analog switch 4 or 5 outputs a key press minute signal to the amplifier circuit 6 as shown in FIG. Further, a “0” signal is supplied from the RAM 9 to the terminal STB of the amplifier circuit 6.

Further, the address change point detection signal from the EOR circuit 17 is output to the FF circuit control timing pulse output circuit 13. As a result, the FF circuit control timing pulse output circuit 13 outputs a timing pulse (reset output) as shown in FIG. 3(i) to the FF circuit 7. Therefore, FF circuit 7 is cleared.

As a result, the amplifier circuit 6 outputs a signal as shown in FIG. 3(g) to the FF circuit 7 when the key press signal is less than or equal to the first voltage value. Then, the FF circuit 7 is set, and this set output "1" is output to the NAND circuit 10 and the data terminal Din of the RAM 9. At this time, the FF circuit 8 remains in the reset state, and its set output is "0".

Therefore, data is not output from the NAND circuit 10.

Furthermore, in response to the rise of the sampling pulse from the sampling pulse output circuit 14, a (write) timing pulse as shown in FIG. As a result, the RAM 9 sets a flag in the area corresponding to the address from the host computer.

Then, when another address is supplied from the host computer next time, the address change point detection circuit 11, that is, the EO
The R circuit 17 outputs an address change point detection signal as shown in FIG. 2(c) to the delay circuit 12. As a result, the delay circuit 12 outputs a signal as shown in FIG. 3(d) to the sampling pulse output circuit 14. Then, a sampling pulse as shown in FIG. 3(e) is outputted from the sampling pulse output circuit 14 to the gate terminal of the amplifier circuit 6 and the address decoder 1.

In this case, since key A is pressed, y%g switch 4
, or the key press minute signal is not output from 5 to the amplifier circuit 6.

Further, the address change point detection signal from the EOR circuit 17 causes the FF circuit control timing pulse output circuit 1 to
3 outputs a timing pulse to the FF circuit 7. As a result, the FF circuit 7 is cleared. Therefore, data is not output from the NAND circuit 10.

Thereafter, each time a different address is supplied, the same operation as above is performed, and no data is output from the NAND circuit 10.

Then, when one scan is performed and the A address is supplied again from the host computer, the A address is output to the address decoder 1.2, RAM 9, and address change point detection circuit 11. This allows the RAM
9 is supplied with the address corresponding to the area where the flag is set, and receives the "1" signal from the data terminal Dout (see Figure 9).
m)) is output to the terminal STB of the amplifier circuit 6 and the data terminal of the FF circuit 8.

Further, the address change point detection circuit 11, that is, the EOR circuit 1
7, an address change point detection signal as shown in FIG. 7(C) is output to the delay circuit 12. As a result, the delay circuit 12 outputs a signal as shown in FIG. 3(d) to the sampling pulse output circuit 14. Then, a sampling pulse as shown in FIG. 3(e) is outputted from the sampling pulse output circuit 14 to the gate terminal of the amplifier circuit 6.

Further, in response to the depression of the key A, the analog switch 4 or 5 outputs a small key depression signal to the amplifier circuit 6 as shown in FIG.

Further, the terminal STB of the amplifier circuit 6 is connected to “1” from the RAM 9.
” signal is being supplied.

Further, the address change point detection signal from the EOR circuit 17 is output to the FF circuit control timing pulse output circuit 13. As a result, the FF circuit control timing pulse output circuit 13 outputs a timing pulse as shown in FIG. 3(i) to the FF circuit 8. Therefore, the FF circuit 8
is set, and this set output "1" is output to the NAND circuit 10.

As a result, the amplifier circuit 6 outputs a signal as shown in FIG. 4(g) to the FF circuit 7 when the key press signal is less than the second voltage value. Then, the FF circuit 7 is set, and this set output "1" is output to the NAND circuit 10. Therefore, a key press signal ("O" signal) as shown in FIG. 1 (1) is output from the NAND circuit 10 and supplied to the host computer.

As a result, the host computer
When a “0” signal is supplied as a key press signal from
Based on the address signal (A address) being output at that time, it is determined whether the corresponding capacitive key C is pressed.

As described above, when a capacitive key in the key matrix is pressed in synchronization with the address signal supplied from the host computer, a key press signal is output in response to the address signal, and the key matrix Hysteresis is provided in the reaction voltage when boosting the push signal to a predetermined voltage, and this hysteresis is
By making the change using M, the key press signal is output to the host computer after sampling twice, so chattering can be prevented and the transmission time of each circuit is reduced (5ecs). The reaction time can be shortened.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to provide a capacitive keyboard that can reduce processing time.

[Brief explanation of drawings]

FIG. 2 is a signal waveform diagram showing signal waveforms of important parts. 1.2... Address decoder, 3... Key matrix, C... Capacitive key 3a, ~... Drive line, 3b1~... Sense line, 4.5...
・Analog switch, 6...Amplifier circuit, 7.8...
・FF circuit, 9... Static RAM, 10...
NAND circuit, 11 address change point detection circuit, 12...
Delay circuit, 13... Timing pulse output circuit for FF circuit control, 14... Sampling pulse output circuit, 1
5...Timing pulse output circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A key matrix in which capacitive keys are provided at the intersections of a matrix composed of a plurality of rows and columns, and rows and columns of the key matrix are selected in accordance with address signals sequentially supplied from an external device. a first output circuit that outputs a selection signal; an analog switch that outputs a change in capacitance from the key to which the selection signal was output by the first output circuit; and a voltage signal that converts the signal from the analog switch. Converted,
a sense amplifier that boosts the voltage value to a predetermined voltage when the voltage signal is equal to or higher than a first voltage value or a second voltage value; a detection circuit that detects a change in the address signal from the external device; a second output circuit that outputs a sampling pulse in response to a detection signal from the detection circuit; a third output circuit that outputs a timing pulse in response to the sampling pulse from the second output circuit; a first holding circuit that holds the output of the sense amplifier in response to a sampling pulse from the output circuit and clears it in response to a detection signal from the detection circuit; and a timing pulse from the third output circuit. When supplied, the address signal from the external device is stored in accordance with the content held by the first holding circuit, and when the same address signal as this address signal is supplied from the external device, the data is stored. a second holding circuit that holds data output from the storage circuit in response to a detection signal from the detection circuit; and a second holding circuit that holds the data held by the second holding circuit and the first Compare the data held in the holding circuit and when they match,
a fourth output circuit for outputting a key press signal to the external device; and changing the reaction voltage of the sense amplifier from the first voltage value to the second voltage value in accordance with the data supplied from the storage means. A capacitive keyboard characterized by comprising: a changing means for changing the function; and a capacitive keyboard.