JP2646118B2 - Capacitive keyboard - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a capacitive keyboard using a capacitance switch that detects a key operation by a change in capacitance.

(Prior Art) Conventionally, for example, a large number of keys are arranged in a plane, characters such as predetermined alphabets, numbers, symbols, and signs are assigned to these keys, and the key operation is performed in advance to set the keys. A so-called keyboard that transmits a coded signal corresponding to a character is known.

As a configuration of such a keyboard, a capacitive keyboard using a capacitive key having good durability and excellent key touch has been put to practical use. (Japanese Patent Laid-Open No. 59
-65348, JP-A-60-181815).

In this capacitive keyboard, a change in the capacitance between the electrodes due to a key operation is boosted to a predetermined voltage by a sense amplifier, and an ON / OFF signal of the key is obtained.

That is, the capacitance change between the electrodes due to the key operation is converted into a voltage change by a sense amplifier and amplified to a predetermined voltage,
The amplified output is output as a key press detection signal.

In such a capacitive keyboard, a key switch is controlled on a keyboard circuit board.
It is composed of a CPU (Central Processing Unit) and the like.

However, with a capacitive keyboard composed of a CPU, processing time (calculation time) is required for key detection and key address requests from the host computer.
However, there is a drawback that the processing time is long.

In particular, there is a problem when the response speed from the host computer is required.

(Problems to be Solved by the Invention) As described above, an object of the present invention is to provide a capacitive keyboard that eliminates the disadvantage that the processing time is long and that can reduce the processing time.

[Structure of the Invention] (Means for Solving the Problems) A capacitive keyboard according to the present invention has a key matrix in which capacitive keys are provided at intersections of a matrix composed of a plurality of rows and columns, and an address signal sequentially supplied from an external device. A first output circuit for outputting a selection signal for selecting a row and a column of the key matrix, and an analog for outputting a change in capacitance from a key to which the selection signal has been output by the first output circuit. A switch, a sense amplifier for converting a signal from the analog switch into a voltage signal, and boosting the voltage value to a predetermined voltage when the voltage signal is equal to or more than a first voltage value or a second voltage value; And a second output for outputting a sampling pulse in response to the detection signal from the detection circuit. A circuit, a third output circuit that outputs a timing pulse in response to a sampling pulse from the second output circuit, and an output of the sense amplifier in response to a sampling pulse from the second output circuit; A first holding circuit for clearing in response to a detection signal from the detection circuit, and when a timing pulse is supplied from the third output circuit, the external device is connected to the external device in accordance with the contents held by the first holding circuit. A storage circuit that stores an address signal from the external device and outputs data when the same address signal as the address signal is supplied from the external device;
A second holding circuit for holding data output from the storage circuit in response to a detection signal from the detection circuit;
A fourth output circuit that compares the data held by the holding circuit with the data held by the first holding circuit and outputs a key press signal to the external device when the data matches each other; And means for changing a reaction voltage of the sense amplifier from a first voltage value to a second voltage value in accordance with data supplied from the means.

(Function) In the present invention, when a key in a key matrix is depressed in synchronization with an address signal supplied from an external device, a key press signal is output in response to the address signal. Yes, a hysteresis is provided for a reaction voltage when a press signal from a key matrix is boosted to a predetermined voltage, and this hysteresis is changed using a RAM, thereby sampling the key twice and outputting the key press signal to an external device. It is like that.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a capacitive keyboard according to the present invention, in which an address decoder (first output circuit) 1,
2, key matrix 3, analog switches 4, 5, amplifier circuit (sense amplifier) 6, FF circuit for holding amplifier output (first holding circuit) 7, FF for holding data before scanning
Circuit (second holding circuit) 8, static RAM (RAM; storage circuit) 9, NAND circuit 10, address change point detection circuit (detection circuit) 11, delay circuit 12, FF circuit control timing pulse output circuit 13, sampling Pulse output circuit (second
, And a timing pulse output circuit (third output circuit) 15.

When the sampling signal is supplied from the sampling pulse output circuit 14, the address decoder 1 drives each row of the key matrix 3, that is, the drive lines 3a,. The address decoder 2 operates the analog switches 4 and 5 corresponding to each column of the key matrix 3, that is, the sense lines 3 b, in response to a lower three-digit address signal from a host computer (not shown). Turn on. The address decoders 1 and 2 are configured by, for example, TTL (LS145).

The key matrix 3 is provided with capacitive keys C,... Of which the capacitance changes with each key operation at the intersection of a plurality of rows (drive lines) 3a,... And columns (sense lines) 3b,. . The above drive line 3a, ...
Are connected to a power supply (not shown) via resistors Ra,..., And one ends of the sense lines 3b,... Are connected to a power supply (not shown) via resistors Rb,. I have.

The structure of the capacitive keys C,... Is such that a fixed electrode and a movable electrode which comes into contact with and separates from the fixed electrode by pressing down the key are provided, and one electrode is connected to a row and the other electrode is connected to a column. ing. The above capacity key C
When the button is released from the pressed state, the capacitance (key voltage) gradually decreases.

The analog switches 4 and 5 turn on the switches corresponding to the respective columns of the key matrix 3, that is, the sense lines 3 b,... According to the signal supplied from the address decoder 2. The signal from the sense lines 3b,... Is guided to the amplifier circuit 6 as shown in FIG. The analog switches 4 and 5 are, for example, CMOS
[4066 or 4051).

The amplifier circuit 6 converts the signal supplied from the analog switches 4 and 5 into a voltage signal, that is, a key press minute signal. When the key press minute signal is equal to or less than the first voltage value or equal to or less than the second voltage value. (| First voltage value |> | second voltage value |), which outputs a key press signal as shown in FIG. 2 (g) amplified to the voltage level of the logic circuit (predetermined voltage; 5V). It is. This key press signal is output to the FF circuit 7 when the sampling pulse from the sampling pulse output circuit 14 is supplied. The amplifier circuit 6 outputs a key press signal amplified to the voltage level of the logic circuit when the "0" is supplied to the terminal STB and the minute key press signal is equal to or lower than the first voltage value. When "1" is supplied to the logic circuit, the key press signal amplified to the voltage level of the logic circuit is output when the key press minute signal is equal to or less than the second voltage value. As a result, even when the capacitive key C is about to be released from the pressed state and the key voltage is reduced to cause a small voltage change (within the hysteresis voltage level), the boosted signal is output in response. Has become.

The FF circuit 7 is an FF circuit for holding an amplifier output,
The signal is cleared in response to the timing pulse from the FF circuit control timing pulse output circuit 13 and the amplifier circuit 6
2 is held as shown in FIG. 2 (h).

The FF circuit 8 is an FF circuit for holding data before one scan, and the timing pulse output circuit 13 for controlling the FF circuit.
Latched in response to a timing pulse from
Is held as shown in FIG. 2 (k). The FF circuits 7 and 8 are, for example, TTL (LS7
4) is configured.

When the timing pulse is supplied from the timing pulse output circuit 15, the RAM 9 responds to the output of the FF circuit 7, as shown in FIG. 2 (m), in the area corresponding to the address signal from the host computer. Flag "1"
When an address corresponding to the area where the flag is set, that is, the same address signal as the address signal is supplied (after one scan), a “1” signal is output to the terminal STB of the amplifier circuit 6. At the same time, the data is output to the data input terminal D of the FF circuit 8.

Instead of setting the flag, the RAM 9 may store the address as it is and compare the stored address with the same address (after one scan).

The NAND circuit 10 outputs a key press signal to a host computer (not shown) as shown in FIG. 2 (l) in accordance with the output held by the FF circuits 7 and 8. When a "1" signal is supplied from 7 and 8, a "0" signal is output as a key press signal.

This allows the host computer to operate the NAND circuit 10
When a “0” signal as a key press signal is supplied from
The pressing of the corresponding capacitive key C is determined based on the address signal output at that time.

The address change point detection circuit 11 detects a change point of an address signal supplied from a host computer (not shown). The latch circuit 16 latches the address signal. And an EOR circuit 17 for comparing with an address signal from a computer. That is, the latch circuit
When the contents of the 16 latches do not match the address signal from the host computer, a change point detection signal is output to the delay circuit 12 and the FF circuit control timing pulse output circuit 13 as shown in FIG. It is supposed to. The latch circuit 16 is connected to the sampling pulse output circuit 14
Is reset by the set output. The latch circuit 16 is composed of, for example, TTL (LS373), and the EOR circuit 17 is composed of, for example, TTL (LS266).
It is constituted by.

The delay circuit 12 outputs the change point detection signal from the address change point detection circuit 11, that is, the EOR circuit 17 as shown in FIG. 2 (d), in order to prevent noise at the time of switching by the analog switches 4 and 5. The delay signal is output to the sampling pulse output circuit 14. The delay circuit 12 includes, for example, an EOR circuit 18, resistors R1, R2, and a capacitor C1 as an inversion circuit.

The FF circuit control timing pulse output circuit 13 outputs a timing pulse as shown in FIG. 2 (i) based on a change point detection signal from the address change point detection circuit 11, that is, the EOR circuit 17. The timing pulse is output to the clock terminals of the FF circuits 7 and 8. The FF circuit control timing pulse output circuit 13 includes, for example, an EOR circuit 19 as an inverting circuit, and resistors R3 and R3.
4, and the capacitor C2.

The sampling pulse output circuit 14 includes the delay circuit
In response to the signal from the counter 12, a sampling pulse is output as shown in FIG. 2 (e). The sampling pulse is an input terminal of the timing pulse output circuit 15 and a data terminal D of the address decoder 1. , And the gate terminal of the amplifier circuit 6.

The FF circuit control timing pulse output circuit 13 and the sampling pulse output circuit 14 are connected to a pulse width adjusting capacitor Ca and a resistor Rc (pulse width adjustment with their time constants), respectively.

The timing pulse output circuit 15 outputs a timing pulse as shown in FIG. 2 (j) in accordance with the sampling pulse from the sampling pulse output circuit 14, and the timing pulse is output to the RAM 9. It is supposed to be. The sampling pulse output circuit 14 and the timing pulse output circuit 15
Is constituted by, for example, TTL (LS123).

The address signals supplied from the host computer may be supplied in order or may be supplied at random.

Next, the operation in such a configuration will be described. For example, a case where a key corresponding to the A address (key A) is pressed as the capacitive key C will be described.
That is, the key A is pressed as shown in FIG. 2 (b), and the A address is changed from the host computer (not shown) to the address decoders 1, 2, the RAM 9, and the address change as shown in FIG. 2 (a). It is supplied to the point detection circuit 11. Then, the address change point detection circuit 11, that is, EOR
The circuit 17 outputs an address transition point detection signal to the delay circuit 12 as shown in FIG. As a result, the delay circuit 12 outputs a signal as shown in FIG. Then, a sampling pulse as shown in FIG. 3E is output from the sampling pulse output circuit 14 to the gate terminal of the amplifier circuit 6 and the data terminal D of the address decoder 1. Thus, in accordance with the address, the address decoder 1 outputs a drive signal from a predetermined drive line 3a, and the address decoder 2 turns on the analog switch 4 or 5 corresponding to the predetermined sense line 3b.

Then, when the key A is pressed, the analog switch 4
Alternatively, the key press minute signal as shown in FIG. The terminal STB of the amplifier circuit 6 is supplied with a “0” signal from the RAM 9.

The address change point detection signal from the EOR circuit 17 is output to the FF circuit control timing pulse output circuit 13. As a result, the FF circuit control timing pulse output circuit 13 outputs a timing pulse (reset output) as shown in FIG. Therefore, the FF circuit 7 is cleared.

As a result, when the key press signal is equal to or lower than the first voltage value, the amplifier circuit 6 outputs a signal as shown in FIG. Then, the FF circuit 7 is set, and the set output “1” is output to the NAND circuit 10 and the data terminal Di of the RAM 9.
Output to n. At this time, the FF circuit 8 remains in the reset state, and its set output is “0”. For this reason, data is not output from the NAND circuit 10.

When the sampling pulse from the sampling pulse output circuit 14 rises, the timing pulse output circuit 15 outputs a (write) timing pulse as shown in FIG. As a result, the RAM 9 sets a flag in the area corresponding to the address from the host computer.

Next, when another address is supplied from the host computer, the address change point detection circuit 11, that is, the EOR
The circuit 17 outputs an address transition point detection signal to the delay circuit 12 as shown in FIG. As a result, the delay circuit 12 outputs a signal as shown in FIG. Then, a sampling pulse as shown in FIG. 3E is output from the sampling pulse output circuit 14 to the gate terminal of the amplifier circuit 6 and the address decoder 1.

In this case, since the key A is pressed, a small key press signal is sent from the analog switch 4 or 5 to the amplifier circuit 6.
Is not output to

Further, the FF circuit control timing pulse output circuit 13 outputs a timing pulse to the FF circuit 7 in response to the address change point detection signal from the EOR circuit 17. This allows FF
Circuit 7 is cleared. Therefore, no data is output from the NAND circuit 10.

Thereafter, each time a different address is supplied, the same operation as described above is performed, and no data is output from the NAND circuit 10.

When one scan is performed and the A address is supplied again from the host computer, the A address is output to the address decoders 1, 2, the RAM 9, and the address change point detection circuit 11. As a result, the RAM 9 is supplied with the address corresponding to the area where the flag is set,
The "1" signal from the data terminal Dout (see FIG. 3 (m)) is supplied to the terminal STB of the amplifier circuit 6 and the data terminal D of the FF circuit 8.
Output to

Further, an address transition point detection circuit 11, that is, an EOR circuit 17, outputs an address transition point detection signal to the delay circuit 12, as shown in FIG. As a result, the delay circuit 12 outputs a signal as shown in FIG. Then, the sampling pulse output circuit
From 14 the sampling pulse as shown in FIG.
The signal is output to the gate terminal of the amplifier circuit 6.

When the key A is pressed, the analog switch 4 or 5 outputs a small key-press signal to the amplifier circuit 6 as shown in FIG. Further, the terminal STB of the amplifier circuit 6 is supplied with a “1” signal from the RAM 9.

The address change point detection signal from the EOR circuit 17 is output to the FF circuit control timing pulse output circuit 13. As a result, the FF circuit control timing pulse output circuit 13 outputs a timing pulse as shown in FIG. Therefore, the FF circuit 8 is set, and the set output "1" is output to the NAND circuit 10.

As a result, when the key press signal is equal to or lower than the second voltage value, the amplifier circuit 6 outputs a signal as shown in FIG. Then, the FF circuit 7 is set, and the set output “1” is output to the NAND circuit 10. Therefore, a key press signal ("0" signal) is output from the NAND circuit 10 and supplied to the host computer as shown in FIG.

This allows the host computer to operate the NAND circuit 10
When a “0” signal as a key press signal is supplied from
The depression of the corresponding capacitive key C is determined based on the address signal (A address) output at that time.

As described above, when a capacitive key in the key matrix is pressed in synchronization with an address signal supplied from the host computer, a key press signal is output in accordance with the address signal, and further, the key matrix is output from the key matrix. A hysteresis is provided for the reaction voltage when boosting the press signal to a predetermined voltage, and this hysteresis is set to RA
By changing using M, the key press signal is output to the host computer after sampling twice, so that chattering can be prevented, and the reaction can be performed only in the transmission time of each circuit (several tens of microseconds). And the processing time can be shortened.

[Effects of the Invention] As described in detail above, according to the present invention, it is possible to provide a capacitive keyboard capable of reducing processing time.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention. FIG. 1 is an electric circuit diagram schematically showing the entire structure, and FIG. 2 is a signal waveform diagram showing signal waveforms of main parts. 1, 2... Address decoder, 3.
C: Capacitive key, 3a, ... Drive line, 3b, ... Sense line, 4, 5 Analog switch, 6 Amplifier circuit, 7, 8 FF circuit, 9 Static RAM, 10: NAND circuit, 11 address change point detection circuit, 12: delay circuit, 13: timing pulse output circuit for controlling FF circuit, 14: sampling pulse output circuit, 15: timing pulse output circuit.

Claims (1)

(57) [Claims] 1. A key matrix in which a capacity key is provided at an intersection of a matrix composed of a plurality of rows and columns, and a selection for selecting a row and a column of the key matrix according to an address signal sequentially supplied from an external device. A first output circuit that outputs a signal; an analog switch that outputs a change in capacitance from a key to which a selection signal is output by the first output circuit; and a signal from the analog switch that is converted into a voltage signal. And
When the voltage signal is equal to or higher than the first voltage value or the second voltage value, a sense amplifier that boosts the voltage value to a predetermined voltage, a detection circuit that detects a change in an address signal from the external device, A second output circuit that outputs a sampling pulse in response to a detection signal from the detection circuit, a third output circuit that outputs a timing pulse in response to a sampling pulse from the second output circuit, A first holding circuit that holds the output of the sense amplifier in response to a sampling pulse from the output circuit and clears the output in response to a detection signal from the detection circuit; and a timing pulse from the third output circuit. When supplied, an address signal from the external device is stored in accordance with the content held in the first holding circuit, and the same address signal as the address signal is stored in the first holding circuit. A storage circuit that outputs data when supplied from an external device; a second storage circuit that stores data output from the storage circuit in response to a detection signal from the detection circuit; The data held by the circuit is compared with the data held by the first holding circuit.
A fourth output circuit for outputting a key press signal to the external device; and changing a reaction voltage of the sense amplifier from a first voltage value to a second voltage value according to data supplied from the storage means. A capacitive keyboard comprising: