JPH0287647A - Method of designing integrated circuit device - Google Patents

Abstract

PURPOSE:To easily specify a truly erroneous part during inspection by comparing a layout with a circuit diagram by a method wherein a circuit diagram inside a functional block is changed on the basis of the number of equipotential terminals of a functional block computed from a relative arrangement position of the functional block and a one-to-one correspondence of terminals between the layout and the circuit diagram is guaranteed. CONSTITUTION:At an arrangement processing part 11, a relative arrangement position of a functional block inside an integrated circuit device is decided; at an equipotential terminal number computation part 12, the number of equipotential terminals with reference to individual signal lines between functional blocks is computed; at an equipotential terminal and net information addition part 13, equipotential terminals covering the number computed in the 12 and net information are added to circuit diagrams inside the individual functional blocks. When three functional blocks 21, 22, 23 are situated in relative arrangement positions and request that the 21, 22, 23 should be connected regarding a signal line, an equipotential terminal 26 and a net 28 are added to a net 27 which connects a fundamental block 24 in a circuit diagram inside the functional block 22 to a terminal 25.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for designing an integrated circuit device, and particularly to a method for designing a hierarchical layout.

[Conventional technology]

Conventionally, in the design method of this type of integrated circuit device, equipotential terminals as many as expected to be used when laying out the functional block are provided in advance in the circuit diagram in the functional block, or the circuit diagram in the functional block is In the figure, no equipotential terminals were provided, but a mask pattern was added to serve as equipotential terminals during layout design.

[Problem to be solved by the invention]

In the conventional integrated circuit device design method described above, the number of terminals is fixed when designing the circuit diagram in a functional block.
There may be equipotential terminals that are not used during layout design, or one terminal on the circuit diagram may be represented as multiple equipotential terminals on the layout, and when verifying by comparing the layout and the circuit diagram, the true The disadvantage is that it is difficult to identify the location of the fraud.

[Means to solve the problem]

The integrated circuit device design method of the present invention is a procedure for adding equipotential terminals and net information to a circuit diagram in a functional block based on equipotential terminals of a functional block calculated from the relative arrangement positions of functional blocks in an integrated circuit device. have.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a flowchart showing the basics of the design method according to the present invention. In placement processing 11, the relative placement positions of functional blocks within the integrated circuit device are determined, and the number of equipotential terminals is calculated 12.
The number of equipotential terminals for each signal line between functional blocks is calculated in 13, and equipotential terminals and net information calculated in 12 are added to the circuit diagram in each functional block in 13.

FIG. 2 is a diagram of one embodiment of the present invention. If the three functional blocks 21, 22, and 23 are located in relative positions as shown in Figure 2, and there is a request to connect 21, 22, and 23 for a certain signal line, the functional block 22 has two equipotential terminals. It is more advantageous in terms of layout to provide 25°26. For this reason, an equipotential terminal 26 and a net 28 are added to the net 27 connecting the basic block 24 and the terminal 25 in the circuit diagram in the functional block 22.

FIG. 3 is a diagram of another embodiment of the invention. If three functional blocks 31, 32, and 33 are located in relative positions as shown in FIG. It is more advantageous in terms of layout to provide the signal line 35 and pass the signal line through it. Therefore, function block 3
A net 36 is added to connect terminals 34.35 and 34.35, which did not originally exist in the circuit diagram in 2.

In this embodiment, the signals passing through the functional blocks are explicitly added to the circuit diagram, so it is easy to create mask patterns for the passing signal lines described in the circuit diagram when laying out the inside of the functional blocks. It has the advantage of being possible.

〔Effect of the invention〕

As explained above, the present invention changes the circuit diagram in the functional block based on the number of equipotential terminals of the functional block calculated from the relative placement position of the functional block, and makes one-to-one correspondence between the terminals in the layout and the circuit diagram. By guaranteeing that the number of terminals described in the circuit diagram is easily identified when comparing and verifying the layout and circuit diagram, it is also possible to easily identify true irregularities when performing verification by comparing the layout and circuit diagram. This has the effect that a mask pattern can be created faithfully according to the number of nets.

[Brief explanation of drawings]

FIG. 1 is a flowchart showing the basics of the design method of the invention, FIG. 2 is a diagram showing one embodiment of the invention, and FIG. 3 is a diagram showing another embodiment of the invention. 21, 22.23.31.32.33... Functional block, 24... Basic block within functional block, 25.26, 34.35... Equipotential terminal ,2
7゜28, 36...net. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In the hierarchical layout design of an integrated circuit device, a procedure for adding equipotential terminals and net information to the circuit diagram in a functional block based on the number of equipotential terminals of the functional block calculated from the relative placement positions of the functional blocks in the integrated circuit device. 1. A method for designing an integrated circuit device, comprising: