JPH0286327A - Frequency divider - Google Patents

Abstract

PURPOSE:To apply variable frequency division and timing control to an input signal and to obtain an output signal of a desired frequency by switching the frequency division ratio of a variable frequency division means in response to an output of an arithmetic means and obtaining an output signal from the correction means. CONSTITUTION:When a period of a desired output signal is 3.7 times that of an input signal, a correction means 7 uses a clock pulse having a frequency 10 times that of an FG signal SFG to apply the timing correction. A variable frequency division means 5 applies frequency division ratio switching of 3 and 4 and the timing is corrected by the correction means 7 to obtain a PG signal SPG' with a desired frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frequency dividing device that divides an input signal into a desired frequency.

Conventional technology In capstan servo in magnetic recording and reproducing devices, a frequency generator (hereinafter referred to as FG) is used to detect the rotational speed of a gear capstan motor in order to implement phase servo during recording.
The output (hereinafter referred to as FG multiplied signal) is frequency-divided by a frequency divider and used. This frequency divided output is commonly called a PG multiplied signal.

FIG. 3 shows a block diagram of this conventional frequency dividing device. In FIG. 3, 1 is an input terminal, 2 is a frequency dividing means, and the input signal (FG signal fSFG) input from input terminal 1 is
). 3 is an output signal (
This is an output terminal that outputs a PG signal (5PG).

The operation of the frequency dividing device configured as described above will be explained below.

FIG. 4 is an operation waveform diagram showing a first example of operation of the frequency dividing means 2. In FIG. The FG multiplied signal FG shown in waveform A in FIG. 4 is inputted and frequency-divided by 1/N as shown in waveform B, and the frequency-divided output shown in waveform C can be obtained as the PG multiplied signal PG. Here, the operating waveform shown in waveform B uses an up counter as a frequency division counter, and performs frequency division by repeatedly counting the count value from 0 to N'' (N=6 on the school side). In other words, the up counter changes from 0 to 1 at the rising edge (falling edge is also acceptable) of the FG multiplied signal FG of waveform A.
．． Count up as 2, 3, 4.5, decode the count value corresponding to the frequency division ratio N, and generate the PG signal 5PGN of waveform CN.
get. Then, with this PG signal 5PGN, the FCi signal S
The falling edge of FG is detected and the rising counter is reset by the detection signal.

However, the up counter counts from 0 to N again,
By repeating the same operation thereafter, 1) 17H frequency division can be achieved. Note that the waveform C1 is a PG signal 5PG1 obtained by decoding the count value 1 of the up counter, and it is possible to obtain a decoded output with a count value from 0 to N as long as it is within the count range of the counter.

Next, FIG. 5 is an operation waveform diagram showing a second example of operation of the frequency dividing means 2. In FIG. The difference from the first operation example is that a down counter is used as a frequency dividing counter. Therefore, in this case, a value corresponding to the frequency division ratio N is preset in the down counter, the count is down-counted from 5 to 0, and the count value 0 is decoded to obtain the PG signal 5PG0 shown in the waveform C0. Then, the falling edge of the FG multiplied signal FG is detected using this PG signal 5PGo, and the down counter is preset with this detection signal.

However, the down counter counts from 6 to 0 again,
Thereafter, by repeating the same operation, the frequency can be divided by 1/N. Note that the waveform C1 is the PG signal 5PG1 obtained by decoding the count value 1, and as in the first operation example, a decoded output within the count range can be obtained.

It should be noted that the operation of the frequency dividing means 2 described above is only one example, and it goes without saying that various configurations are possible.

Problems to be Solved by the Invention However, in the above configuration, as shown in FIGS. 4 and 6, the time t0. Frequency division at t2 is possible, but at time t
0. Division at t1 is not possible.

That is, in the conventional frequency divider, the frequency division ratio N for dividing the input signal is
There was a problem that could only be set to a positive integer.

Therefore, in the capstan servo device, the FG signal SF
If you want to obtain a signal with a frame frequency of 3oHz of the vertical synchronization signal, for example, if you want to obtain a signal with a frame frequency of 3oHz of the vertical synchronization signal, the frequency of the FG multiplied signal FG is divided from the PG multiplied signal P.
It was necessary to set the frequency to be an integral multiple of the frequency of G. For this reason, the capstan shaft diameter of the capstan motor and the number of teeth of the FG are restricted, which poses a bottleneck in design.

Generally, the tape speed vt when directly driving a magnetic tape with a capstan motor is calculated by the following equation.

Here, π is pi, D is the diameter of the capstan shaft, N is the frequency division ratio, fPG is the frequency of the PG flaw signal PG, and Z is FG.
is the number of teeth.

In equation (1), vt takes a specific value based on the tape format of the magnetic recording/reproducing device. Therefore, PG double signal PG
If the frequency fPG of is also specified as 5oHz, (
2) It is necessary to set N and Z so that the value obtained by dividing the product of D and N by Z becomes constant as shown in the formula.

Normally, it is more economical to use a standard product for the capstan shaft, but since N and Z are limited to integers, it is necessary to use one with special dimensions in some cases. However, if you absolutely must use a standard product, then
The G frequency fPG must be set to a frequency different from 30 Hz. In this case, the frame frequency vertical synchronization signal cannot be used as a phase servo reference signal. Therefore, there is no choice but to generate and use an internal reference signal using a reference signal generator.

As is clear from the above description, the conventional frequency dividing device can only divide the frequency by a positive integer, which has many restrictions on the design of, for example, a capstan servo device.

The present invention solves the above problems, and aims to provide a frequency dividing device that can obtain a PG multiplied signal PG of a desired frequency from an FG multiplied signal FG without being subject to various restrictions. It is something.

Means for Solving the Problems To achieve this object, the frequency dividing device of the present invention includes variable frequency dividing means for variably dividing an input signal, and arithmetic means for performing calculations in synchronization with the output of the variable frequency dividing means. and a correction means for correcting the timing of the output of the variable frequency division means according to the output of the calculation means, and the frequency division ratio of the variable frequency division means is switched according to the output of the calculation means, and the output signal is adjusted by the correction means. It has a configuration designed to obtain.

Effect: With the above-described configuration, the present invention can change the frequency division ratio of the variable frequency division means according to the calculation output obtained by the calculation means, and can correct the timing of the output of the variable frequency division means by controlling the correction means. Therefore, an output signal obtained by dividing the input signal to a desired frequency can be obtained.

As a result, in the capstan servo device, the constants vt, D, fPG, and Z in equation (1) can be set to arbitrary values, and the capstan servo device is not subject to design restrictions. do not have.

EXAMPLE An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of a frequency dividing device in one embodiment of the present invention. In Fig. 1, 4 is an input terminal;
Reference numeral 6 denotes variable frequency dividing means, which variably divides the frequency of the input signal (FG signal 5FG) inputted from the input terminal 4. 6 is an arithmetic means which outputs the output signal (PG signal 5P) which is the output of the variable frequency dividing means 6.
Calculation is performed in synchronization with G). Reference numeral 7 denotes a correction means for correcting the timing of the output signal of the variable frequency dividing means 6. and,
Switching of the frequency division ratio by the variable frequency dividing means 5 and timing correction by the correcting means 7 are performed in accordance with the calculation output Sx of the calculation means 6. Reference numeral 8 denotes an output terminal, from which an output signal of a desired frequency (PG doubler SPG/) is obtained from the output of the correction means 7.

Regarding the frequency dividing device of this embodiment configured as above,
The operation will be explained below.

FIG. 2 is an operational waveform diagram showing an example of the operation of the frequency dividing device of this embodiment. Here, the variable frequency dividing means 5 shows an example in which an up counter is used as a frequency dividing counter, and the desired output signal (PG double signal SPG') has a cycle of the input signal (FG double signal F
An example is shown in which the value is 3.7 times that of G). Further, an example will be shown in which the correction means 7 sets the fineness of correction to the period of the FG multiplied signal FG. Therefore, the correcting means 7 only needs to correct the timing using a clock pulse having a frequency ten times that of the FG multiplied signal FG, and this can be easily realized using a digital delay circuit. In addition, the times t0 to t1□ shown in the figure are FG times the signal FG.
The period is 3.7 times that of .

In Fig. 2, waveform A is the FG times signal FG, and waveform B is
The frequency dividing operation of the variable frequency dividing means 6 is represented by waveform CN.

C1 is the output (PG signal 5PGN, 5PG1) obtained by decoding the count value N, 1 of the variable frequency dividing means 6, the waveform is the correction amount by the correction means 7, the waveform ED, EU is the subtraction by the calculation means 6, The calculation operation of addition is shown in the waveform FD.

FU is the calculation output S of the calculation means 6 in the variable frequency dividing means 6.
The waveform G is the output obtained by comparing the magnitude of x with a predetermined value, and the waveform H is the output obtained by latching the magnitude comparison output in the variable frequency dividing means 5 at the falling edge of the PG signal 5PGN.
An output signal (PG doubler SPG') in which the timing of the rising edge of signal 5PGN is corrected by calculation output Sx is shown.

Now, the desired period of PG double signal SPG' is FG double signal F
Since it is 3.7 times the period of G, there is a difference of +0.7 compared to the integer frequency division of 4, -0, 3, and 3.

Therefore, by simply dividing the frequency by an integer, the desired PG doubler SP
Minus (delay) or plus (
In the end, the desired P
It is not possible to obtain G double credit SPG'.

Therefore, the present invention switches the frequency dividing ratio between 3 and 4 using the variable frequency dividing means 5, obtains a frequency divided output earlier than each time to-t12, and corrects the timing of this using the correcting means 7. The purpose is to obtain a PG doubler SPG' of a desired frequency, and switching of the frequency division ratio and timing correction are performed in accordance with the calculation output Sx of the calculation means 6.

For convenience of explanation, time t0 is FG times signal F.

The explanation will be given assuming that it coincides with the rise of . Actually, it does not matter what time it starts, and it is determined by the calculation output Sx. The calculation output SX at time t0 is 0.

Two examples have been shown in which the calculation means 6 performs subtraction (waveform Ep) and addition (waveform EU), but either one may be used. Since the correction means 7 sets the fineness of correction to the period of the FG doubler SFG, it is sufficient to perform correction in 19 ways.

Therefore, the calculation means 6 only needs to be able to output 10 values from 9 to 0 or from 0 to 9, which correspond to the subtraction and addition shown in the waveforms ED and EU. Here, the edge differences -0, 3 and +0.7 are -3 and +7 if they are made to correspond to the number of clock pulses.

As you can see from the waveform diagram, t0~11.13~14.16
The frequency is divided by 3 between ~17,11°~t11, and t1~t
2゜t2~t3・t4~t6・t6~kai6・tγ~t8
If the frequency is divided by 4 between t8 and t9 and t9 and t1° and t11 and t12, the frequency divided output 5PGN (waveform ON) can be obtained earlier than each time t1 to t12. At this time, the difference between the rise of the frequency divided output 5PGN and each time is t0
~0, 7, 4, 1.8, 5, 2, 9 at t12, respectively
゜6.3,0,7,4. Therefore, if this value is used as a correction value, the PG doubler SP at the desired timing can be
G' can be obtained. The waveform shows the amount of correction, and each correction value is the value obtained by subtracting 3 from the previous value or 1.
The value is 7 added to the previous value. This corresponds to the above-described difference of -3 or +7. The value obtained by this calculation is the calculation output Sx shown in the waveforms Ep and EU. Here, the calculation by the calculation means 6 is performed after each time.
This can be done before the next correction starts.

On the district side, the PG signal 5PG1 shown in the waveform C1 may be used, and calculations may be performed in synchronization with the rising edge of this signal.

On the other hand, the frequency dividing ratio in the variable frequency dividing means 6 may be changed according to the calculation output Sx.

That is, this may be done by dividing the frequency by 4 when the previous calculation output Sx (ie, correction value) is 3 or more, and by dividing by 3 when it is less than 3. Therefore, this means that the calculation output Sx is set to a predetermined value (3 in this case).
This magnitude comparison output (waveform FD
, FU) to PG double trust S,. , (waveform CN) (that is, the end point of frequency division), and switch using the latch output (waveform G). On the other hand, when the latch output shown in waveform G is low, the frequency division ratio is N=s, and when it is high, the frequency division ratio is N=4. Here, the predetermined value 3 used for the magnitude comparison corresponds to the above-mentioned difference -3. This means that if the previous correction value is less than 3, the next correction value is 7 or more.
This indicates that the next frequency division ratio will become smaller. This is a case where the absolute value 3 of the difference -3 is used as the standard for size comparison. When using the absolute value 7 of the difference +7, the current correction value (calculation output Sx) may be used. In this case, it is sufficient to perform a magnitude comparison with respect to 7, and if it is 7 or more, divide the frequency by 3, and if it is less than 7, divide the frequency by 4. The magnitude comparison output may be latched, created, and used between the end of the calculation and just before the divided output 5PGN is obtained. For example, it is latched at the falling edge of the divided output 5PG1. By doing as described above, the frequency division ratio of the variable frequency dividing means 6 can be switched according to the calculation output Sx.

As described above, the calculation means 6 performs calculations in synchronization with the frequency division output SPG of the variable frequency division means 6, and the frequency division ratio of the variable frequency division means 6 is switched according to the calculation output Sx, and the correction means 7 The timing of the frequency-divided output SPG is corrected. and,
A desired frequency divided output (PG doubler SPG') shown in waveform H can be obtained from the correction means 7.

In addition, in the above explanation, the frequency division output 5PG of the variable frequency division means 6
Although the case where the timing of the rise of N is corrected and the calculation is performed in synchronization with the rise of the divided output 5PG1 has been shown, the present invention is not limited to this, and may be freely modified within the scope of the gist of the present invention. It is.

In addition, when the calculating means e is configured as a hardware, pulses of a number equal to the value to be calculated (3 or 7) are used as clock pulses, and a down counter is used for subtraction, and an up counter is used for addition. The waveforms E p and EU show exactly this situation. In the case of software configuration, it is possible to execute a subtraction or addition program using a microcomputer. Furthermore, in terms of hardware, RO
M (read-only memory) can also be used. In this case, the pre-calculated correction value is written in the ROM, and the frequency division output SPG of the variable frequency division means 5 is stored in the ROM.
It is necessary to form and use an address signal for this purpose.

Generally, the FG double signal FG, the PG double signal SPG' of a desired frequency, and the clock pulse are given in terms of frequencies, so the concept will be explained as fFG=fPG' and fCK, respectively.

(1) First, find the magnification G f FG/f PG' of the frequency fFG of the FG double signal with respect to the frequency fPG' of the PG doubler SPG'. This is 3.7 times the above value.

(2) Find the integer value N when fFG/fPG' is rounded up and the distortion value N2 when rounded down. This is the frequency division ratio in the variable frequency division means 6, and if it corresponds to the above value, N = 4. N2=3(N,=N2+1
).

(3) N1. The difference obtained by subtracting fFG/fPG' from N2 is multiplied by the multiplication factor fCY,/fFG of the frequency fCK of the clock pulse/L/S with respect to the frequency fFG of the FG multiplied signal PG to obtain the difference M-27 converted into the number of clock pulses. demand. ”=CfFG/fPG”1)×fCK/fF
G=””=(fFG/7PG'-N2)×fCK/f
If it is FG, then if it corresponds to the above values, M-=-3, M
”=+7.

Note that the clock pulse is used by the correction means 7 for timing correction.

From the above, the variable frequency dividing means 5 sets the frequency division ratios to N1 and N1.
2, and the arithmetic means 6 performs either M- or M+ arithmetic (subtraction, addition, or addition).

In the above operation description, an example is shown in which an up counter is used as the variable frequency dividing means 5, but a down counter may also be used. Effects of the Invention As described above, the present invention provides variable frequency dividing means for variably dividing an input signal, and calculation in synchronization with the output of the variable frequency dividing means. and a correction means that corrects the timing of the output of the variable frequency division means according to the output of the calculation means, and the correction means switches the frequency division ratio of the variable frequency division means according to the output of the calculation means. Since the configuration is such that an output signal can be obtained more easily, it is possible to realize a frequency dividing device that can obtain an output signal of a desired frequency by variable frequency division and timing correction of an input signal. and,
If the frequency dividing device of the present invention is applied to, for example, a capstan servo device, it is possible to design a device that ignores the conventional constraints such as the capstan shaft diameter and the number of FG teeth (2). 2 can be set freely, which has great practical effects.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram of a frequency dividing device in an embodiment of the present invention, FIG. 2 is an operation waveform diagram showing an example of the operation of the embodiment, and FIG.
The figure is a block diagram of a conventional frequency dividing device, and FIGS. 4 and 6 are a block diagram of a conventional frequency dividing device. FIG. 7 is an operation waveform diagram showing a second operation example. 5...Variable frequency dividing means, 6...Calculating means, 7...Correction means. Name of agent: Patent attorney Shigetaka Awano and one other person

Claims (1)

[Claims] variable frequency dividing means for variably frequency-dividing an input signal; arithmetic means for calculating in synchronization with the output of the variable frequency dividing means; and correcting the timing of the output of the variable frequency dividing means in accordance with the output of the arithmetic means. 1. A frequency dividing device, comprising: a correction means, and configured to switch the frequency division ratio of the variable frequency division means according to the output of the calculation means and obtain an output signal from the correction means.