JPH0286193A - Manufacture of thin film multilayer circuit board - Google Patents

Abstract

PURPOSE:To prevent a step from forming between the surfaces of insulating layers and those of conductor layers and facilitate soldering by forming conductor layer patterns by embedding recessions formed beforehand on the conductor layer pattern forming scheduled areas of the insulating layers. CONSTITUTION:Openings are formed on the conductor via holes 23 of a ceramic substrate 22 having conductor patterns 21 formed therewithin. A conductor layer 26 is formed on a first insulating layer 24 having openings made therein and a copper plating layers 28 are formed in the openings with a resist pattern 27 used as a mask. In this structure, the copper plating layers 28 acting as circuit patterns are buried in the first insulating layer 24. A conductor layer 29 is formed on the substrate 22. The conductor layers 26 and 29 are removed by etching with resist films 31 of the specific pattern, which are formed on the plating layers 28 of the substrate, used as a mask. A second insulating layer 34 having conductor via holes 33 formed therein is formed on circuit patterns 32 having the copper plating layers 28, the peripheries of which are covered by the conductor layers 26 and 29, on the substrate. And then a third insulating layer 35 embedded with the circuit patterns 32 is formed on the second insulating layer 34. Thereby no step is produced between the surfaces of the insulating layers 24 and 35 and those of the circuit patterns 32.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing a thin film multilayer circuit board, a conductor layer pattern formed on an insulating layer formed in multiple layers for forming a thin film multilayer circuit board is used to form a conductive layer pattern on the surface of the insulating layer. Manufacturing of circuit boards in which conductor layer patterns formed on multiple insulating layers on a board are connected by conductor via holes in order to prevent the formation of steps between the surfaces of the conductor layers. In this method, a recess is formed in advance in a region of the insulating layer where a conductor layer pattern is to be formed, and a conductor layer pattern is embedded in the recess.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film multilayer circuit board.

Thin-film multilayer circuit boards are used as printed wiring boards with improved dielectric strength and on which electronic components that consume large amounts of power are mounted.

Such a thin film multilayer circuit board is formed by laminating multiple insulating layers having conductor via holes on a ceramic substrate, and forming a conductor layer pattern connected to the conductor via holes on the insulation layer. The layer pattern creates a level difference between the conductor layer surface and the insulating layer surface, making the surface of the formed thin film multilayer circuit board uneven, which hinders work such as soldering of electronic components mounted on the board. Therefore, it is desirable to eliminate the level difference between the surface of the insulating layer and the surface of the conductive layer pattern.

[Conventional technology]

To explain the conventional manufacturing method of thin film multilayer circuit boards, holes are punched into a green sheet in a predetermined pattern, and after filling the punched areas with conductive paste,
After forming a conductive paste in a predetermined pattern on the sheet, it is laminated and then fired to form a ceramic substrate 3 with conductor via holes 2 formed on the conductor layer pattern 1, as shown in FIG. 3(a). Form. Next, chromium (Cr) is deposited on this substrate 3 by a sputtering method or a mowing method.
A conductor layer 4 having a two-layer structure of copper (Cu) layers is formed.

Next, as shown in FIG. 3(b), a photoresist film 101 is formed.
Using as a mask, a copper plating layer 5A having a predetermined pattern is formed to a thickness of about 20 μm by the electroplating method, and then the resist film 101 is removed.

Next, the conductor layer 4 is etched away using the patterned copper foil N5A as a mask.

Next, as shown in FIG. 3(C), chromium (
After forming the chromium layer 5B to a thickness of about 1,500 by vapor deposition, the chromium layer was formed into a predetermined pattern by etching using a resist film (not shown), as shown in FIG.
As shown in d), the conductor layer 4. A first conductor layer pattern 5 having a three-layer structure consisting of a copper coating layer 5A and a Cr layer 5B is formed.

Next, a first insulating layer 6 made of a photosensitive polyimide film is formed on the substrate, the first insulation layer 8 is exposed to light using a mask in a predetermined pattern, and the unexposed portions are etched to form the first conductive layer pattern. An insulating layer via pole 7 is formed on the insulating layer via pole 5.

Next, a conductor layer 8 having a two-layer structure made of Cr and copper (Cu) is formed on the first insulating layer 6 by sputtering, and the aforementioned conductor 8 is also formed in the insulating layer via hole 9 to form a conductor via hole 9. do.

Next, as shown in FIG. 3(e) using a resist film (not shown) as a mask, a conductor layer pattern 8A made of Cu is formed on the conductor via pole 9 by a plating method, and then the first conductor layer pattern 5 is Conductor layer 8. A second conductor layer pattern 10 consisting of a copper plating layer 8A and a Cr vapor deposition layer 8B is formed.

Next, as shown in FIG. 3(f), a second photosensitive polyimide film is formed on the substrate including the second conductor layer pattern 10.
After forming the insulating layer 11, it is exposed to light in a predetermined pattern using a mask, and the unexposed portions are etched to form the second insulating layer via hole 12.

Next, a conductor layer 13 made of Cr and Cu layers is formed on the second insulating layer 11.

Next, as shown in FIG. 3(A), after forming a third conductor layer pattern 14 in the same manner as in the formation of the first conductor layer pattern 5 and the second conductor layer pattern 10, a third insulating layer pattern 14 is formed. 15, a third insulating layer via hole 16 is further formed, and the third insulating layer via hole 16 is further changed into a conductor via hole by the method described above, and the method described above is repeated to form a thin film multilayer circuit board. There is.

[Problem to be solved by the invention]

However, in the conventional method described above, the surfaces of the first conductor layer pattern 5 and the ceramic substrate 3, the surface of the second conductor layer pattern 10 and the surface of the first insulating layer 6, and the surface of the third conductor layer pattern 14, There is a step between the second insulating layer 11 and the surface of the second insulating layer 11, and this step is formed by each conductor layer pattern 5.10.
In order to reduce the conductor resistance by increasing the thickness of 14 from the current thickness of 20 μm to 50 μm, the thickness of the insulating layer must be approximately 200 μm.
As a result, steps are increasingly formed, making it difficult to flatten the surface of the multilayer thin film circuit board to be formed. Furthermore, in order to eliminate the level difference between the conductor layer pattern and the insulating layer, if an attempt is made to form the insulating layer thickly to achieve planarization, it is necessary to form the insulating layer very thickly.

When such a difference in level occurs, as the insulating layer is multilayered, the surface of the insulating layer becomes uneven, and there is a problem that a conductor layer pattern formed on the insulating layer cannot be formed with high precision.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to provide a method for manufacturing a thin film multilayer circuit board in which a step is not generated between the surface of a conductor layer pattern and the surface of an insulating layer.

[Means to solve the problem]

The thin-film multilayer circuit board of the present invention that achieves the above object is characterized in that, in the production of a circuit board in which conductor layer patterns formed in multiple layers on a board are connected to each other through conductor via holes, the above-mentioned insulation It is constructed by forming a recess in advance in a region of the layer where a conductor layer pattern is to be formed, and embedding the conductor layer pattern in the recess.

[For production]

In the method of the present invention, a recess is formed in advance in the region of the insulating layer where the conductor layer pattern is to be formed, and the conductor layer pattern is buried in the recess so that the surface of the conductor layer pattern and the surface of the insulating layer are aligned. , Avoid creating a step difference between the conductor layer pattern and the surface of the insulating layer.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

As shown in FIG. 1(a), a first insulating layer 24 made of a photosensitive polyimide film is formed on a ceramic substrate 22 in which a conductive pattern 21 and a conductive via hole 23 are formed, and then a first insulating layer 24 made of a photosensitive polyimide film is formed using a mask exposure method. After exposure, the unexposed portion is etched to form an opening 25 above the conductor via hole 23.

Next, as shown in FIG. 1(b), a conductor layer 26 made of chromium (Cr) and copper (Cu) is formed on the first insulating layer 24 in which the opening 25 is provided.

Next, as shown in FIG. 1(C), the opening 25 described above is opened.
A resist pattern 27 serving as a plating mask is formed on the substrate except for the plating.

Next, as shown in FIG. 1(d), a copper plating layer 28 is formed in the opening 25 by electrolytic plating using the resist pattern 27 as a mask.

Next, as shown in FIG. 1(e), the resist pattern 27 is removed.

In this way, the copper plating layer 28 serving as a circuit pattern is embedded in the first insulating layer 24.

Next, as shown in FIG. 1(f), a conductor layer 29 made of chromium (Cr) is formed on the substrate 22 by sputtering or the like, and is bonded to an interlayer insulating layer to be formed on the substrate in a later step. Try to increase the level.

Next, as shown in Fig. 1, the plating layer 2 of the substrate is
A resist film 31 having a predetermined pattern is formed on the resist film 8 .

Next, as shown in FIG. 1(h), the resist 1 pattern 31
The conductor layers 26 and 29 are removed by etching using the mask as a mask.

Next, as shown in FIG. 1(i), the resist film 31 is removed.

Next, as shown in FIG. 1(j), the circuit pattern 32 in which the periphery of the copper plating layer 28 on the board is covered with conductor N26. A second insulating layer 34 made of a photosensitive polyimide film in which a conductor via hole 33 is formed is formed by using the method of steps up to ) excluding only the step shown in FIG. 1(f).

Next, a circuit pattern 32 in which the periphery of the copper plating layer 28 is covered with a conductor layer 26, 29 is formed on the second insulating layer 34 using the steps from FIG. A third insulating layer 3 made of a photosensitive polyimide film embedded with
form 5. In this way, a first insulating layer on which a circuit pattern 32 is formed, a second insulating layer on which a conductor via pole 33 is formed, and a third insulating layer 35 on which a circuit pattern 32 is formed are sequentially formed on the ceramic substrate 22. . Then, these insulating layers are sequentially laminated. In this way, the circuit pattern 3 formed of the copper plating layer 28 covered with the conductor layers 26 and 29 forming these circuit patterns 32
2 is buried in the first insulating layer 24 and the third insulating layer 35, so that no step is created between the surface of the insulating layer 24, 35 and the surface of the circuit pattern 32.

When the above-described method is used, as shown in FIG. , 52B, 53A, 53B, 54A,
A power supply and ground pattern (G/V) 5 which forms 54B and 55 and has a frame-like cross section and extends perpendicularly to the plane of the paper.
6, and a signal circuit pattern 57 extending perpendicular to the plane of the paper is formed in the same manner as in forming the circuit pattern 32 in the center of the frame-shaped power supply and ground pattern 56 on the insulating layer 43. A thin film multilayer coaxial circuit board can be formed.

Further, the conductor via hole layer 5 is formed using the same method as that for forming the conductor via hole 33 described above in the insulating layer 42, 44.
8.59 can be formed to form a thin film multilayer coaxial circuit board that connects the signal circuit pattern 57 and the frame-shaped power supply/ground pattern 56.

As described above, according to the method of the present invention, a circuit pattern is formed by embedding a conductor layer in an insulating layer on a ceramic substrate. When these insulating layers are formed into a multilayer structure without generating any steps, a thin film multilayer circuit board with a flat surface can be obtained.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, a multilayer thin film circuit board with a flat surface can be obtained.

[Brief explanation of drawings]

1A to 1D are cross-sectional views showing the steps of an embodiment of the method of the present invention; FIG. 2 is an explanatory diagram of a coaxial circuit pattern formed by the method of the present invention; 3(a) to 3(g) are cross-sectional views showing the steps of the conventional method. In the figure, 21 is a conductor pattern, 22 is a ceramic substrate, 23 is a conductor via hole, 24 is a first insulating layer, 25 is an opening, 26 is a conductor layer, 27 is a resist pattern, 28 is a Cu plating layer, 29 is a conductor layer, 31 is a resist film, 32 is a circuit pattern, 33 is a conductive via hole, 34 is a second insulating layer, 35 is a third insulating layer, 41, 42.43, 44.45 are insulating layers,
51.52A52B, 53A, 53B, 548, 54B
, 55 is a conductor layer pattern, 56 is a power supply and ground pattern, 57 is a signal circuit pattern, and 58 and 59 are conductor via holes. 444 Akebono no Saisho Gii l de no / l Ice Encounter 1q1・Tilt [; End of T Ube Geki” Menu Figure 1 Figure 1 Fupai Akira/lγ; Figure te) Follow / Section 1 - End view of construction material association

Claims (1)

[Claims] Multiple insulating layers (24, 34, 35) on the substrate (22)
) Formation of the conductor layer pattern (33) of the insulating layer (24, 34, 35) in the production of a circuit board in which the conductor layer patterns (32) formed on the insulating layer (24, 34, 35) are connected through conductor via holes (33). forming a recess (25) in advance in the planned area;
A method for manufacturing a thin film multilayer circuit board, characterized in that a conductor layer pattern (33) is embedded in the recess.