JPH0284744A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0284744A JPH0284744A JP20117189A JP20117189A JPH0284744A JP H0284744 A JPH0284744 A JP H0284744A JP 20117189 A JP20117189 A JP 20117189A JP 20117189 A JP20117189 A JP 20117189A JP H0284744 A JPH0284744 A JP H0284744A
- Authority
- JP
- Japan
- Prior art keywords
- silver
- tab
- lead frame
- pellet
- inner leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims abstract description 38
- 229910052709 silver Inorganic materials 0.000 claims abstract description 38
- 239000004332 silver Substances 0.000 claims abstract description 38
- 239000008188 pellet Substances 0.000 claims abstract description 20
- 239000010949 copper Substances 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052802 copper Inorganic materials 0.000 claims abstract description 4
- 238000007747 plating Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 7
- 239000002994 raw material Substances 0.000 abstract 1
- 239000010931 gold Substances 0.000 description 4
- 239000010970 precious metal Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910000510 noble metal Inorganic materials 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
- H01L2224/48249—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明はリードフレームを用いた半導体装置の製造方法
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device using a lead frame.
［従来技術］
一般に、たとえばトランジスタや集積回路（ＩＣ）の如
き半導体装置の製造には、金属リボン状のリードフレー
ムが用いられている。このリードフレームは半導体チッ
プであるペレットを取り付けるためのタブ、ペレットの
ボンディングとワイヤで電気的に接続されるインナーリ
ード、該インナーリードとダムと呼ばれる連結部を介し
て連結され、外部接続端子を構成するアウターリード等
を有している。[Prior Art] Generally, metal ribbon-shaped lead frames are used in the manufacture of semiconductor devices such as transistors and integrated circuits (ICs). This lead frame includes a tab for attaching a pellet, which is a semiconductor chip, an inner lead that is electrically connected to the bonding of the pellet with a wire, and is connected to the inner lead via a connecting part called a dam, forming an external connection terminal. It has an outer lead etc.
このようなリードフレームにおいて、従来インナーリー
ドには、ペレットのボンディングとの電気的接続のため
に金（Ａｕ）や銀（Ａｇ）等の貴金属を、たとえば樹脂
モールドやパッケージの如き封入物への気密封止のため
のモールド外形線ＭＬ（またはガラス封止外形線）の領
域内でメッキするのが普通である。In such lead frames, conventionally, inner leads are filled with precious metals such as gold (Au) or silver (Ag) for electrical connection with pellet bonding, and are filled with air into an encapsulation such as a resin mold or package. It is common to plate within the area of the mold outline ML (or glass sealing outline) for hermetic sealing.
［発明が解決しようとする課題］
しかしながら、リードフレームに形成される銀メッキ層
は部分メッキの場合でも、はとんどのメッキ部分は本来
不必要なものであり、金や銀のような極めて高価な貴金
属材料の無駄使いになり、また徒らにリードフレームお
よびそれを用いた半導体装置のコストを上昇させる結果
となる。[Problems to be Solved by the Invention] However, even when the silver plating layer formed on the lead frame is partially plated, most of the plating parts are originally unnecessary, and extremely expensive materials such as gold and silver are used. This results in a waste of precious metal materials and unnecessarily increases the cost of the lead frame and the semiconductor device using it.
さらに、たとえば銀の場合には、本来タブにはメッキを
する必要がない上に、余分な銀メッキによりマイグレー
ションのポテンシャルを高くし、水分による短絡を生じ
易くなる等の欠点を生じていた。Furthermore, in the case of silver, for example, there is no need to plate the tab, and additional silver plating increases the migration potential, making it more likely to cause short circuits due to moisture.
本発明は前記した従来技術の欠点を解消するためになさ
れたもので、貴金属材料である銀の使用量を大幅に減少
させ、なおかつその銀がリードフレームに対して接着良
好にせしめることのできる半導体装置の製造方法を提供
することを目的とするものである。The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and it is possible to significantly reduce the amount of silver used as a precious metal material, and to provide a semiconductor that allows the silver to adhere well to a lead frame. The object of the present invention is to provide a method for manufacturing the device.
本発明の前記ならびにその他の目的と新規な特徴は１本
明細書の記述および添付図面から明らかになるであろう
。The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
［問題点を解決するための手段］
本願において開示される発明のうち代表的なものの概要
を説明すれば１次のとおりである。[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.
すなわち。Namely.
■タブ、そのタブに先端が近接する複数のインナーリー
ド、外部端子を構成する複数のアウターリードおよびそ
れらインナーリードとアウターリードとを連結する連結
部とから成る銅系素材のリードフレームを準備する段階
、
■そのリードフレームの全面に対して銀との密着性の良
好な被膜を形成する段階、しかる後、■ワイヤボンディ
ングされるべき前記複数のインナーリードの先端に部分
銀メッキ層を施す段階、■前記タブ上に半導体ペレット
をボンディングする段階、
■ワイヤの一端を前記ペレットの電極部に、他端を前記
インナーリードの先端にボンディングする段階、
■前記インナーリード、半導体ペレット、タブおよびワ
イヤをパッケージにより封止する段階。■Preparing a lead frame made of a copper-based material consisting of a tab, a plurality of inner leads whose tips are close to the tab, a plurality of outer leads that constitute external terminals, and a connecting part that connects these inner leads and outer leads. (2) Forming a coating with good adhesion to silver on the entire surface of the lead frame, (2) Applying a partial silver plating layer to the tips of the plurality of inner leads to be wire bonded, (2) bonding a semiconductor pellet onto the tab; (i) bonding one end of the wire to the electrode portion of the pellet and the other end to the tip of the inner lead; (ii) packaging the inner lead, semiconductor pellet, tab, and wire; Sealing stage.
とを含むことを特徴とする。It is characterized by including.
［作用］
前記した手段によれば、リードフレームに対して部分的
な銀メッキ層形成であるために、貴金属材料である銀の
使用量は大幅に減少されることになる。[Function] According to the above-described means, since the silver plating layer is formed only partially on the lead frame, the amount of silver, which is a noble metal material, used can be significantly reduced.
また、部分銀形成に先立っての銀との密着性の良好な被
膜形成はをリードフレーム対して全面的な形成手段とし
たものであるから極めて簡便である。Further, the formation of a film having good adhesion to silver prior to the formation of partial silver is extremely simple since it is a means of forming the entire surface of the lead frame.
［実施例］
第１図は本発明の一実施例である半導体装置に使用され
ているリードフレームを示す平面図、第２図はそのペレ
ット取付状態を示す拡大部分断面図、第３図は本発明の
リードフレームの状態をよ視図である。[Example] Fig. 1 is a plan view showing a lead frame used in a semiconductor device according to an embodiment of the present invention, Fig. 2 is an enlarged partial cross-sectional view showing the pellet attached state, and Fig. 3 is a diagram showing a lead frame used in a semiconductor device according to an embodiment of the present invention. FIG. 3 is a perspective view of the state of the lead frame of the invention.
本実施例はシングルインライン（Ｓ Ｉ Ｌ）形のリー
ドフレームに本発明を適用した例であり、このリードフ
レームは、外部接続端子を構成するアウターリード１０
、該アウターリード１０と連結部（ダム）１２を介して
連結されたインナーリード１４、半導体チップであるペ
レット１８（第２図）を取り付けるタブ１６、該タブ１
６を機械的に支持するタブ吊り用リード２ｏ、前記ペレ
ット１８のポンディングパッド部と前記インナーリード
１４とを電気的に接続するワイヤ２２（第２図）を有し
ている。This embodiment is an example in which the present invention is applied to a single in-line (S I L) type lead frame, and this lead frame has an outer lead 10 constituting an external connection terminal.
, an inner lead 14 connected to the outer lead 10 via a connecting portion (dam) 12, a tab 16 for attaching a pellet 18 (FIG. 2), which is a semiconductor chip, and the tab 1.
6, and a wire 22 (FIG. 2) that electrically connects the bonding pad portion of the pellet 18 and the inner lead 14.
本実施例においては、前記インナーリード１４への金ま
たは銀のような貴金属のメッキは第１図および第２図に
符号２４で示すように、ワイヤ２２をボンディングすべ
き部分に部分的に施されている。したがって、本実施例
における銀のような貴金属の使用量は非常に少くなり、
コスト的に極めて有利である。In this embodiment, the inner lead 14 is partially plated with a noble metal such as gold or silver at a portion where the wire 22 is to be bonded, as shown by reference numeral 24 in FIGS. 1 and 2. ing. Therefore, the amount of precious metals such as silver used in this example is very small.
Extremely advantageous in terms of cost.
このような部分的なメッキ２４を施す方法としては、リ
ードフレームの素材が銅（Ｃｕ）系の金属の場合には、
まず第３図に示すように、予めリードフレーム（全面）
上にフラッシュメッキ層２６を、常温での酸化防止を可
能にする程度の厚さに形成しておき、そのフラッシュメ
ッキ層２６上に部分銀メッキ層２４を形成する。この場
合の有益な点は以下に述べるとおりにある。As a method for applying such partial plating 24, when the lead frame material is a copper (Cu)-based metal,
First, as shown in Figure 3, the lead frame (full surface) is prepared in advance.
A flash plating layer 26 is formed thereon to a thickness sufficient to prevent oxidation at room temperature, and a partial silver plating layer 24 is formed on the flash plating layer 26. The advantages of this case are as follows.
一般に、Ｃｕ系フレーム素材は多くの不純物を含み、ま
た表面が酸化されているために、銀との密着性が良くな
い。このため、上述の如く予めリードフレームに銀との
密着性をよくする被膜を全面的に形成する。全面的な被
膜（フラッシュメッキ層）形成は、リボン状のリードフ
レームに対して最も簡便な方法であることは言うまでも
ない。Generally, Cu-based frame materials contain many impurities and have an oxidized surface, so they do not have good adhesion to silver. For this purpose, as described above, a coating that improves adhesion to silver is previously formed on the entire surface of the lead frame. It goes without saying that forming a coating (flash plating layer) on the entire surface is the simplest method for ribbon-shaped lead frames.
かかるフラッシュメッキ層上への部分銀メッキは密着性
良く、確実なものとなる。Partial silver plating on such a flash plating layer has good adhesion and is reliable.
このようにして、インナーリード１４上の必要な部ファ
ンのみに形成された銀メッキ層２４には、他端をペレッ
ト１８のポンディングパッド部にボンディングされたワ
イヤ２２の一端がボンディングされており、この銀メッ
キＭ２４とワイヤ２２とのボンディングにより良好な電
気的接続が行なわれる。In this way, one end of the wire 22, the other end of which is bonded to the bonding pad of the pellet 18, is bonded to the silver plating layer 24, which is formed only on the necessary parts of the fan on the inner lead 14. Bonding between the silver plating M24 and the wire 22 provides good electrical connection.
なお、その場合、銀メッキ暦２４はごく一部のみに施さ
れるので、インナーリード１４のほぼ全面に銀メッキ暦
を施す場合と違って、銀メッキ層２４に若干のダレが生
じても特に問題とはならない。In this case, since the silver plating layer 24 is applied only to a small portion, unlike the case where the silver plating layer 24 is applied to almost the entire surface of the inner lead 14, even if the silver plating layer 24 slightly sag, it is not particularly important. Not a problem.
ペレットおよびワイヤボンディングされたリードフレー
ムには樹脂封止パッケージ２８が、銀メッキ層２４を含
むインナーリード１４．タブ１６、タブ１６にボンディ
ングされたペレット１８およびワイヤ２２をｍ封止する
ように形成される。A resin-sealed package 28 is attached to the pellet- and wire-bonded lead frame, and an inner lead 14 including a silver plating layer 24 is attached to the lead frame. The tab 16 is formed to seal the pellet 18 and wire 22 bonded to the tab 16.
樹脂封止後、リードフレームのダム１２および外枠が切
り落され、第４図に示されているようなＳＩＬ形ＩＣが
完成される。After resin sealing, the dam 12 and outer frame of the lead frame are cut off to complete the SIL type IC as shown in FIG.
本発明はＳＩＬ形のみならず、デュアルインライン（Ｄ
ＩＬ）形の半導体装置やペレット取付部をセラミックパ
ッケージ内に気密封止した半導体装置も含むものである
。The present invention is applicable not only to SIL type but also to dual in-line (D
It also includes IL) type semiconductor devices and semiconductor devices in which a pellet mounting portion is hermetically sealed within a ceramic package.
［発明の効果］
以上用説明したように、本発明によれば、半導体装置に
使用される貴金属である銀の使用量を大幅に減少させる
ことができるため、コストを著しく低減させることがで
きる。[Effects of the Invention] As described above, according to the present invention, the amount of silver, which is a noble metal used in semiconductor devices, can be significantly reduced, and thus costs can be significantly reduced.
また、特に樹脂封止の場合はセラミックによる気密封止
に比べて水分がパッケージ内へ浸入し易いが、部分銀メ
ッキ形成のために、銀によるマイグレーションのポテン
シャル減少により、水分による短絡の発生を防止するこ
とができる。In addition, especially in the case of resin sealing, moisture can easily infiltrate into the package compared to hermetic sealing with ceramic, but because of the partial silver plating, the migration potential due to silver is reduced, preventing the occurrence of short circuits due to moisture. can do.
さらに、本発明によれば、部分銀メッキ層形成に先立っ
てのリードフレームに対する銀との密着性の良い薄膜形
成は全面的に行なうものであるから極めて簡便である。Furthermore, according to the present invention, the formation of a thin film with good adhesion to silver on the lead frame prior to forming the partial silver plating layer is performed on the entire surface, which is extremely simple.
第１図は本発明の一実施例である半導体装置に使用され
ているリードフレームを示す平面図、第２図はそのペレ
ット取付状態を示す拡大部分断面図、
第３図は本発明のリードフレームの状態をより詳細に開
示した拡大部分断面図、
第４図は本発明の方法によって組立られた半導体装置を
示す斜視図である。
１０・・・アウターリード、１４・・・インナーリード
、１６・・・タブ、１８・・・ペレット、２ｏ・・・タ
ブ吊り用リード、２２・・・ワイヤ、２４・・・部分的
な銀メッキ層、２６・・・フラッシュメッキ層、２８・
・・樹脂封止パッケージ。
第
図
第
図
第
図FIG. 1 is a plan view showing a lead frame used in a semiconductor device according to an embodiment of the present invention, FIG. 2 is an enlarged partial sectional view showing the pellet attached state, and FIG. 3 is a lead frame of the present invention. FIG. 4 is a perspective view showing a semiconductor device assembled by the method of the present invention. DESCRIPTION OF SYMBOLS 10... Outer lead, 14... Inner lead, 16... Tab, 18... Pellet, 2o... Lead for tab suspension, 22... Wire, 24... Partial silver plating Layer, 26... Flash plating layer, 28.
・Resin-sealed package. Figure Figure Figure Figure
Claims (1)
ナーリード、外部端子を構成する複数のアウターリード
およびそれらインナーリードとアウターリードとを連結
する連結部とから成る銅系素材のリードフレームを準備
する段階、 （２）そのリードフレームの全面に対して銀との密着性
の良好な被膜を形成する段階、しかる後、（３）ワイヤ
ボンディングされるべき前記複数のインナーリードの先
端に部分銀メッキ層を施す段階、（４）前記タブ上に半
導体ペレットをボンディングする段階、 （５）ワイヤの一端を前記ペレットの電極部に、他端を
前記インナーリードの先端にボンディングする段階、 （６）前記インナーリード、半導体ペレット、タブおよ
びワイヤをパッケージにより封止する段階、とを含むこ
とを特徴とする半導体装置の製造方法。[Claims] 1. (1) Consists of a tab, a plurality of inner leads whose tips are close to the tab, a plurality of outer leads constituting external terminals, and a connecting portion that connects the inner leads and the outer leads. a step of preparing a lead frame made of a copper-based material; (2) a step of forming a film with good adhesion to silver on the entire surface of the lead frame; applying a partial silver plating layer to the tip of the inner lead; (4) bonding a semiconductor pellet onto the tab; (5) attaching one end of the wire to the electrode part of the pellet and the other end to the tip of the inner lead. A method for manufacturing a semiconductor device, comprising the steps of bonding; (6) sealing the inner lead, semiconductor pellet, tab, and wire with a package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20117189A JPH0284744A (en) | 1989-08-04 | 1989-08-04 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20117189A JPH0284744A (en) | 1989-08-04 | 1989-08-04 | Manufacture of semiconductor device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10113080A Division JPS5727050A (en) | 1980-07-25 | 1980-07-25 | Lead frame and semiconductor device using said lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284744A true JPH0284744A (en) | 1990-03-26 |
Family
ID=16436542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20117189A Pending JPH0284744A (en) | 1989-08-04 | 1989-08-04 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284744A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19640256A1 (en) * | 1995-09-29 | 1997-04-03 | Dainippon Printing Co Ltd | Connecting frame for plastics embedded semiconductor component |
| EP0902472A2 (en) * | 1997-09-15 | 1999-03-17 | Microchip Technology Inc. | Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4895184A (en) * | 1972-03-16 | 1973-12-06 | ||
| JPS52128845A (en) * | 1976-04-21 | 1977-10-28 | Hitachi Cable | Method of fabricating silver plated copper wire |
-
1989
- 1989-08-04 JP JP20117189A patent/JPH0284744A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4895184A (en) * | 1972-03-16 | 1973-12-06 | ||
| JPS52128845A (en) * | 1976-04-21 | 1977-10-28 | Hitachi Cable | Method of fabricating silver plated copper wire |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19640256A1 (en) * | 1995-09-29 | 1997-04-03 | Dainippon Printing Co Ltd | Connecting frame for plastics embedded semiconductor component |
| US6034422A (en) * | 1995-09-29 | 2000-03-07 | Dai Nippon Printing Co., Ltd. | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame |
| DE19640256B4 (en) * | 1995-09-29 | 2004-04-08 | Dai Nippon Printing Co., Ltd. | Lead frame, method for precious metal plating of the lead frame and semiconductor device with lead frame |
| EP0902472A2 (en) * | 1997-09-15 | 1999-03-17 | Microchip Technology Inc. | Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor |
| EP0902472A3 (en) * | 1997-09-15 | 2000-10-18 | Microchip Technology Inc. | Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor |
| JP2009032899A (en) * | 2007-07-27 | 2009-02-12 | Renesas Technology Corp | Semiconductor device |
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