EP0902472A2 - Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor - Google Patents

Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor Download PDF

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Publication number
EP0902472A2
EP0902472A2 EP19980117437 EP98117437A EP0902472A2 EP 0902472 A2 EP0902472 A2 EP 0902472A2 EP 19980117437 EP19980117437 EP 19980117437 EP 98117437 A EP98117437 A EP 98117437A EP 0902472 A2 EP0902472 A2 EP 0902472A2
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EP
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Patent type
Prior art keywords
lead frame
integrated circuit
semiconductor chip
circuit semiconductor
coil
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19980117437
Other languages
German (de)
French (fr)
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EP0902472A3 (en )
Inventor
Joseph Fernandez
Lee Furey
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Microchip Technology Inc
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Microchip Technology Inc
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/645Inductive arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06KRECOGNITION OF DATA; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49541Geometry of the lead-frame
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04Resonant antennas
    • H01Q9/16Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole
    • H01Q9/26Resonant antennas with feed intermediate between the extremities of the antenna, e.g. centre-fed dipole with folded element or elements, the folded parts being spaced apart a small fraction of operating wavelength
    • H01Q9/27Spiral antennas
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1904Component type
    • H01L2924/19041Component type being a capacitor
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/30107Inductance

Abstract

A combination inductive coil and integrated circuit semiconductor chip is provided in a single lead frame package. The lead frame is preferably made of a copper alloy and has a flat configuration. The chip is electrically connected to end portions of the inductive coil thus permitting the inductive coil to function as an antenna for the chip.

Description

    Field Of The Invention
  • This invention relates generally to the use of passive devices with semiconductor devices and methods therefor and, more particularly, to a combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor.
  • Background Of The Prior Art
  • In the past, passive devices such as instructors, capacitors and resistors were combined with active devices such as diodes and transistors on a printed circuit board to manufacture electronic circuits and/or electronic systems.
  • As the technology developed, active devices of various types such as bipolar and MOS (or unipolar) devices became integrated into a single semiconductor chip. Integration of these active devices and also passive devices such as resistors and capacitors into a single semiconductor chip led to the formation of electrical circuits in a single semiconductor chip which became known as an integrated circuit semiconductor chip.
  • Packaging of such integrated circuit semiconductor chips became very important. As a result, integrated circuit semiconductor chip manufacturers have sought for ways to inexpensively and reliably package integrated circuit semiconductor chips.
  • One early packaging technique was to provide hybrid packages which usually incorporated integrated circuit semiconductor chips with passive devices ouch as capacitors and resistors on a ceramic substrate surface of a ceramic package which would have metal pins to permit the ceramic package to be inserted into via holes in a printed circuit board containing a number of such ceramic packages interconnected to provide either an electronic circuit or electronic system. Ceramic packages were very costly resulting in higher costs for a printed circuit board using multiple ceramic packages.
  • In an effort to significantly reduce manufacturing costs, lead frame packages were developed to protectively house integrated circuit semiconductor chips. A lead frame package generally comprised a metal lead frame member that would carry an integrated circuit semiconductor chip on a portion thereof. Wirebonding techniques were used to electrically connect terminal portions or pads of the integrated circuit semiconductor chip to fingers of the lead frame structure. Subsequently, the integrated circuit semiconductor chip on the lead frame structure with its wirebond connections thereto was encapsulated with plastic to provide a plastic encapsulated lead frame package. From a manufacturing cost point of view, plastic encapsulated lead frame packages were very inexpensive as compared to, for example, ceramic type packages.
  • A need existed to develop electronic type products that would be relatively inexpensive to make and that would take advantage of the lead frame manufacturing technology. Specifically, a need existed for improved lead frame type products that could perform functions that were not provided by the available lead frame products.
  • Summary Of The Invention
  • Accordingly, it is an abject of this invention to provide an improved lead frame package and method.
  • It is a further object of this invention to provide an improved lead frame package and method which combines an integrated circuit semiconductor chip and a passive device in a single lead frame package.
  • It is another object of this invention to provide an improved lead frame package and method which combines an integrated circuit semiconductor chip and an inductor in a single lead frame package.
  • It is still another object of this invention to provide an improved lead frame package and method which combines an integrated circuit semiconductor chip and an inductive coil in a single lead frame package where the integrated circuit semiconductor chip is a transmitter.
  • It is another object of this invention to provide an improved lead frame package and method which combines an integrated circuit semiconductor chip in a single lead frame package where the integrated circuit semiconductor chip is a receiver and the inductive coil is the antenna for the receiver.
  • Brief Description Of The Preferred Embodiments
  • In accordance with one embodiment of this invention, a combination inductive coil and integrated circuit semiconductor chip is provided in a single lead frame package which comprises, in combination: a single package; a lead frame located in the single package and having a coil configuration, the lead frame located in one horizontal plane; and an integrated circuit semiconductor chip located in the single package and coupled to the lead frame and having at least one terminal pad electrically connected to at least one portion of the coil configuration of the lead frame. Preferably the integrated circuit semiconductor chip has at least two terminal pads, one of the two terminal pads of the integrated circuit semiconductor chip being electrically connected to one end portion of the coil configuration of the lead frame, the other of the two terminal pads of the integrated circuit semiconductor chip being electrically connected to the other end portion of the coil configuration of the lead frame.
  • In accordance with another embodiment of this invention, a method of combining an inductive coil and integrated circuit semiconductor chip in a single lead frame package is provided which comprises the steps of: providing a single package; providing a lead frame located in the single package and having a coil configuration, the lead frame located in one horizontal plane; and providing an integrated circuit semiconductor chip located in the single package and coupled to the lead frame and having at least one terminal pad electrically connected to at least one portion of the coil configuration of the lead frame.
  • The foregoing and other objects, features and advantages of this invention will be apparent from the following more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.
  • Brief Description Of The Figures
    • Figure 1 is a sectional view taken through a single lead frame plastic encapsulated package of this invention showing an integrated circuit semiconductor chip mounted on a portion of the single lead frame plastic encapsulated package and electrically connected to the two end portions of an inductive coil that is spaced from the chip and which comprises a substantial portion of the lead frame of this package.
    • Figure 2 is also a sectional view taken through another embodiment of a single lead frame plastic encapsulated package of this invention showing an integrated circuit semiconductor chip mounted on a corner end portion of an inductive coil that comprises a substantial portion of the lead frame of this package wherein the chip is dielectrically insulated from the portions of the inductive coil located beneath the chip, but electrically connected to the two end portions of the inductive coil.
  • Description Of The Specification
  • Referring to Figure 1, reference number 10 generally refers to a combination inductive coil and integrated circuit semiconductor chip in a single lead frame package. The package 10 comprises a plastic encapsulated envelope 12 that is made of the type of plastic encapsulation type material used in plastic encapsulated packages. Contained within the plastic encapsulated envelope 12 as an inductive coil shape or configuration lead frame structure 14 having, for example, three attached tie members 16 which have been cut off from the tie members (not shown) of adjacent similarly configured coil shaped lead frames (not shown) that were, for example, stamped out in one metal stamping operation used to form a number of these coil shaped lead frames at one time for subsequent separation into individual coil shaped lead frame elements like the one shown in Figure 1. The tie bars 16 functions to hold the coil 14 and the subsequently described die paddle in the same plane. In the embodiment of Figure 1, the inductive coil 14 is preferably made of a copper alloy such as copper alloy known as CDA194. Preferably, the copper lines of the inductive coil 14 are about 10 mils wide and the space between adjacent copper lines is preferably about 10 mils wide. In the embodiment of Figure 1, the inductive coil 14 preferably is flat and has six turns, however, if desired, a greater or lesser number of turns can be used depending upon the magnitude or amount of electrical inductance desired. The length of the inductive coil 14 is, for example, about 160 mils long. The operating signal of the RF inductive coil 14 is, for example, 13.6 Megahertz and the range is from about a couple of inches to about one meter.
  • A die attach paddle or pad 18 also is part of the lead frame, but not a portion of the inductive coil 14 because it is spaced therefrom as shown in Figure 1 where it is shown connected to a pair of vertical tie bar type members 20 and a top horizontal tie bar member 22. The members 20 and 22 were previously connected to corresponding tie bar members (not shown) of adjacent lead frame structures (not shown) before being separated into the configuration shown in Figure 1. An integrated circuit semiconductor chip 24 is shown mounted on and connected by, for example, a suitable adhesive on its backside portion to the die attach paddle 18.
  • In the embodiment of Figure 1, two terminal pads 26 and 28 of the integrated circuit semiconductor chip 24 are, respectively, electrically connected to outer 30 and inner 32 end portions of the inductive coil 14 respectively, by means of electrically conductive wire bonds 34 and 36. The chip 24 can be any type of integrated circuit semiconductor chip, however, if the chip 24 is a transmitter type of integrated circuit semiconductor chip, then an electronic signal generated by such a chip 24 can be transmitted by means of the inductive coil 14 functioning as a transmitting antenna with an RF signal of 13.6 Megahertz at a range of from about a couple of inches to about a meter. Correspondingly, if the chip 24 is a receiver type of integrated circuit semiconductor chip, then, by means of the inductive coil 14 functioning as a receiving antenna, the chip 24 can receive appropriate electronic signals. If desired, the chip 24 can be both a transmitter and receiver to permit the chip 24 to selectively function as either a transmitter or receiver.
  • Referring to Figure 2, the same reference numerals used in Figure 1 are used in Figure 2 to designate the same elements. In the embodiment of Figure 2, there are four turns for the inductive coil 14 rather than the six turns depicted in Figure 1. Again, the number of turns for the inductive coil can be varied as desired for specific reasons such as the magnitude or amount of inductance needed for the inductive coil 14. Furthermore, in the embodiment of Figure 2, the integrated circuit semiconductor chip 24 is preferably located over a corner portion or the coil 14 adjacent to where the end portion 30 of the coil 14 is located. A dielectric type adhesive or epoxy is used to adhere the chip 24 to the portions of the coil 14, in the corner, located beneath the chip 24. The use of the dielectric adhesive prevents a bottom portion of the chip 14 to produce an electrically short across adjacent portions of the coil 14. In the embodiment of Figure 2, the wire bond 34 provides an electrical contact between terminal pad 26 of the chip 24 and a silver plated tip portion 38 located at the end portion 30 of the inductive coil 14. Similarly, a silver plated tip portion 40 at the end portion 32 of the coil 14 also permits the wire bond 36 to provide electrical contact between the terminal pad 28 of the integrated circuit chip 24 and the silver plated tip portion 40 of the end portion 32 of the coil 14. The silver plated tip portions 38 and 40 are created by silver plating the appropriate region on the copper surface of the copper inductive coil 14. The embodiment of Figure 2 is more compact which should provide shorter electrically conductive paths and faster response times. Also, the embodiment of Figure 2 requires less lead frame material and should be less costly than the embodiment structure of Figure 1. One further significant advantage of the embodiments of Figures 1 and 2 is that the RF inductive coils 14 of these two embodiments can be made of the same material as is used in stamping out lead frames for other packages Another significant advantage of the embodiment of Figure 2 is that more coil turns per area can be used, if desired, and the substantial elimination or minimization of crossing wire bonds over coils of the inductive coil 14 is achieved in Figure 2. The silver plated tip portions 38 and 40 shown in Figure 2 can also be used for the embodiment of Figure 1, if desired. One further significant advantage of the embodiments of Figures 1 and 2 is that, if desired, no external leads are provided outside of the package of Figures 1 and 2 and the antenna (inductive coil 14) can be solely used to provide electronic signals into the packages of Figures 1 or 2 and to also, if desired, take electronic signals out of the packages of Figures 1 and 2.
  • While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims (40)

  1. A combination inductive coil and integrated circuit semiconductor chip in a single lead frame package comprising, in combination:
    a single package;
    a lead frame located in said single package and having a coil configuration, said lead frame located in one horizontal plane; and
    an integrated circuit semiconductor chip located in said single package and coupled to said lead frame and having at least one terminal pad electrically connected to at least one portion of said coil configuration of said lead frame.
  2. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to one end portion of said coil configuration of said lead frame, the other of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to the other end portion of said coil configuration of said lead frame.
  3. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 2 wherein both of said two terminal pads of said integrated circuit semiconductor chip being located on a top surface of said integrated circuit semiconductor chip, a bottom surface portion of said integrated circuit semiconductor chip being connected to a portion of said lead frame.
  4. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 3 wherein said single package is a plastic encapsulated single package.
  5. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said coil configuration of said lead frame being a substantially flat coil configuration.
  6. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 5 wherein said coil configuration of said lead frame is a coil made of a copper alloy.
  7. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 6 wherein said copper alloy is a CDA/94 copper alloy.
  8. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 6 wherein said copper coil having two end portions, each of said two end portions having silver filled tip portions.
  9. The combination inductive coil and integrated circuit semiconductor chip in a single lend frame package of Claim 8 wherein said silver filled tip portions being spot silver plated tip portions silver plated onto each of said two end portions of said copper coil.
  10. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 2 wherein said coil configuration of said lead frame being a substantially flat oil configuration, said coil configuration of said lead frame is a coil made of a copper alloy, said copper coil having two end portions, each of said two end portions having silver filled tip portions, one of said two terminal pads of said integrated circuit semiconductor, being electrically connected to a silver filled tip portion located at one of said two end portions of said copper coil, the other of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to a silver filled tip portion located at the other of said two end portions of said copper coil.
  11. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said integrated circuit semiconductor chip is a transmitter, said coil configuration of said lead frame is a transmitting antenna for said transmitter.
  12. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said integrated circuit semiconductor chip is a receiver, said coil configuration of said lead frame is a receiving antenna for said receiver.
  13. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said integrated circuit semiconductor chip being located over a substantially corner region of said coil configuration of said lead frame.
  14. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 1 wherein said integrated circuit semiconductor chip being located adjacent one side portion of said coil configuration of said lead frame.
  15. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 13 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads being electrically connected to one end portion of said coil configuration of said lead frame, the other one of said two terminal pads being electrically connected to the other end portion of said coil configuration of said lead frame.
  16. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 15 wherein said one end portion of said coil configuration of said lead frame being located adjacent one side of said integrated circuit semiconductor chip, said other end portion of said coil configuration of said lead frame being located adjacent another side of said integrated circuit semiconductor chip.
  17. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 14 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads being electrically connected to one end portion of said coil configuration of said lead frame, the other one of said two terminal pads being electrically connected to the other end portion of said coil configuration of said lend frame, said one end portion of said coil configuration of said lead frame being located in a center portion of said coil configuration of said lead frame spaced from said integrated circuit semiconductor chip, said other end portion of said coil configuration of said lead frame being located adjacent to one side portion of said integrated circuit semiconductor chip.
  18. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 17 wherein said integrated circuit semiconductor chip being located on and attached to a portion of said lead frame having a substantially rectangular configuration and spaced from said other end portion of said coil configuration of said lead frame.
  19. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 15 wherein said one end portion of said coil configuration of said lead frame being located in a center portion of said coil configuration of said lead frame, said other end portion of said coil configuration of said lead frame extending underneath and past said integrated circuit semiconductor chip.
  20. The combination inductive coil and integrated circuit semiconductor chip in a single lead frame package of Claim 19 wherein said integrated circuit semiconductor chip being insulated from and attached to said corner region of said coil configuration of said lead frame.
  21. A method of combining an inductive coil and integrated circuit semiconductor chip in a single lead frame package comprising the steps of:
    providing a single package;
    providing a lead frame located in said single package and having a coil configuration, said lead frame located in one horizontal plane; and
    providing an integrated circuit semiconductor chip located in said single package and coupled to said lead frame and having at least one terminal pad electrically connected to at least one portion of said coil configuration of said lead frame.
  22. The method of Claim 21 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to one end portion of said coil configuration of said lead frame, the other of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to the other end portion of said coil configuration of said lead frame.
  23. The method of Claim 22 wherein both of said two terminal pads of said integrated circuit semiconductor chip being located on a top surface of said integrated circuit semiconductor chip, a bottom surface portion of said integrated circuit semiconductor chip being connected to a portion of said lead frame.
  24. The method of Claim 23 wherein said single package is a plastic encapsulated single package.
  25. The method of Claim 21 wherein said coil configuration of said lead frame being a substantially flat coil configuration.
  26. The method of Claim 25 wherein said coil configuration of said lead frame is a coil made of a copper alloy.
  27. The method of Claim 26 wherein said copper alloy is a CDA/94 copper alloy.
  28. The method of Claim 26 wherein said copper coil having two end portions, each of said two end portions having silver filled tip portions.
  29. The method of Claim 28 wherein said silver filled tip portions being spot silver plated tip portions silver plated onto each of said two end portions of said copper coil.
  30. The method of Claim 22 wherein said coil configuration of said lead frame being a substantially flat coil configuration, said coil configuration of said lead frame is a coil made of a copper alloy, said copper coil having two end portions, each of said two end portions having silver filled tip portions, one of said two terminal pads of said integrated circuit semiconductor, being electrically connected to a silver filled tip portion located at one of said two end portions of said copper coil, the other of said two terminal pads of said integrated circuit semiconductor chip being electrically connected to a silver filled tip portion located at the other of said two end portions of said copper coil.
  31. The method of Claim 21 wherein said integrated circuit semiconductor chip is a transmitter, said coil configuration of said lead frame is a transmitting antenna for said transmitter.
  32. The method of Claim 21 wherein said integrated circuit semiconductor chip is a transmitter, said coil configuration of said lead frame is a transmitting antenna for said transmitter.
  33. The method of Claim 21 wherein said integrated circuit semiconductor chip being located over a substantially corner region of said coil configuration of said lead frame.
  34. The method of Claim 21 wherein said integrated circuit semiconductor chip being located adjacent one side portion of said coil configuration of said lead frame.
  35. The method of Claim 23 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads being electrically connected to one end portion of said coil configuration of said lead frame, the other one of said two terminal pads being electrically connected to the other end portion of said coil configuration of said lead frame.
  36. The method of Claim 35 wherein said one end portion of said coil configuration of said lead frame being located adjacent one side of said integrated circuit semiconductor chip, said other end portion of said coil configuration of said lead frame being located adjacent another side of said integrated circuit semiconductor chip.
  37. The method of Claim 34 wherein said integrated circuit semiconductor chip having at least two terminal pads, one of said two terminal pads being electrically connected to one end portion of said coil configuration of said lead frame, the other one of said two terminal pads being electrically connected to the other end portion of said coil configuration of said lead frame, said one end portion of said coil configuration of said lead frame being located in a center portion of said coil configuration of said lead frame spaced from said integrated circuit semiconductor chip, said other end portion of said coil configuration of said lead frame being located adjacent to one side portion of said integrated circuit semiconductor chip.
  38. The method of Claim 37 wherein said integrated circuit semiconductor chip being located on and attached to a portion of said lead frame having a substantially rectangular configuration and spaced from said other end portion of said coil configuration of said lead frame.
  39. The method of Claim 35 wherein said one end portion of said coil configuration of said lead frame being located in a center portion of said coil configuration of said lead frame, said other end portion of said coil configuration of said lead frame extending underneath and past said integrated circuit semiconductor chip.
  40. The method of Claim 39 wherein said integrated circuit semiconductor chip being insulated from and attached to said corner region of said coil configuration of said lead frame.
EP19980117437 1997-09-15 1998-09-15 Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor Withdrawn EP0902472A3 (en)

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Application Number Priority Date Filing Date Title
US929579 1997-09-15
US08929579 US5909050A (en) 1997-09-15 1997-09-15 Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor

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EP0902472A2 true true EP0902472A2 (en) 1999-03-17
EP0902472A3 true EP0902472A3 (en) 2000-10-18

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EP1191478A1 (en) * 2000-08-31 2002-03-27 Shinko Electric Industries Co. Ltd. Antenna and antenna frame for IC card
US7463199B2 (en) 2002-11-07 2008-12-09 Fractus, S.A. Integrated circuit package including miniature antenna
US7924226B2 (en) 2004-09-27 2011-04-12 Fractus, S.A. Tunable antenna
US8154462B2 (en) 1999-09-20 2012-04-10 Fractus, S.A. Multilevel antennae
US8196829B2 (en) 2006-06-23 2012-06-12 Fractus, S.A. Chip module, sim card, wireless device and wireless communication method
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US6180433B1 (en) 2001-01-30 grant
JPH11154727A (en) 1999-06-08 application
EP0902472A3 (en) 2000-10-18 application
US5909050A (en) 1999-06-01 grant
JP2000124388A (en) 2000-04-28 application

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