JPH0283763A - Control system for measuring instrument - Google Patents

Abstract

PURPOSE:To obtain an interface that can correspond to a desired transfer speed with no deterioration of the throughput and with no abnormal working by supplying a clock after converting it via a speed converting part in accordance with the designation of a handshake speed designating area set on a subroutine of a computer. CONSTITUTION:A handshake speed designating area is secured on a subroutine set in a computer 60 of a controller 100 which controls an equipment to be controlled. A speed converting part 90 which is formed by a variable divider is controlled with the designation of a handshake speed designating area. Then a clock (1) is divided in accordance with the designation and a conversion clock (2)is supplied. An interface part 70 transfers the information at a speed corresponding to the clock (2). Thus it is possible to obtain an interface for control of measuring instruments that can correspond to a desired transfer speed with no deterioration of the throughput and with no abnormal working.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a control method for measuring instruments connected to a computer via a GPIB interface bus, which does not reduce the overall throughput and does not malfunction at any transfer speed ( The purpose of this project is to provide a control system for measuring instruments that uses a compatible GPIB interface, and includes an interface unit for converting the ink face on the output side of a computer to a GPIB interface, and a data byte transfer control system that makes up the GPTB interface. An area for specifying the handshake speed is set L-J on the subroutine in the computer in which the procedure for controlling handshake between the computer and the controlled device is set, and the speed specified in the handshake speed specification area is When the speed is changed, a speed conversion section is configured to process the processing timing in the interface section at the corresponding speed.

[Industrial application field]

The present invention relates to a control method for a measuring instrument connected to a computer via a GPTB interface.

Many systems that use computers to control various types of measuring instruments use the GPIB interface, which is sanctioned by the International Electrotechnical Commission (IEC).

This has a GPIB interface, such as a voltmeter.

CPI is suitable for systematizing and controlling various measuring instruments such as signal generators and tape readers, or for constructing and using devices with different operating speeds in the same system.
This is because the B interface is defined.

However, with the expansion of its range of use and the advancement of technology, the transfer speed has improved more than expected, causing a slight discrepancy in the hunt shake between the control device, the computer, and the controlled device, the measuring instrument. This may cause the system to malfunction and stop.

It is necessary to completely eliminate such abnormal operations in order to further expand the range of use.

[Conventional technology]

FIG. 5 is a diagram illustrating a conventional example of a system connected by a GPIB interface, and FIG. 6 is a diagram illustrating a GPTB adapter circuit.

The n controlled devices 2 (1) to 2 (n) are various measuring instruments such as voltmeter signal generators and tape leagues, and the controlled devices 2 (1) to 2 (n) are controlled based on a predetermined program. Microprocessor (hereinafter referred to as MPU) 6 and GP
The controller I/roller 1 equipped with the rB adapter circuit 7 is connected to the CP
Connect via IB interface bus 5.

As shown in Figure 6, the GPIB interface bus 5 is connected to a data bus (fa) for carrying messages consisting of 8-bit information, addresses, commands, etc. A data byte transfer control bus (BL) that asynchronously confirms messages, and an interface management bus (C) that distinguishes between information and commands, confirms the request source, and determines the method of recognition. It is composed of.

These three buses (al~(C)
A GPIB adapter circuit 7 is installed between the MPU 6 and the GPIB adapter circuit 7, and the GPIB adapter circuit 7 and the MPU 6 are connected by a data bus (a)' and a control bus (b)'.

In addition to the MPU 6 and the GPIB adapter circuit 7, the controller I/roller 1 is provided with a clock generator 8 for generating a clock CLK of a predetermined speed that determines the processing timing of the GPIB adapter circuit 7.

Further, the GP■B adapter circuit 7 includes, for example, a data bus of the GPIB interface 5 (data bus 7 corresponding to al), a data byte transfer control bus (data byte transfer control bus 72 corresponding to bj, and an interface management bus FC). A sofa 73 is provided for interface management corresponding to the above.

The GPTB adapter circuit 7 is used to control the operations of the controlled devices 2 (1) to 2 (n) from the MPU 6 and to transfer information generated by the controlled devices 2 (1) to 2 (n). When controlling the controlled devices 2(1) to 2(n) through the control device, the control is performed based on a predetermined procedure.

Messages for controlling the controlled devices 2(1) to 2(n) are transferred from the MPU 6 through the data bus (a)', received by the data bus buffer 71 in the GPIB adapter circuit 7, and then transferred to the GPIB interface bus 5. Internal data is sent to the low data bus.

Messages on the data bus fal, which consists of eight signal lines (8 bits), are transferred using a byte serial/bit parallel method, and messages on this data bus (bl) are transferred using data byte transfer control, which consists of three signal lines. bus (by bl,
Confirmed asynchronously.

This asynchronous confirmation using the data byte transfer control bus (bl) is called a three-wire handshake, and is processed at the timing of the clock CLK, which is fixed at a predetermined speed (a speed corresponding to a predetermined signal transfer speed).

Note that the 3-wire handshake checks whether the transfer signal is valid or not, confirms whether preparation for reception of the transfer signal is completed or not, and confirms whether reception of the transfer signal is completed or not for each data byte in a predetermined order. to be processed.

When configuring a system using the GPIB interface bus 5 as described above, signal transfer speeds of 1 Kbps to 200 Kbps have come to be applied as the range of its use has expanded.

[Problem to be solved by the invention]

In the case of the above-mentioned conventional example, the three-wire handshake is processed at the timing of the clock CLK, which is fixed at a speed corresponding to a predetermined signal transfer speed.

In such a situation, if you change the signal transfer speed from the previous speed to a higher one, a slight deviation in handshake timing will cause abnormal operations such as system stoppage, and moreover, each time the transfer speed is increased, The frequency of occurrence of abnormal operations will also increase.

The present invention can achieve this without reducing the overall throughput.
Moreover, it is an object of the present invention to provide a control system for a measuring instrument using a GPIB interface that can handle any transfer speed without abnormal operation.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 60 is a computer that controls the controlled equipment based on a predetermined program, and 70 performs interface conversion to connect the computer 60 and the controlled equipment using a GPIB interface. It is an interface section, and 90 is an output clock ■ which specifies the input clock ■ in a subroutine in the computer 60.
This is a speed conversion unit that converts the handshake speed to the speed of This problem is solved by providing a designated area and equipping the controller 100 that controls the controlled devices connected via the GPIB interface with the above-mentioned means.

[For production]

The interface between the computer 60 and the controlled device is a GPIB interface in the interface section 70, and the data bus and data byte transfer control bus that constitute this GPIB interface are used to control the speed specified in the handshake speed specification area on the subroutine in the computer 60. By converting the handshake timing in the speed converter 90, it is possible to reliably prevent abnormal operations such as system operation stoppage caused by handshake troubles.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 to 4.

FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining an embodiment of the frequency dividing circuit according to the present invention, and FIG. 4 is a diagram explaining an example of the configuration of a program according to the present invention. show. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 uses an MPU 6. In this example, the GPIB adapter circuit 7 and the speed conversion section 90 are configured by a frequency dividing circuit 90a that divides the clock (2) output from the clock generator 8 at a predetermined frequency division ratio according to the designation from the MPU 6.

The clock generator 8 generates a clock ■ having one fixed speed, and the frequency dividing circuit 90a draws in the data bus (a)' and the control meter bus (b)' from the MPU 6, and the frequency dividing circuit 90a draws in the data bus (a)' and the control meter bus (b)'. Determine the timing of the transfer, divide the frequency so that the contents on the data bus (a)' at that time are transferred,
This is taken as the processing timing of the GPIB adapter circuit 7.

The program used in M P t, J 6 has subroutine branches in the main routine, as shown in Figure 4.
A predetermined area (d) on the subroutine (e+ is released to the user as an area for specifying speed.

For example, the speed can be specified by the code (5PEED shown in cl).
@Gpib; * or the maximum speed (-clock speed generated by clock generator 8) without specifying the transfer speed, for example, 5PEED shown in the sign (dl) @Gp
If ib;A, the transfer speed is (1/2) of the maximum speed A
It will be specified as double.

Note that @Gpib represents the GPIB Has I10 bus, and the value of variable A is valid from 0 to 8. Such a specified statement is set so that the area is released to the user and can be used in accordance with the equipment that the user has.

According to this statement, the frequency dividing circuit 90a converts the speed of the clock (2) generated by the clock generator 8 at a predetermined frequency division ratio.

That is, as shown in FIG.
)' controls the 4-bit data transferred at (
b) It is latched into the launch circuit 93 at the timing of the signal transferred from '.

Then, the upper 3 bits of the launch outputs of the 4 pins are sent to the control terminals A-C of the selector circuit 94, and the remaining 1 bin I.
is sent to the gate terminal G of the selector circuit 94 and one input terminal of a NAND circuit (hereinafter referred to as a NAND circuit) 95.

The clock ■ generated by the clock generator 8 is divided into four timing signals by the first stage shift register circuit 91 of two shift register circuits 9192 connected in series, and the final timing signal is sent to the next stage. The shift register circuit 92 similarly divides the signal into four timing signals, and sends them to the terminal DO-D7 of the selector circuit 94, making a total of eight timing signals.

One of these eight timing signals is selected depending on the content of the launch output input to the control terminals A-C, and the NAND
The output of the circuit 95 is NANDed by a NAND circuit 96, and the result is sent out as a clock (2) having a timing to be used by the GPIB adapter circuit 7.

By using this clock ■ in the GPIB adapter circuit 7, it is possible to control the controlled devices 2 (1) to 2 (n) at a transfer rate suitable for the controlled devices 2 (1) to 2 (n). .

In addition, the statement that specifies this speed can be specified for each controlled device 2 (1) to 2 (n), so the controlled device 2 (1) to 2 (n) that requires control at different speeds can be
Even if 1) to 2(n) are arbitrarily connected, it is possible to configure a system without reducing the overall throughput.

In the case of the frequency dividing circuit 90a of this embodiment, it is possible to divide the transfer rate by a maximum of 1/256 times.

[Effects of the Invention] According to the present invention as described above, it is possible to reliably prevent a system stoppage due to handshake timing due to an increase in transfer speed by a simple method, and the GPIB interface can be applied more widely.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining an embodiment of the frequency dividing circuit in the present invention, and FIG. 4 is a block diagram explaining the invention in detail. FIG. 5 is a diagram illustrating a conventional example of a system connected by a GPTB interface, and FIG. 6 is a diagram illustrating a GPIB adapter circuit. In the figure, L 100.100a is the controller, 2(1) to 2(
n) is a controlled device, 5 is a GPIB interface, 6 is an MPU, 7 is a GPIB adapter circuit, 8 is a clock generator, 60 is a computer, 70 is an interface section, 71 is a data bus buffer, 72 is a data byte transfer control buffer; 73 is an interface management buffer; 90 is a speed converter; 9L92 is a system register circuit; 93 is a launch circuit; 94 is a selector circuit; 95.
96 represents a NAND circuit;

Claims (1)

[Claims] GPIB (General Pur
The present invention is a system for controlling a plurality of types of controlled devices using a pose Interface Bus) interface, comprising: an interface unit (70) for converting an interface on the output side of the computer (60) to the GPIB interface; A subroutine within the computer (60) in which a procedure for controlling handshake between the computer (60) and the controlled device on the data byte transfer control bus constituting the interface is set;
An area for specifying a handshake speed is provided, and a speed conversion unit (90) is provided for processing the processing timing in the interface unit (70) at the speed when the speed specified in the handshake speed specification area is set. , a clock that determines the handshake speed between the computer (60) and a plurality of types of controlled devices, and an input clock ( [1]) is an output clock ([2]) converted by the speed converter (90).