JPH028319Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an electronic musical instrument that displays the current or remaining number of memory steps in a memory when musical tone data is written in the memory in advance.

In recent years, musical tone data of an arbitrary song can be preset into memory using keys on a keyboard, and then this preset musical tone data can be sequentially read out.
An electronic musical instrument that automatically plays the above songs has been developed. In this case, each piece of music data is sequentially written to each step of the memory.

By the way, in conventional electronic musical instruments of this type, when the memory overflows, a confirmation sound is emitted to notify this condition, or a confirmation sound is emitted at a predetermined step, and furthermore, a confirmation sound is emitted at each predetermined step and at the time of overflow. In some music players, the number of remaining steps that can still be written into the memory is notified to the performer by lighting up a display or the like.

However, in the above method, it is not possible to visually check the current or remaining number of steps one by one, so the number of remaining steps must be counted each time and written into the memory, which is cumbersome.

This idea was made in view of the above points,
Each memory step is displayed by the display means, and the current number of steps or the remaining number of steps can be checked at any time. Furthermore, when the current number of steps or the number of remaining steps reaches a predetermined number, the display state is changed. For example, it is an object of the present invention to provide an electronic musical instrument that notifies the user that an overflow is about to occur by switching from a lighting state to a blinking state.

An embodiment of this invention will be described below with reference to the drawings. FIG. 1 shows the circuit configuration of the electronic musical instrument of the above embodiment. In the figure, a key matrix 1 is made up of key switches for each key on a keyboard (not shown) arranged in a matrix, and is connected to a CPU (central processing unit).
Key scan signal SC periodically output from 2
The on/off state of each key is detected. In response to this, a key code signal KD is output from the key matrix 1 and applied to the CPU 2. The CPU 2 processes the input key code signal KD, determines the on/off state of each key, and generates determination data. In addition, this CPU2 has other
Various operations of this electronic musical instrument are controlled, but a detailed description of the functions will be omitted.

The switch section 3 is comprised of various switches provided near the keyboard of the electronic musical instrument. Examples of the above-mentioned switches include a rhythm designation switch, a volume switch, a tone designation switch, an autoplay switch, an end chord input switch, a one-key play switch, a mode changeover switch, and the like. Further, the mode changeover switch has a changeover position for each mode: power-off mode, record mode, and performance mode. The outputs of the auto play switch, end code input switch, and one key play switch are outputted from the switch unit 3 as a signal AUTO, a signal END, and a signal 1key, respectively, and are applied to the CPU 2 for processing. Further, when the record mode is set by the mode changeover switch, a signal REC is output from the mode changeover switch and is applied to the transfer gate 4 as a gate control signal. Further, the signal 1key is applied as a drive signal to a tone length counter 5, which will be described later, via this transfer gate 4.

Note that the CPU 2 is provided with registers and registers used when presetting music data into the RAM (random access memory) 6, the details of which will be described later.

As mentioned above, the RAM 6 is a memory in which musical tone data of a predetermined song is written and stored.
In this case, musical tone data is written using keys on the keyboard. Also, RAM6 is 0 to 240
The musical tone data is sequentially written into each step starting from step 0. Each operation of reading and writing musical tone data to the RAM 6 is controlled by a read/write control signal R/W output from the CPU 2. Further, the designation of the address of the RAM 6 (that is, the designation of each of the above steps) is performed by inputting the count value data of the address counter 7 via the bus line B1. And the above address counter 7
A +1 signal is output from the CPU 2 every time one step is completed, and the contents are incremented.

When writing musical tone data of a predetermined song to RAM6,
First, pitch data is input by operating keys on the keyboard. In this case, pitch data is output from the CPU 2 to the bus line B2 and written to the RAM 6 for each key operation. At the same time, the data (number of steps) in the register in the CPU 2 is output to the bus line B3 and applied to the determining section 8 and latch 9. Therefore, the judgment unit 8 determines that the number of steps is 230.
This is a circuit that determines whether it is a step or a 241 step.If it is a 230 step, it outputs the signal OB, and if it is a 241 step, it outputs the signal OV.
Give each to CPU2. On the other hand, the latch 9 latches the number of steps and provides it to the decoder 10, so that the decoded output of the decoder 10 is transferred to the display section 11.
The number of steps given is displayed. Incidentally, the pitch data written to the RAM 6 is simultaneously supplied to the musical tone creation section 12 via the bus line B4, and a musical tone is created. Then, the sound is emitted from the speaker 13. For this reason, it is now possible to confirm by ear whether the input musical sound data is accurate or not.

After inputting a series of pitch data for a predetermined song according to the musical score as described above, the end code input switch is finally operated to input an end code. This end code is stored in a register within the CPU 2, and is also stored in the step next to the step in which the last musical tone data is stored in the RAM 6.

After writing the pitch data to the RAM 6, write the pitch data for each pitch data by operating the one-key play switch. in this case,
First, the address counter 7 is reset, and then the one-key play switch is sequentially operated for each tone length data. In this case, the operation signal 1key of the one-key play switch is transmitted to the tone length counter 5 through the transfer gate 4 which is opened by the signal REC.
is applied to. The tone length counter 5 is driven by the operation signal of the one-key play switch and performs a time counting operation only while the operation signal is being applied. The time measurement data CO is taken into the tone length data storage section 14A of the buffer 14 via the bus line B5 when the one-key play switch is turned off. So Batsuhua 14
The corresponding pitch data read from the RAM 6 is simultaneously stored on the bus line B in the pitch data storage section 14B.
Therefore, the above-mentioned accurate pitch data is written to the same step of the RAM 6 again via the bus line B7 together with the pitch data.

Note that a read signal RD is output from the CPU to the buffer 14 when the one-key play switch is turned off, and as a result, the pitch data corresponding to the note length data is transferred to each section 14A, 1 of the buffer 14, as described above.
4B respectively. At the same time, a reset signal R is output from the CPU 2 to the note length counter 5, and the note length counter 5 is reset. As a result, preparations are made for writing tone length data to musical tone data in the next step. Furthermore, when writing the above-mentioned tone length data, the musical tone data read from the RAM 6 is given to the musical tone creation section 12 via the bus line B6, CPU 2, and bus line B4, and a musical tone for confirmation is emitted. be done.

When performing automatic performance by sequentially reading out the musical tone data of a predetermined song written to the RAM 6 as described above, the musical tone data from the RAM 6 is transferred to the bus line B.
6. It is sent to the musical tone creation section 12 via the CPU 2 and bus line B4. Furthermore, tone length data in the musical tone data is provided to the coincidence circuit 15 via the bus line B6. On the other hand, this coincidence circuit 15 inputs the clock data C ₀ of the tone length counter 5, compares the tone length data with the clock data C ₀ , and when they match, generates a coincidence signal eq and supplies it to the CPU 2. At this time, the CPU 2 outputs a reset signal R to clear the note length counter 5, and at the same time outputs a +1 signal to the address counter 7. In this way, the address counter 7 is incremented while comparing the note length data read from the RAM 6 and the time data of the note length counter 5, and automatic performance is executed. Also
Data from the RAM 6 is also given to the CPU 2, and various processes are executed to detect the end code and to end the performance of the song at the time of detection.

The display unit 11 is composed of, for example, a liquid crystal display device, and as shown in the figure, three digits are displayed using, for example, date-type liquid crystal display segments. Further, data for specifying the digit of the display section 11 is outputted from the CPU 2 to the bus line B8, and is applied to the decoder 16. That is, the decoded output of the decoder 16 is applied to the display section 11 and digit selection is performed sequentially. Furthermore, the judgment unit 8
After the 230th step is detected and the signal OB is output, the signal FL is output from the CPU 2 and applied to the decoder 16. As a result, each digit of the display section 11 is configured to start executing a flashing display operation. Furthermore, when the judgment unit 8 detects the 241st step and the signal OV is output, the CPU 2 outputs the signal OV.
BZ is output and given to the musical tone creation section 12. As a result,
The musical sound creation unit 12 then starts creating a buzzer sound,
It is configured to notify the overflow state of the RAM 6.

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 to 4. First, the operation of writing pitch data to the RAM 6 will be explained with reference to FIGS. 2 and 4. In this case, operate the mode changeover switch to set the record mode. At this time, a “1” level signal REC is output from the switch section 3,
Transfer gate 4 is opened. Further, the address counter 7 is reset and the 0th step of the RAM 6 is addressed. Furthermore, the _CPU is
The registers within 2 are cleared. Another step
The data in this register is outputted to the bus line B3 by the process of _S2 , latched by the latch 9, decoded by the decoder 10, and provided to the display section 11. Further, digit designation data is periodically outputted from the CPU 2 to the bus line B8, and digit selection on the display section 11 is performed. As a result, the current number of memory steps, ie, 0 steps, is displayed on the display section 11, as shown in FIG. 4a.

The process in step _S3 is the process of determining whether or not a key on the keyboard has been turned on.The process in step _S3 is repeated from the moment you look at the musical score until you operate the key for the first musical note. , display section 1
The display state of No. 1 remains unchanged as shown in FIG. 4a.

Next, when the key for the first musical tone is turned on and the pitch is input, this key-on operation is judged by the CPU 2, and the process proceeds from step _S3 to step _S4 .
Then, the key input data is input to the register, and then a judgment operation is performed to determine whether the data in the register is an end code. Of course, there is no end code input at this point, so the process advances to step _S5 , and the data in the register is transferred to 0 in RAM via bus line B2.
Transferred to step and written.

Further, through the processing in step _S6 , the CPU 2 increments the data in the register by +1, and advances the step to the next first step. Along with this, the CPU 2 also outputs a +1 signal to the address counter 7, sets the content to 1, and increments the address counter 7.

Next, in step _S7 , sound emitting processing is executed for the first musical tone (contents of the register) written in step 0 of the RAM 6. Therefore, the first musical tone is emitted, and it can be confirmed by ear whether or not the input has been made correctly.

It is determined in step _S8 whether the key of the above-mentioned first tone has been turned off. When the above key is turned off, the first musical tone stops emitting, and the next step _S9 updates the data in the register.
The determining unit 8 determines whether the data has 230 steps or more. Since there is now one step and there are less than 230 steps, the process returns to step _S2 , and the data in the register is displayed on the display section 11 in the same manner as described above.

FIG. 4b shows the display state of the display section 11 and the state of the data in the RAM 6 at this point. That is, the next incremented 1 is displayed on the display section 11.
The steps will be displayed. Further, pitch data of the first musical note is stored in step 0 of RAM6. In this case, the pitch data is expressed as 6-bit data as shown in the figure, the upper 2 bits of which indicate the octave, and the lower 4 bits of which indicate the pitch name, but a detailed explanation of this pitch data will be omitted. .

Thereafter, each process of steps _S3 to _S9 and _S2 is executed in the same way for each key operation, and while the contents of the register and the address counter are both incremented, a sound is output for each step after the first step. High data is written sequentially. And display part 1
1, each step number is sequentially displayed. Figure 4c
The pitch data for one step is written, and the pitch data for one step is written.
Shows the status when returning to _S2 .

When the data up to the 228th step is written as described above and the process returns to step _S2 , the screen shown in FIG.
As shown, the next step 229 is displayed on the display section 11. Then, when the pitch data of the 229th step is input, the process proceeds to step _S9 through each process of steps _S3 to _S8 . During this time, the data in the register becomes 230 due to the processing in step _S6 , and this data 230 is given to the judgment section 8, so the judgment section judges the 230 step and outputs a signal OB of "1" level. It is given to CPU2.

On the other hand, in step _S9 , the data in the register is
It is determined that it is 230 or more, then step S ₁₀
Proceed to. In this step _S10 , it is determined whether the data in the register is greater than 240 or not. The data in the register is now less than 240, so the process advances to step _S11 . As a result, CPU2
Since the signal FL (level "1") is outputted from and applied to the decoder 16, the display at step 230 currently displayed on the display section 11 starts a flashing display as shown in FIG. 4e. Therefore, it is reported that the number of remaining steps in RAM 6 is now 10. Also, after step _S11 above, the process returns to step _S3 , and 231
The step is in a state where it is waiting for data to be written.

Writing of data from step 231 to step 239 is executed by repeating each process of steps _S3 to _S11 . During this time, the display section 11 continues to display flashing images.

When 240 is displayed on the display unit 11, that is, when the data in the register is 240, if you write the next data, the data for the 240 step will be written to the RAM 6, and the data in the register will be
It becomes 241. Then, in the process of step _S10 , it is determined that the data in the register is greater than 240, and the process proceeds to step _S12 . As a result, the CPU
A signal BZ (“1” level) is outputted from 2 and given to the musical tone creation section 12. Therefore, a buzzer starts to sound, the overflow state of the RAM 6 is notified, and further data input is prohibited, and the series of processing ends.

On the other hand, if writing of the pitch data is completed before reaching the 240th step, for example at the 229th step, the end code input switch is finally turned on. At this time, the signal END (“1”) is sent from the switch section 3.
level) is output and given to the CPU 2, and in response, an end code (6-bit all "1" data) is input to the register. For this reason, the steps
The input of the above-mentioned end code is determined by the processing in _S4 , and the end code is written to the next step (step 230 in the above example) of the pitch data written last in RAM 6, and a series of processing is carried out. finish.

Next, referring to FIG. 3, an explanation will be given of the operation of inputting tone length data for the pitch data described above by operating the one-key play switch. In this case, the mode changeover switch continues to be set to record mode. Therefore, transfer gate 4 is opened. The address counter 7 is also cleared, and the process of step _S21 shown in the flowchart of FIG. 3 is executed to clear the register. This causes the 0 step of RAM6 to be addressed. Also, the process of step _S22 is executed,
The display section 11 displays 0 steps. The state is shown in FIG. 4a. This prepares the device for inputting tone length data. Note that FIG. 4 also shows the case of this pitch data input operation as well as the pitch data input operation described above.

Next, when you turn on the one-key play switch to input accurate note length data for the first musical tone, the output signal 1key (“1” level) is sent to the CPU 2.
The output signal 1key is applied to the tone length counter 5 via the transfer gate 4 while the process of step _S23 is executed.

In step _S23 , the ON operation of the one-key play switch is detected, and after the judgment process in step _S24 is completed, the process proceeds to step _S26 . As a result,
A reset signal R is output from the CPU 2, the clock data CO of the tone length counter 5 is cleared, and counting operation is started. Next, in step _S27 , the determining section 8 determines whether the data read from step 0 of the RAM 6 is an end code. The first musical tone data is stored in the 0th step, and this musical tone data is supplied to the musical tone creation section 12 via the bus line B6, CPU2, and bus line B4. As a result, the first musical tone is created and emitted by the process of step _S28 . Furthermore, the register is incremented by the process of step _S29 , and its data becomes 1. Note that the pitch data read from the RAM 6 is stored in the pitch data storage section 1 of the buffer 14.
It is input for 4B.

When the one-key play switch is turned off when the exact time corresponding to that note has elapsed for the first musical tone, the signal 1key goes to the "0" level, and as a result, the above-mentioned off operation is detected by the process of step _S30 . Also, the time counting operation of the tone length counter 5 is stopped, and then a read signal is sent from the CPU 2 to the buffer 14.
RD outputs. Therefore, the timing data for the first musical tone is read into the timing data storage section 14A,
At the same time, the corresponding pitch data is stored in pitch data storage section 1.
4B. As a result, the above-mentioned time measurement data and pitch data are given to the 0 step of the RAM 6 via the bus line B7, that is, the accurate tone length data and pitch data of the first musical tone are written to the 0 step. It turns out.

Next, after processing step _S31 , the process returns to step _S22 , and as shown in FIG. 4b, the next step 1 is executed.
The steps are displayed on the display section 11.

The tone length data writing operation for each step up to step 229 is similarly executed by repeating steps _S22 to _S31 . During the processing of step 229, if the data in the register becomes 230 in step _S29 , the next step is
At _S31 , the data 230 in the register is determined by the determination unit 8, and a signal OB of "1" level is output. Therefore, as explained in the pitch data writing operation, as shown in FIG. 4e, the display section 11
Thereafter, a flashing display is performed.

Further, when the data in the register becomes 241, the data 241 in the register is determined by the determining section 8 in step _S32 , and the signal OV of the "1" level is determined.
is output and a buzzer sound is emitted.

With the above operations, the tone length data writing operation is completed. Thereafter, when the mode changeover switch is set to the play mode and the autoplay switch is turned on, musical tone data are sequentially read out from the RAM 6 and the music is automatically played. In this embodiment, a normal display is performed up to a predetermined step, and a flashing display is performed after the predetermined step, so that there is an advantage that memory overflow countermeasures can be reliably taken. In addition, in the above example
Although the capacity of RAM 6 is set to 241 steps, this capacity is not limited to the above capacity but may be arbitrary. Further, the step of starting the flashing display is not limited to the above embodiment, but may be arbitrary. Furthermore, in the above embodiment, for example, 230
Although the flashing display starts when the number of steps exceeds 230, it is also possible to display the flashing until it reaches 230 steps and stop the flashing display after 230 steps. It is only necessary to make the display states different from each other, so it is not limited to the method of executing or not executing the flashing display, but also by changing the display position or displaying other display objects together, etc. It is possible to distinguish the information using various methods. Furthermore, although the number of steps is displayed in the form of counting up sequentially from 0, the present invention is not limited to this, and a method of displaying the maximum number of steps first and counting down may also be used. In this case, steps S ₁ and S ₂₁ are first set to 241, and the register values are set to 1 in steps S ₆ and S ₂₉ .
All you have to do is bring them down one by one. Furthermore, the display is flashed when the register value reaches, for example, 10, and the steps S ₉ , S ₁₀ , and
All you have to do is change the contents of S ₃₁ and S ₃₂ .

As explained above, this invention is an electronic musical instrument in which musical tone data is written in advance in a memory, and then the musical tone data is read out from the memory to perform automatic performance. Since we have provided an electronic musical instrument that constantly displays the current number of steps or remaining steps in the memory where data is written, you can easily check the remaining steps that can still be written to the memory and prevent memory overflow. It can be prevented. Therefore, there is an advantage that there is no need to write or redo a write operation due to an overflow. Also, when the current number of steps or the number of remaining steps reaches a predetermined number of steps, the steps are displayed in a different state than before.
For example, if a lighting display is performed up to a predetermined step and a blinking display is performed after the predetermined step, the memory overflow can be detected immediately before it occurs, which has the advantage that sufficient countermeasures can be taken against the overflow.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an electronic musical instrument according to an embodiment of this invention, Fig. 2 is a flowchart explaining the operation of writing pitch data to the memory, and Fig. 3 is an explanation of the operation of writing pitch data to the memory. FIG. 4 is a flowchart illustrating the display state of the display section and the storage state of the memory at the time of each write operation of pitch data and pitch data to the memory. 1...key matrix, 2...CPU,,
...Register, 3...Switch section, 4...Transfer gate, 5...Tone length counter, 6...
RAM, 7... Address counter, 8... Judgment section, 9... Latch, 10... Decoder, 11...
Display section, 12... Musical tone creation section, 13... Speaker, 14... Buffer, 15... Matching circuit, 16
...Decoder, B1 to B8...Bus line.

Claims (1)

[Scope of Claim for Utility Model Registration] A memory in which musical sound data is sequentially written over a plurality of steps and stores the musical sound data, and the number of memory steps used up to now or the remaining memory when writing the musical sound data to this memory. a display means for displaying the number of memory steps of the display means; a display control means for controlling the display operation of the display means; and a musical sound generating means for reading the musical tone data from the memory and generating and emitting a musical tone corresponding to the read musical tone data. In the electronic musical instrument, the display control means further determines whether the number of memory steps used so far or the number of remaining memory steps displayed on the display means has reached a predetermined number of steps. a detection means for detecting the number of memory steps; and when the detection means detects that the number of memory steps used so far or the number of remaining memory steps has reached a predetermined number of steps, the display of the number of memory steps is changed to the predetermined number of steps. 1. An electronic musical instrument comprising display mode control means for controlling a display mode to a display state different from the display state up to the point where the display state is reached.