JPH0281581A - Multiscreen generating circuit - Google Patents

Abstract

PURPOSE: To select and display various images by converting an A/D clock by means of screen selection information, controlling a window control signal and loading address values obtained by dividing a memory area by the window control signal. CONSTITUTION: Screen selection information is received and the A/C clock is converted by information and the window control signal is controlled. The address values obtained by dividing the area of the memories DM1-DM5 by the window control signal are loaded and various screens (one screen, four screens, nine screen, thirteen screens and sixteen screens) are freely selected and displayed. Furthermore, an analog video is mixed into digital video output and therefore the two screens and a PIP function are realized. At the time of display, two screen sources can vertically be viewed and a vertical line is horizontally moved. Thus, scroll function is realized. Thus, a multiplex image source can freely be displayed on one monitor by the selection of a user.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital video signal processing circuit in color television receivers and videotape recorders, and in particular to a digital video signal processing circuit that can process from 4 to 16 image sources depending on the size of the monitor and at the user's choice. This invention relates to a multi-screen generation circuit that can display multiple screens on one monitor, and when used for multi-channels, can freely select even if the number of broadcast channels differs depending on the region.

Conventional technology and problems In general, as part of the trend of high V4 technology in color television (C'rV) and video tape recorders (VTR), multiple screens are being displayed on one monitor in Europe, America, and Japan. New technologies are being announced on products. The multi-screens that appear on the above technology are 4
It has the function of displaying one or more types of multi-screens according to the specifications of each company, such as 9-screen, 12-screen, 16-screen, etc.

However, conventionally there were 4 screens, 9 screens, or 12 screens.

The 16 screens were fixed to one or two types on one display for each mode, and the selection range was narrow due to the size of the monitor, and scrolling of the screen was impossible.

Means for Solving the Problems Therefore, the object of the present invention is to
Another object of the present invention is to provide a circuit that can freely display multiple screen sources corresponding to 1 screen, 9 screens, 13 screens, and 16 screens on one monitor according to the user's selection. The purpose of the above is to provide a circuit that can freely select the number of broadcast channels according to the number of channels when the number of broadcast channels differs depending on the region when using multi-channels.

Example The present invention will now be described in detail below with reference to the accompanying drawings.

FIG. 1 is a system block diagram applied to the present invention, in which a video signal is separated into R-Y, BY, and Y signal stations in a demodulator, f'sc is trapped in a color-difference signal trap, and a controller is integrated.
~The roller receives a control 11 signal and a clock signal from the microcomputer based on screen selection, and generates limp ring clock signals (ADCLK, DACLK) through 7-channel log/digital conversion and conversion by the digital/analog converter.

The digitized data of the analog/digital converter is processed through the controller and converted into f1 albo.
1- The screen selection information is stored in the main DMI to DM4, and the digital/analog converter DAI to D△ reads the video signal for multi-screen stored in the dual port memory r) M1 to DM4. 3, and encoded by one encoder in synchronization with the bus l-gate pulse of the controller, so that the composite video signal is configured into a multi-screen.

FIG. 2 is a block diagram according to the present invention, in which a synchronization signal from the synchronization generator 1 and multi-screen mode command data and control signals from the input terminal of FIG.
Receive and decode screen selection information through 4c+
, 9p, 13p.

A command decoding unit 10 that generates a 16D signal, and image digital data for display on various multi-screens are divided into areas for each screen and are divided into areas according to the screen f] Alpo 1 in FIG. 1 above.
~Write row/column and read row/column address signal generation circuits 21-2 that generate write/read address signals to write and read from memories DM1-DM4
an address signal generating section 20 consisting of an address signal generating section 20, which is composed of an address signal generating section 4; a reference signal generation circuit 30; and a write row/column address of the address signal generation section 20 that receives the vertical sampling interval signal of the write reference signal generation circuit 30 and the screen selection information of the command decoding section 10 and is written together with the screen information. Signal generation circuit 2
A write screen control unit 140 that controls address generation of data to be written by specifying 1.22, and a horizontal synchronization signal separated by the video signal of the synchronization generation unit 1 and a 4×3.58MHz basic clock terminal 4fSC. In response to the signal and the above screen selection information of the cloak decoding unit 10, the above 1, 4, 9° 13.16 screen, 40.
4x above by 9p, 13D, i6p6p 3.58
An analog/digital conversion clock generation section 188 that divides MHz to generate clock signals for the analog/digital conversion section shown in FIG. 1, and controls address signals generated by writing and reading from the address signal generation section 20. The dual port memories DM1 to DM shown in FIG.
The first ?4 that feeds the address signal of ?4? A multiplexer 60 controls the digitally converted signal A/D of the video signal and serial brightness and color data to the dual port memories DM1 to DM4. 2nd degree Y8,
A value/parallel converter 50 that converts and outputs parallel data to YB and color C ends, and the analog/digital conversion clock 9
A limp ring clock signal for digital data conversion of a video signal by screen selection of the output 188, a clock signal of the write reference signal generation circuit 30, and a read enable and read start signal of the dual port memory of the write reference signal generation circuit 30. Based on this, it generates first and second brightness and color signal selection control signals for the serial/parallel converter 50 and address switching and data transmission signals for the first multiplexer 60, and outputs the R/CASC of the dual port memory.
R OW/ Column Δdress 3 tr
obe), WE(Wr+tc Enable
), a write timing generator 70 that generates a DT double signal to execute transmission control to the register of the serial port, and a horizontal synchronization signal of the synchronization generator 1 and a reference clock edge 4t.
'sc signal, generates a gate pulse to verse 1 in FIG. 1 and a clock signal for the digital/analog conversion section, generates a serial clock signal for the dual port memories DM1 to DM4, and generates a control timing signal by pig lead. The read timing generation circuit 80 and the read row/column address generation circuit 23.2/1 of the address signal generation section 20 output multiple screens at the address specified by the generation by the serial clock SC signal of the read timing generation circuit 80. The clock signal causes the first . Second brightness Y8.

The latch section 90 latches separately for YB and color 〇, and the data in the latch section 90 is mixed by the control clock of the read timing generation circuit 80 and output to the digital/analog conversion section in FIG. It is composed of a multiplexer 100.

FIG. 3 is a detailed circuit diagram of the analog/digital conversion clock generation section 188 of FIG. 1 according to the book, in which the reset terminal 41. Reference clock 4rsc end 42. Horizontal open end 43. The first and third screen selections 9p, 4p, and 16p 44, 45, and 46 are connected, and from the reset terminal 41 to the inverter N11. N+2
The output after passing through and the output from the horizontal open end 43 are AND gate A.
When input to N u, the outputs to the AND gates i to 8 N are input to the D flip-flops DPII-DPI2 to initialize all systems, and the first screen selection terminal 44 is connected to the NAND gate NA The input terminal of the NAND gate N A +2 is connected to the input terminal of the NAND gate N A +2 through the inverter N+3, and the input terminal of the NAND gate N A n to N A
+2 output terminals are connected to the input terminals of AND gate NA and +3, and the output terminal of the NAND gate NA +3 is connected to the data terminal of the D flip 70 tube DFn, and the output EQ of the D flip knob DFu is connected to the input terminal of the AND gate NA +3. NAND gate NA
15 to 1 alistic OR gate hEXOn+7) is connected to the input terminal, and the output terminal σ of the above D-norm flop DFn is connected to the above N
The input terminals of the AND gates h N A u and N A 12 are connected, and the output terminal of the exclusive OR gate EX Ou is connected to the D flip-flop D through the inverter N +3.
Connect to the data of F +2 @D and perform the above D flip 70
The output EQ of Tsubu DPI2 is the exclusive OR gate EX
Connected to O++ and the input terminal of NANO gate NAl4,
The output terminal σ of D F12 is connected to the above NAND gate NAl4.
is connected to the input terminal of DF12, and the output terminal σ of DF12 is connected to the above NAND
It is connected to the input terminal of the gate N A ++, and is connected to the input terminal of the gate N A ++. Second
The screen selection board ends 44 and 45 are connected to the input end of the OR gate ORn, and the output end of the OR gate 0R11 and the first screen selection end 46 are connected to the input end of the NOR gate NOR+2;
The above OR gate 0R11 and NOR gate NOR+2
The output terminals of the NAND gates NA+s and NΔ16 are respectively connected to the input terminals of the NANO gates NA14 to N
The A I6 output generates a signal at the clock output terminal 47 by converting the analog video signal into a digital signal by selecting multiple screens through the NAND gate N A +y. FIG. 4 is an operation timing diagram of FIG. 3 according to the present invention, in which the 48 waveform is the input signal 4fSC of the reference clock end 42, the 4b waveform is the human input signal of the reset end 41 or the horizontal open end 43, and the 4C waveform is the input signal of the reference clock end 42. When the logic of the first to third screen selection terminals 44, 45, and 46 is high, low, or low, the waveform is N when writing 9 screens.
This is the output signal of the AND game h NΔ17, and the 4d waveform is the input logic of the 1st to 3rd screen selection board ends 44, 45° 46, and the 45th end is "high" and the 44th and 46th ends are "low".
If , it is the output signal of NAND gate N A 17 when writing the 13th screen of the 13th screen, and the 4e waveform is the input logic of the 1st to 3rd screen selection terminals 44.45°46. If the 46 end is "high" and the 44.45 end is 0, it means that there are 16 screens, or it is the output signal of the NAND gate N A +7 when writing the 1st and 2nd screens of 13 screens.

FIG. 5 shows the D Noritub flop 0F of FIG. 3 according to the present invention.
II, is a transition diagram of the counting state generated at the output end of DPI2.

FIG. 6 shows the pop-up screen control section 140 of FIG. 1 according to the present invention.
2 is a specific circuit diagram of the first to fourth screen selection signals 4ρ, 9p, 13p, and 16p terminals 141 to 14 of the cloak decoding unit 10 in FIG.
4 AND gates AN+ to AN4,
The output terminals of the AND gates AN1 to AN4 are connected to the input terminal of the NOR gate NOR+, and the NOR gate NOR+ is connected to the input terminal of the NOR gate NOR+.
The output terminal of + is connected to the data output of D flip DF+ and the enable terminal EN of counter CNT+,
The output PaQ of the D flip-flop DF+ is input to the OR gate OR+ together with the output of the inverter Δ140, and the output of the OR gate OR+ is the AND gate AN5.
The input terminal of the reset terminal 145. Multi-screen conversion signal end 1
4G, the output terminal of the AND gate AN5 inputs the reset signal of the counter CNT+,
The reset @147 and vertical synchronization signal 148 are input to the reset R and clock tcK signals of the counters CNT2 and CNT3, and the output terminals QC, QD, or QΔ~QC of the counters CNT2 and CNT3 are input to a multiplexer.
Connected to the input terminal of MDX+, and connected to the above multiplexer MU
The output signal of the output terminal Q of X+ is connected to the clock terminal OK of the D-norm flop DF and the input terminal of the OR gate OR+ via the clock terminal CK of the counter CNT+ and the inverter N140.

A write control signal is generated through the occupation control terminals W Co to W C3 of the output QA-QD of the counter CN lower 1, and the output of the occupation control '#J terminal W Co to W C3 is the AND gate AN+ to AN4. is configured to be input.

FIG. 7 is an operation timing diagram of FIG. 6 according to the present invention, in which 7a is the output signal of the output MQ of the multiplexer MDX1, and 7b is the output signal of the first
~Second screen selection 4p, 90 end 141. 142 and the fourth screen selection 16p pane 144 become "LOW".

7C is reset 1 end 145. Multi-screen conversion message @ end 14
7d is the control data waveform of the input terminal QA to QD of the counter CNT+, and 7e is the control data waveform of the input control tllmWCo-WC3, and 7e is the output of the counter CNT+ of the NOR gate NOR+.
This is the enable signal of 7fG, ED flip 20 tube DF + output signal of output terminal Q.

FIG. 8 is a diagram illustrating the actual configuration of multiple screens according to the present invention, 8A is an example of 4 screens, 8B is an example of 9 screens, 8C is an example of 13 screens, and 8D is an example of 16 screens. This is an example.

A specific embodiment of the present invention will be described in terms of measurement with reference to the above-mentioned FIGS. :240 lines, horizontal:372 dots When setting the standard, the band of luminance signal Y and color difference signal C is approximately 4=1, so dual port memory DM+
- Three of DM4 are used for Y (YA, YB), and two memories of the dual port memory DM+"DM<" are allocated to C (B-Y, R-Y).

The areas of the dual port memories DM+ to DM4 can be configured as shown in Table 1 below.

Table 1 Horizontal synchronization signal and reference clock end 4fsc 4×3.58
M1-11 is input to the analog/digital conversion clock generation section 188 and the interpolation reference signal generation circuit 30, and data for selecting the screen as shown in FIG. 8 (8△ to 8D) is sent to the command decoding section through the microcomputer. 10 is input. At this time, the screen selection information 4p, 9 of the command decoding 10 achieved by the screen selection command
p, 13p.

16ρ is input to the analog/digital conversion clock generation section 188 and output reference signal generation circuit 30, and at this time, the analog/digital conversion 9079 generation section 40 generates a clock signal by converting the video signal into a digital signal. Looking specifically at this in FIG. 2, we can see that the 4d signal, which is the same as the 4fsc in FIG.
+z clock signal, and the above-mentioned D flip-flops DF n to DF +2 are reset and initialized by the input signal 4b of the reset terminal 41 and the horizontal synchronization terminal 41.43. At this time, the first. Second. Third screen selection 9
An analog/digital conversion (hereinafter referred to as "A/D") clock signal is generated by the input signals of the D, 4D, and 16p terminals 44, 45, and 46 for multi-screen selection.

For example, when we consider that the reference clock for one screen is 4 f s c, the four screens in Figure 8 (8A) are viewed with the horizontal synchronization signal as the reference, and half of the clock is lost, so 2 When the frequency is divided, it is generated as shown in 4d, and the PIP and 9 screens in Figure 8 (8B) have horizontal synchronization of 1
Since this is the case when the frequency is reduced by /3, the above 4fsc is generated as shown in 4C and divided by 1/3, resulting in 1 in Fig. 8 (8D).
4f' because the horizontal synchronization of 6 screens is divided into 4
When SC is divided into 1/4, it is generated as shown in 4e, and the 13th screen in Fig. 8 (8C) is generated on the corresponding horizontal line so that the 16th screen and the 4th screen are generated in the same way. The frequency division can be done differently.

The generated clocks for generating 4p, 9p to 13p, and 16p are converted by the input logic of the first to third screen selections 9D4°45.46. In other words, NAN at the time of 9p
The output of D gate N A +7 is the third frequency divided by 3 of 4rsc.
When the screen selection 9D4 is "PAHI" and the 2nd and 3rd screen selection board ends 45.46 are "LOW", it is generated like 4C, 4p, or when writing the 13th screen of 13o. The third screen selection 9D5 is "high" and 'M1. Third
It is generated like the third option of the picture, and it is 16p, or 1 to 12 of 13p.
The third screen selection 9D6 at the time of writing the th screen is "high", and the first and third screen selections 9D4.

45 goes low and is generated as 4e.

Therefore, in FIG. 2, the horizontal circumference Jl of the AND gate ANn
l! 4 of the reference clock terminal 42 by inputting the signal terminal 43.
'r S C signal 1st to 3rd screen selection signal 44 to 4
The output fa Q of the D flip knob DF+ is divided by a predetermined frequency by the signal of the D flip knob DF+.
When the output terminal Q of F2 is Ql, Ql produces a frequency divided by 2, and 02 produces a frequency divided by 4, so when the 45 terminal is "high", it generates a clock that can create 4 screens. , the corresponding clock NAND gate that can create 16 screens when the 46 end is "high" NA 14~NA
It is output through +7. That is, when the outputs of Q+ and 02 are transitioned from θθ→1θ→01 as shown in FIG.
When the first screen selection signal terminal 44 is "high", 10FO
, O, so this is a case of frequency division by 3. However, if it is 0 or 1, 44 is "low", so it will not be 9 screens. Therefore, the counter in FIG. At this time, the frequency of 4f'SC is divided by 3 and outputted, so that A/D clocks corresponding to 9 screens are supplied.

As described above, the 13th and 16th screens are also frequency-divided by 4 f'sc and supplied to the Δ/D clock (ADCLK) signal of the analog/digital converter shown in FIG. 1, and applied to the write timing generator 70. Further, the occupation reference signal generation circuit 30 also generates the occupation start control signal and the memory write T enable signal to the write timing generation section 70 based on the screen selection information and the vertical and horizontal till signals of the synchronization generation section 1.
is applied to the writing screen control unit 140 at the same time as a vertical zigzag period signal. At this time, the timing generating section 70 sequentially selects the R-Y, B-Y, and Y signals outputted from the rear tone section in FIG. After being sampled by a clock, the signal 1 is converted into a digital signal and input to the serial/parallel converter 50.

The signal input to the serial/parallel converter 50 is inputted to the first signal by the control clock of the write timing generator 70. Second
The brightness YA, YB and color signals are separated and input to the dual port memory DfVl+"0M2. On the other hand, the write screen control unit 140 specifies the row and column addresses to be written along with the screen selection information and performs window control to do so. Generates the 2IllWCo-WC3 signal.

Looking specifically at the writing screen control section 140 in FIG. 6, the first to fourth screen selection signals 4D, 9p, and 13p.

16o terminals 141 to 144 are input to 1) fl counter CN T + output 1) aQΔ・～QD output and pull 1 spear terminal RCD output to AND gate AN+～AN
4 and generates the corresponding information through the NOR gate NOR+, but the output of the NOR gate NOR+ is 7.
The output of the output terminal Q of the D flip 70 tube OF+ is generated as shown in e, and is generated as shown in 7f. At this time, of course, reset 1 end 145. 147 in the initial state, but when the reset is finished and the conversion signal 7G is input to the multi-conversion pulse end 146, the counter CN'r I becomes the reset 1-state and other mode screens are displayed. Reset so that it jumps to . , Subsequently, the counters CN'r+, CN receive the ill signal of the vertical synchronizing signal terminal 148 as a clock signal.
'r Count in 3? Duplex (No-MUX1)
When the multi-break MUX+ is input, the counter CNT is controlled by the strobe selector one end 150 according to the command decoding signal received from the ficon.
+.

Select a predetermined output value of CNT3 and turn the counter CNT
When the corresponding window control signals W C3 to W Co are generated at the output terminal QA-〇[3 as shown in 7d, the write row/column address generation circuit 21.22
input to specify the screen selection, and the first
・-When the fourth screen selection signal terminals 141 to 144 correspond to the current count, they are reset by the AND gate NOR+ and the D flip-flop DF.CNT2,
CNT3.

The purpose of MUX+ is to vary the strobe time, and the 150 is controlled from a controller, but the initial state is MIJX+'s 4
is output, and input values from 1 to 6 are selected by time variable up and down.

The above figure 7 shows the case where 143="high", that is, 13p, and when WC3WCO is 12 (that is, the 13th screen of 13p), CNT1 is disabled.DF+ The Q of is set to 1 by delaying the output of NOR+ by 1 clock and resetting CNT.
Control signals for fill-in screens are continuously generated so that three screens can be shown on one screen.

It operates in the same way for 4ρ, 9D, and 16D.

In addition, it is written only - times and only the last screen changes continuously (state 1 where it writes from 0 to 12 and stops at 12)
In order to make it so, by setting it using the set terminal of DF+, the O output of NOR+ becomes ANs
It can be used so that it is not applied to the input. 5
Therefore, the digital video signal generated by the serial/parallel converter 50 is converted into the timing signals RAS, CAS, WE of the write timing generator 70.

The write row/column address generation circuits 21 and 22 of the address generation circuit section generate the 1st -? by DT. Dual port memory DM selected by Lunaplexer 60
Frequently used screens are written to corresponding addresses of + to DM4 for each screen selection window as desired by the user. When reading, the read control signal generated by the command decoder 10 is used to control the dual port memory DM using the main horizontal and vertical synchronization signals and the main horizontal synchronization signal.
~Read the address of DMA/generate it in the column address generation circuits 23 and 24 and send it to the first multiplexer 6.
When selecting 0, the data of the multi-screen at the corresponding address is read and outputted by the serial clock of the read timing generation circuit 80.
The data is multiplexed by the data multiplexer IQO using the υ110 clock generated by the υ110 clock. The above multiplexed data can be converted into digital/analog (
D/A) of the read timing generation circuit 80
The converted analog signal is encoded by an encoder using burst gate pulses and output as a multi-composite video signal.

Although the above embodiments of the present invention have been described with reference to 1.4, 9.13, and 16-inch multi-screens, those with ordinary knowledge will understand that the screen selection signal can be used for two screens without departing from the basic idea of the present invention. If and PIP are also applied, it is possible to easily use not only the multi-screen function but also the two-screen scrolling function and the PIP function as described below.

2-screen scrolling is basically the same as 1-screen digital video signal, but it can be divided into analog video formulas and two analog video sources can be displayed together.
In the case of that PIP, basically A/D clock like 9 screens and vertical skip (only 1H is written during 3H)
If used as a structure and only the screen position at the time of reading is specified, analog video can be mixed in the same way as scrolling, even existing PIP can be realized.

Effects of the Invention As mentioned above, the screen selection information is received and thereby A.
/D clock (, i conversion), controls the window control signal, and loads address values that partition memory areas using the window control signal to display various screens (1 screen, 4 screens, 9 screens, 13 screens, 16 screens). By freely selecting and displaying 16 screens) and by mixing analog video with digital video output, it is possible to display 2 screens and PI Pli function, and when the screen is displayed, 2 screen sources can be viewed vertically. It has the advantage of being able to provide a scrolling function by moving the vertical line horizontally.

[Brief explanation of the drawing]

1 is a system diagram applied to the present invention, FIG. 2 is a block diagram according to the present invention, FIG. 3 is a specific circuit diagram of the analog/digital conversion clock generation section 188 of FIG. 2 according to the present invention, and FIG. 4 is an operation timing diagram of FIG. 3 according to the present invention, FIG. 5 is a transition diagram of the counting state of FIG. 3 according to the present invention, and FIG. 6 is a specific circuit diagram of the fill-in screen control unit 140 of FIG. 2 according to the present invention. , FIG. 7 is an operational waveform diagram of FIG. 6 according to the present invention, and FIG. 8 is a diagram illustrating an actual configuration of a multi-screen according to the present invention. . DESCRIPTION OF SYMBOLS 1... Synchronization generation section, 10... Mantle decoding section, 20... Address signal generation section, 30... Interpretation reference signal generation circuit, 50... Serial/parallel conversion section, 60
...First? Multiplexer, 70... Write timing generation section, 80... Read timing generation circuit, 90
...Latch section, 100...Data multiplexer 188...7 Analog/digital conversion clock generation section.

Claims (1)

[Scope of Claims] A multi-screen processing circuit for a digital color television and a video tape recorder, which includes a dual port memory (DM1 to DM4), a synchronization generation section (1), and a microcomputer analog/digital conversion section. It receives a vertical synchronization signal from part (1) and multi-screen mode command data and control signals from the microcomputer, decodes it, and outputs screen selection information (4p, 9p, 1).
a command decoding unit (10) that generates signals (3p, 16p), and writes and reads the above-mentioned various image digital data for multi-screen display into the above-mentioned dual port memories (DM1 to DM4) by dividing them into respective screen areas. Row/column and read row/column address signal generation circuits (21 to 21) that generate write/read address signals as shown in FIG.
24), and a vertical and horizontal synchronization signal separated by the synchronization generation part (1) and screen selection information from the command decoding part (10), A write reference signal generating circuit (30) that generates a reference signal receives a vertical sampling interval signal from the write reference signal generating circuit (30) and screen selection information from the command decoding section (10), and writes the screen selection information together with the screen selection information. The address signal generating section (20)
write row/column absent signal generation circuit (21,
22) to control address signal generation, and a horizontal synchronization signal separated by the video signal of the synchronization generation section (1) and a basic clock end (4fsc) of 4×3. 58
MHz signal and the above command decoding section (10)
The analog/digital conversion clock receives the screen selection information and divides the 4×3.58 Hz according to the selection of the 1st, 4th, 9th, 13th, and 16th screens, respectively, to generate the analog/digital converter clock signal. Generating part (18
8), and write and read address signals generated from the address signal generator (20) are multiplexed under control to generate the dual port memory (DM).
a first multiplexer (60) that supplies the address signals of 1 to DM4); and a signal (A/D) converted into a digital signal of the video signal by the dual port memory (DM1 to DM4);
and a serial/parallel converter (50) that converts and outputs the serial luminance and color data in parallel to the first and second luminance (TA, YB) and color (C) ends under control, and the analog/digital conversion clock. Generating part (40)
The serial/parallel converter (50) receives the sampling clock signal for digital data conversion of the video signal according to screen selection and the dual port memory write enable and write start signals of the write reference signal generating circuit (30).
the first and second brightness and color signal selection control signals;
Generates address switching and data transmission signals for the multiplexer (60) and R/
A write timing generator (70) that generates a DT signal for controlling transmission to registers of CAS, WE, and serial ports, and a horizontal synchronization signal of the synchronization generator 1 and a reference clock terminal 4f.
A read that receives the signal from SC and generates the burst gate pulse and a serial signal for the digital/analog converter, generates a serial clock signal for the dual port memory (DM1 to DM4), and generates a control timing signal for data read. The timing generation circuit (80) and the read row/column address generation circuit (23, 24) of the address signal generation section (20) read the multiple screen data at the address specified by the timing generation circuit (80).
80) is output according to the signal at the serial clock end (SC), and the first and second brightness (YA, YB) are output according to the clock signal.
and a latch part (90) that latches separately for the collar (C);
A data multiplexer (100) that mixes the data of the latch section (90) according to the control clock of the read timing generation circuit (80) and outputs the mixed data to the digital/analog conversion section. Screen generation circuit.