KR920003651B1 - Background screen processing circuit of multi-screen display - Google Patents

Abstract

The circuit includes a microprocessor (10) for outputting multi- picture signals, and a memory (50) for storing brightness signals and color signals. A counter means (21) counts a certain number in synchronization with the multi-picture signals, and a control signal generating means (24) generates background color converting signals and data clear signals. A decoding means (22) outputs signals in such a manner as to output incremented number of sub- pictures each time when the counting means (21) upcounts. A latching means (31) latches first and second brightness and color signals to output them to the memory (50). A color selecting means (32) adjusts the color and brightness of the background picture.

Description

Desktop processing circuit of multi-screen display

1 is an exemplary view of a kind of multi-screen.

2 is a diagram illustrating a small screen processing procedure.

3 is a block diagram of the present invention.

4 is a detailed circuit diagram of a command decoder 20 and a data latch 30 during the third time.

5 is an operational waveform diagram according to the present invention

* Explanation of symbols for main parts of the drawings

G1, G3-G7: AND gate G2: NAND gate

G8-G10: Oagate FF1-FF5: Flip-flop

L1-L3: Latch 10: Micom

20: command decoder 21 21: counter

22: decoding unit 23: counter control unit

24: control signal generator 24: data latch unit

31: latch unit 32: desktop color selection unit

40: clock generator 50: memory

60: analog / digital converter

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a multi-screen display technology in a video tape recorder (VTR) or a television (television: TV) for processing a video signal in a digital form. When constructing a small screen when the main screen is related to the circuit processing a solid color.

In general, the multi-screen display performed on a VTR or a TV refers to displaying several small screens together on one main screen display screen. The number of multi-screens that is generally configured is 4 screens, 9 screens, 13 screens, and 16 screens. And the display state is as shown in Figs. Referring to the principle of the multi-screen display function, as shown in (e)-(h) shown in FIG. It reads the contents at once and displays them on the screen of the TV.

However, when the mode is changed to display multiscreen for the first time on a normal screen or when the type of multiscreen is changed in the multiscreen mode, the new small screen data is not recorded since it always starts from the 1st small screen of FIG. The screen data previously recorded remains. However, in the related art, since there is no proper solution for this, the memory recording state is displayed on the screen as it is, so that the small screen of the new content and the small screen of the previous content are displayed together until the small screens are filled. There was this.

Therefore, it is an object of the present invention to write a single color data in the memory for full screen display instantaneously when the first display of a multi-screen on a normal screen or when switching to another multi-screen form, and process the desktop as a single color and then An object of the present invention is to provide a background processing circuit for sequentially displaying small screens.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

영역 만큼만을 기록할 수 있도록 하는 기록 제어 신호(MCS)를 발생하는 클럭발생부(40)로 구성된다.3 is a block diagram of an embodiment of the present invention, which outputs a multi-screen signal (MULTIP) and controls the overall operation of the entire circuit as a whole, and digitalizes an analog video signal to a 6-bit video signal (AD). Analog / Digital converter 60 outputting a) and a background color conversion signal (DCLRB) and a data clear signal (DCLR) which are toggled at each occurrence of two vertical synchronization signals (DVSB), and have states opposite to each other at the same time. When the data clear signal DCLR is in the second state, the 4, 9, 13, and 16 screen generation signals 4P, 9P, 13P, and 16P are sequentially rotated whenever the multi-screen signal MULTIP is input. A commander decoder 20 for outputting, and a first luminance signal YAD, a color signal CD, and a second luminance signal YBD output from the analog / digital converter 60 according to a predetermined control signal state. Latch each of the memory 50 simultaneously. When the data clear signal DCLR is in the first state, the first luminance signal YAD, the color signal CD, and the second luminance signal YBD are initialized irrespective of the input and randomly generated for each signal. A data latch unit 30 which selects one bit of and adjusts the color and contrast of the background image by logically combining it with the background color conversion signal DCLRB having a second state, and the 4, 9, 13, and 16 screens. The data latch unit 30 is controlled by dividing the reference clock according to the input state of the generation signals 4P, 9P, 13P, and 16P, and outputting first and color second luminance latch signals YALCH, CLCH, and FBLCH. In the memory 50, one of the vertical synchronization signal generation time of the entire memory

And a clock generator 40 for generating a write control signal MCS that allows recording only as much as the area.

에서 클럭을 받도록 직렬 연결하여 수직동기 신호(DVSB)를 업카운트하는 카운터부(21)와, 상기 제 1 플립플롭(FF1)의 비반전 출력(Q1)과 상기 제 2 플립플롭(FF2)의 반전출력 및 상기 데이타 클리어 신호(DCLR)를 논리곱하여 4화면 발생신호(4P)를 출력하는 앤드게이트(G3), 상기 제 1 플립플롭(FF1)의 비반전 출력(Q1)과 상기 제 2 플립플롭(FF2)의 비반전출력(Q2) 및 상기 데이타 클리어 신호(DCLR)를 논리곱하여 13화면 발생신호(13P)를 출력하는 앤드게이트(G4), 상기 제 3 플립플롭(FF3)의 비반전 출력(Q3)과 상기데이타 클리어 신호(DCLR)를 논리곱하여 16화면 발생신호(16P)를 출력하는 앤드게이트(G7)로 이루어진 디코딩부(22)와, 상기 제 1 플립플롭(FF1)의 반전출력과 상기 제 3 플립플롭(FF3)의 비반전 출력(Q3)을 논리조합하는 낸드게이트(G2), 상기 낸드게이트(G2)출력과 초기 전원공급시 마이컴(10)으로부터 발생되는 상기 리세트 신호(RESET)를 논리곱하여 상기 제 1-제 3 플립플롭(FF1-FF3)을 초기화 하기위한 앤드게이트(G7)로 이루어진 카운터 제어부(23)로 구성된다.4 is a detailed circuit diagram of the command decoder 20 and the data latch unit 30 during the third time. The command decoder 20 is initialized to the multi-screen signal MULTP and is applied to the vertical synchronization signal DVSB. A fourth flip-flop FF4 synchronously operating as a toggle counter, preset by the multi-screen signal MULTIP, and initialized by a reset signal RESET generated from the microcomputer 10 upon initial power supply A fifth flip-flop FF5 and a fifth flip-flop FF5 for outputting a background color conversion signal DCLRB, which is kept in synchronization with the inverted output of the fourth flip-flop FF4. And a control signal generator 24 comprising an AND gate G6 for multiplying the reset signal RESET and outputting a data clear signal DCLR, and a first-third flip-flop FF1- that performs a toggle operation. Inverting terminal of FF3)

A counter 21 for up counting the vertical synchronization signal DVSB by serially connecting a clock to receive a clock, and inverting the non-inverting output Q1 of the first flip-flop FF1 and the second flip-flop FF2. An AND gate G3 for outputting the four-screen generation signal 4P by performing an AND operation on the output and the data clear signal DCLR, a non-inverting output Q1 of the first flip-flop FF1 and the second flip-flop ( AND gate G4 for outputting 13-screen generation signal 13P by ANDing the non-inverting output Q2 of FF2 and the data clear signal DCLR, and the non-inverting output Q3 of the third flip-flop FF3. ) And a decoding unit 22 comprising an AND gate G7 for multiplying the data clear signal DCLR and outputting 16-screen generation signal 16P, the inverted output of the first flip-flop FF1, and the first 3 NAND gate G2 for logical combination of non-inverting output Q3 of flip-flop FF3, the NAND gate G2 output and initial power supply And a counter controller 23 formed of an AND gate G7 for initializing the first to third flip-flops FF1 to FF3 by logically multiplying the reset signal RESET generated from the sudden microcomputer 10. .

The data latch unit 30 is initialized by the data clear signal DCLR and sequentially generated to the first luminance latch signal YALCH, the color latch signal CLCH, and the second luminance latch signal YBLCH, respectively. Latch means 31 having first to third latches L1 to L3 for synchronizing the first luminance signal YAD, the color signal CD, and the second luminance signal YBD in digital form in synchronism; First-third OR for adjusting the color and contrast of the background image by ORing the most significant bits of the first and second luminance signals YAD, YBD and the color signal CD and the background color conversion signal DCLRB, respectively. Background color selection means 32 having gates G8-G10.

5 is an operation waveform diagram according to an exemplary embodiment of the present invention, which illustrates an example of a case of entering the first multi-screen mode and changing from 4 screens to 9 screens. (T1) is a normal display section, (T2) is a background processing section that is executed before the first start of a multi-screen, (T3) is a four-screen processing section, and (T4) is a multi-screen from 4 to 9 screens. The background screen processing section is executed before changing the shape of the symbol, and (T5) is the 9 screen processing section.

In addition, the horizontal stripe indicates redundancy or don't care, and the shaded part represents image data, and the same code as that added to each signal of FIG. 3 or 4 is added to each waveform.

The present invention will be described in detail based on the above configuration.

First, a description will be given of a case in which the desktop is processed in a single color when switching from a normal display state to a multiscreen state. In the normal playback state, when the multi-screen signal MULTIP as shown in FIG. 5 is output from the microcomputer 10 of FIG. 3, the fourth flip-flop FF4 divides the vertical synchronization signal DVSB into two and outputs it through the non-inverting output stage. do.

On the other hand, the inverted output of the fourth flip-flop FF4 is applied to the clock of the fifth flip-flop FF5, and the inverted output and reset signal RESET of the fifth flip-flop FF5 are applied to the AND gate G6. Logically multiply to generate a data clear signal (DCLR). The reset signal RESET is a signal generated from the microcomputer 10 at the first power supply.

As shown in FIG. 5, the data clear signal DCLR is kept low for a period of 2V during which two vertical synchronization signals DVSB are generated to initialize the first to third latches L1 to L3. Let's do it. Therefore, all zeros are output to the output terminals of the three latches L1-L3 regardless of which state each bit of the image signal AD digitalized by the analog / digital converter 60 is input to. The background color conversion signal DCLRB generated from the non-inverting output terminal of the fifth flip-flop FF5 is in a high state. In the case of the present invention, the digitalized image signal AD is assumed to be 6 bits, and the output form is sequentially repeated the luminance signal (the first luminance signal), the color signal, the next luminance signal (the second luminance signal), and no signal for a predetermined period. do. Therefore, each of the first and third flip-flops FF1 to FF3 latches the three signals in synchronization with a corresponding latch signal, and the latched signals are simultaneously transmitted to the memory 50 during the absence of the signal.

At this time, the three OA gates G8-G10 input the ground color conversion signal DCLRB to one input terminal and logically match the most significant bit of the outputs of the first to third latches L1 to L3. That is, the first latch L1 latches and outputs the first luminance signal YAD (5: 0) of the digital form from the analog / digital conversion unit 60. The most significant bit of the output and the background color conversion signal DCLRB are output. ) Is logically summed at the first orifice G8, converted into 20 (Hex) data, and written to the memory 50. In addition, the most significant bit of each color signal [CD (5: 0]) and the second luminance signal [YBD (5: 0)] as the output of the second latch (L2) is the same as above. The second and third orifices G9 and G10 are converted into data of 20 (Hex) as a result of being ORed with the background color conversion signal DCLRB and stored in the memory 50.

In this way, when the background data is set to 20 (Hex) for both luminance and color data, the background color becomes gray. Gating is performed using the background color conversion signal DCLB to the first-third latch L1-L3 output. You can change the color and contrast of the background color as you change the state.

When gating to the most significant bit as in the embodiment of the present invention, when the digital conversion range of the luminance signal related to contrast is from 0 to 1, 20 (Hex) is 0.5, resulting in gray, and the digital range of the color signal related to color. It is well known that 20 (Hex) is 0.5 in the range of 0 to 1, so that the color does not appear at the intermediate level due to the characteristic of the color signal, and the color changes as it is converted up or down than the intermediate level.

On the other hand, the 4, 9, 13, and 16 screen generation signals 4P, 9P, 13P, and 16P output from the decoding unit 22 are the AND gates G3 generated by the data clear signal DCLR maintaining the low state as described above. It is applied to one input terminal of -G5, G7, and both are turned low. Therefore, the clock generator 40 divides the reference clock 4fsc and writes the write control signal MCS to the memory 50 so that the entire memory 50 can be written for one vertical synchronization signal generation time 1V. The latch unit 31 generates first and second luminance latch signals YALCH and YBLCH and a color latch signal CLCH.

The first and second luminance signals YAD and YBD and the color signal CD stored in the memory 50 are read in a known manner so that the first and second luminance signals are synthesized as Y and a six color signal CD is obtained. ) Is converted to RY, BY, analog converted, and then displayed on the screen.

As described above, after the multi-screen signal multip is generated at the time t1 and two vertical synchronization signals CVSB generation time 2 V elapse, as shown in FIG. 5 at the time t2 The data clear signal DCLR is converted to the high state again.

At this time, the non-inverting output Q1 of the first flip-flop FF1 is high, the non-inverting output Q2 of the second flip-flop FF2 is low, and the non-inverting output Q3 of the third flip-flop FF3. ) Is in a low state, and the AND gate G7 outputs the 16-screen generation circuit 16P in the low state by ANDing the non-inverting output Q3 of the third flip-flop FF3 and the data clear signal DCLR. do. In addition, the two AND gates G4 and G5 having the non-inverting output Q2 of the second flip-flop FF2 as one input respectively receive the 13-screen generation signal 13P and the 9-screen generation signal 9P in a low state. Output Therefore, only the AND gate G3 which inputs the non-inverting output Q1 of the first flip-flop FF1 and the inverting output of the second flip-flop FF2 in the high state receives the four-screen generation signal 4P in the high state. Will print. However, each of the 4, 9, 13, and 16 screen generation signals 4P, 9P, 13P, and 16P controls the multi-screen generation only in the high state, so that the clock generation unit inputs the four screen generation signal 4P in the high state. At 40, the write control signal MCS, the first and second luminance latch signals YALCH and YBLCH, and the color latches can record only one quarter of the entire memory 50 during one vertical synchronization signal generation time. Generate signal CLCH.

In addition, as shown in FIG. 5, the data clear signal DCLR is maintained in a high state in the period T3 when the 4 screen signal 4P is in a high state, so that the first to third latches L1 to L3 are maintained. Will behave normally. Therefore, in synchronization with the latch signals YALCH, CLCH, and YBLCH applied from the clock generator 40, the 6-bit video signal AD (5: 0) is latched from the analog / digital converter 60. Among the output signals of each of the latches L1-L3, the most significant bit of the new OA gates G8-G10 is logically combined with the background color conversion signal DCLRB. Since the background color conversion signal DCLRB is low, the logical sum result is bypassed. Therefore, a six-bit first luminance signal YAB, a color signal CD, and a second luminance signal YBD generated at the output of each of the latches L1-L3 are generated.

When the multi-screen signal (MULTIP) is input again, this is to change the shape of the multi-screen (in the embodiment of the present invention, it means 4 screen to 9 screen switching). Input the data of (Hex) so that the desktop can be processed in a single color.

After the two vertical synchronization signal generation times have elapsed after the multi-screen signal multip is generated, the data clear signal DCLR becomes high again as described above. Only the AND gate G5 which inputs and logically combines the non-inverting signals Q1 and Q2 of the first and second flip-flops FF1 and FF2 will output the nine-screen generation signal 9P in the high state. Therefore, as the clock generation unit 40 receives the nine-screen generation signal 9P as described above, each latch signal YALCH can record only one-ninth of the entire memory 50 during one vertical synchronization signal generation time. , CLCH, YCVCH) and write control signal MCS are generated.

On the other hand, when changing from 9 screens to 13 screens or changing from 13 screens to 16 screens, the same principle applies as described above, and thus detailed descriptions are omitted, and the multi-screen generating signals 4P, 9P, 13P, and 16P are sequentially processed. The operation to change to will be described in detail.

)단으로 로우상태의 신호가 인가되므로 상기 세 플립플롭(FF1-FF3)은 클리어되어 다시 000의 출력을 발생하게 된다. 부연하면, 상기 세 플립플롭(FF1-FF3)의 출력을 네 앤드게이트(G3-G5, G7)에서 디코딩하여 순서적으로 4화면, 9화면, 13화면, 16화면 신호를 발생하되, 처음에는 모두 로우상태에서 4화면 발생신호(4P)만 하이상태로 되고 다음으로 9화면 발생신호(9P)만 하이상태에서 13화면 발생신호(13P)만 하이상태로 되었다가 16화면 발생신호(16P)만 하이상태가 된 후 다시 상기 네가지 화면 발생신호(4, 9, 13, 16P)가 모두 로우상태로 된다.As the multi-screen signal (MULTIP) is generated, the outputs (Q3, Q2, Q1) of the first-third flip-flop (FF1-FF3) change from 000 → 001 → 010 → 011 → 100, and then the multi-screen signal (MULTIP) Is generated, the output of the NAND gate G2 which logically combines the non-inverting output Q3 of the third flip-flop FF3 and the inverting output of the first flip-flop FF1 becomes low. Therefore, when the NAND gate G2 output and the reset signal RESET are logically multiplied using the AND gate G1, the clear bar of the first to third flip-flops FF1 to FF3 is defined as:

In the low level, the three flip-flops FF1 to FF3 are cleared to generate an output of 000 again. In other words, the output of the three flip-flops (FF1-FF3) are decoded at four end gates (G3-G5, G7) to sequentially generate four-screen, nine-screen, thirteen-screen and sixteen-screen signals, but initially all In the low state, only the four-screen generation signal (4P) goes high, and in the next state, only the nine-screen generation signal (9P) goes high, and only the thirteen-screen generation signal (13P) goes high. After the state, the four screen generating signals 4, 9, 13, and 16P are all low again.

As described above, in the present invention, when a multi-screen is first generated in a normal screen or when switching from one multi-screen type to another multi-screen type, the background screen of the margin is first changed to a single color and then the small screen is displayed before the small screen is displayed. By doing so, there is an advantage that the previously recorded data is not displayed by monochrome processing of the portion where the new small screen data is not already recorded.

Claims (4)

A multi-screen display having a microcomputer (10) for generating a multi-screen signal (MULTIP), and a memory (50) for storing luminance and color signals, the multi-screen display device for counting a predetermined number in synchronization with the multi-screen signal (MULTIP) The counting means 21 and the control signal generating means for generating the background color conversion signal DCLRB and the data clear signal DCLR each having a state of being toggled at each time of generating the two vertical synchronizing signals DVSB and having mutually opposite states at the same time. (24) and decoding means (22) for sequentially outputting a plurality of multi-screen generating signals sequentially in the order in which the number of small screens is increased by a certain amount each time the counting means (21) up counts; A count control means 23 for clearing when the count means 21 counts the type of the multi-screen generating signal, and the first and second luminance signals YAD and YBD and the color signal DC in digital form. Latch and memo A random bit for each of the latch means 31 for outputting to the memory 50 and the first and second luminance signals YAD and YBD and the color signal DC, respectively, and the background color conversion signal ( DCLRB) in combination with the background color selection means 32 for adjusting the color and contrast of the background and the generation of one vertical synchronization signal to the memory 50 in accordance with the input state of the multi-screen generating signal (MULTIP) Of total memory for

Clock generating means (31) for generating a recording control signal (MCS) for recording only an area and outputting first luminance, color, and second luminance latch signals (YALCH, CLCH, YBLCH) to the latch means (31). Desktop processing circuit of a multi-screen display, characterized in that consisting of. In a multi-screen display having a microcomputer 10 for outputting a multi-screen signal (MULTIP), and a memory 50 for storing luminance and color signals, each of the two vertical synchronization signals DVSB is toggled and is the same. A plurality of background color conversion signals DCLRB and a data clear signal DCLR are generated at a time point, and each time the data clear signal DCLR is in a second state or the multi-screen signal MULTIP is input. A command decore unit 20 which sequentially outputs the screen generation signal while sequentially circulating, and a first luminance signal YAD and a color signal DC output from the analog / digital converter 60 according to a predetermined control signal state. And latching the second luminance signal YBD and outputting the first luminance signal YBD, the color signal DC, and the second luminance signal when the data clear signal MULTIP is in a first state. Input luminance signal (YBD) A data latch unit 30 which initializes irrespective of output power and selects a random bit for each signal and logically combines it with the background color conversion signal DCLRB having a second state to adjust the color and contrast of the background screen. And divides a reference clock according to the input state of the multi-screen generating signals to output first luminance, color, and second luminance latch signals YALCH, CLCH, and YBLCH to control the data latch unit 30, and to control the memory. In (50), one of the vertical synchronization signals is generated.

And a clock generating means (40) for generating a recording control signal (MCS) for recording only an area. The fourth flip-flop (FF4) according to claim 2, wherein the comment decoder (20) is initialized by the multi-screen signal (MULTIP) and operates as a toggle counter in synchronization with a vertical synchronization signal (DVSB). Preset to the signal MULTIP and initialized by the reset signal RESET generated from the microcomputer 10 upon initial power supply, and the signal input to the D terminal is synchronized with the inverted output of the fourth flip-flop FF4. A fifth flip-flop FF5 for outputting the background color conversion signal DCLRB maintained as it is, the inverted output of the fifth flip-flop FF5 and the reset signal RESET are ANDed to output a data clear signal DCLR. A control signal generator 24 formed of an AND gate G6 and a first-third flip-flop FF1-FF3 for toggle operation.

Is connected to receive a clock in series, the counting unit 21 up-counts the vertical synchronization signal DVSB, and the ratio of the non-inverting output Q1 of the first flip-flop FF1 to the second flip-flop FF2. An AND gate G5 for outputting a nine-screen generation signal 9P by performing an AND operation on the inversion output Q2 and the data clear signal DCLR, the inversion output of the first flip-flop FF1 and the second flip-flop ( AND gate G3 for outputting the four-screen generation signal 4P by ANDing the inverted output of FF2 and the data clear signal DCLR, the non-inverted output Q1 of the first flip-flop FF1 and the first An AND gate G5 for outputting a 13-screen generation signal 13P by ANDing the non-inverting output Q1 of the second flip-flop FF2 and the data clear signal DCLR, and the third flip-flop FF3 The AND gate 67 outputs a 16-screen generation signal 16P by ANDing the inversion output Q3 and the data clear signal DCLR. A NAND gate G2 and a NAND gate that logically combine the decoding unit 22, the inverted output of the first flip-flop FF1, and the non-inverted output Q3 of the third flip-flop FF3. G2) a counter controller comprising an AND gate G7 for initializing the first to third flip-flops FF1 to FF3 by ANDing the output signal and the reset signal RESET generated from the microcomputer 10 during initial power supply. 23. A background screen processing apparatus for a multi-screen display, characterized by consisting of 23. The first and second luminance latch signals YALCH, color latch signals CLCH, and second luminance latches of the data latch unit 30 are initialized by the data clear signal DCLR and sequentially generated. Latch means 31 for latching the first luminance signal YAD, the color signal CD, and the second luminance signal YBD in digital form in synchronization with the signal YBLCH, respectively, and the first and second luminances; The background color selection means 32 selects one bit from the signals YAD and YBD and the color signal CD, respectively, and logically combines with the background color conversion signal DCLRB to adjust color and contrast of the background. Desktop processing apparatus of the multi-screen display, characterized in that configured.

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