JPH0279088A - Display memory access method - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of a system by inserting a drawing cycle immediately after the end of a display cycle being processed at a request for drawing access and dividing the subsequent display cycle into minimum access cycles of a display memory on a time-division basis. CONSTITUTION:Display memory access is performed normally in only a display cycle synchronized with a character clock 17 and when a display memory access request signal 4 is signified, the drawing cycle is inserted immediately after the end of the display cycle being processed to perform a drawing process. In the subsequent display access, a fast display cycle which is carried out at the minimum access time of the display memory 10 is performed several times so as to obtain the same timing with the display cycle synchronized with the character clock 17 and then the control returns to the display cycle to repeat the processing, thereby recovering the delay due to the insertion of the drawing cycle. Consequently, the wait time of a microprocessor is shortened and the processing performance of the system is improved.

Description

[Detailed Description of the Invention] [Field of Medical Application] The present invention relates to a display control system, and specifically improves the data in the display memory by speeding up the drawing process from the microprocessor to the display memory. This invention relates to a display memory access method f:lc that allows high-speed rewriting.

[Conventional technology]

Conventionally, regarding the display memory access method, chips
and Technology, 82C455 Data Sheet, Pages 19-25 ((:hips and Tg
c-hnology, P82C455DATASHE
ET PAGE 19-PAGE 25), and in this case, four character transfers are time-divided into four display cycles and one drawing cycle, and the operation of reading data from the image memory for display, and Data reordering operations in memory were processed in pre-assigned cycles.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, the display memory is accessed by dividing the display period into the display cycle and the drawing cycle, so that the microprocessor generates the drawing access memory and then The system is in a waiting state until the drawing cycle is completed.For this reason, the data stored in the display memory cannot be processed at high speed, and since the microprocessor cannot perform other processing during this time, the entire system is There was a problem that no consideration was given to improving the processing performance of the system, which would hinder the continued integration of the current system.

An object of the present invention is to avoid placing a load on the microprocessor for drawing access and to improve the processing efficiency of the system.

[Means to solve the problem]

In order to achieve the above object, in an arbitration control circuit that arbitrates between a display cycle and a drawing cycle, access cycles to the display memory are not controlled in advance in a time-sharing manner, but usually only the display cycle is controlled. When a drawing access request is received from the microphone o7'o processor, a drawing cycle is inserted immediately after the display cycle being processed ends, and the subsequent display cycles are time-divided into the minimum access cycles of the display memory, and the original display is restored. By performing a normal display cycle upon returning to the cycle, drawing access requests from the microprocessor are always accepted.

[Effect]

When there is a display memory access request, the arbitration control circuit of the technical means stops the activation of the display cycle after the display access in progress is completed. It then operates to start a drawing cycle.

As a result, the display memory access element is immediately accepted and drawing access can be executed, which improves the microprocessor's waiting time (reducing labor costs) and improving the processing performance of the system. Since the display data can be read immediately, the cycle can be controlled without overflowing the screen because the display timing of the CRT display is checked at the same time.

[Ability t1 Shiori] Hereinafter, it will be explained with reference to FIG. 1, which is an example of the book @ Ming. 1st
The figure shows a display control system, where 1 is a system bus and serves as an interface with a microprocessor (not shown), 2 is a system address bus for drawing,
5 is a data bus, and 4 is a display memory access code. 5 is a CRT controller which generates a display address 6 which is a d-address for display; the display address is latched by an address latch circuit 7, multiplexed by a system address 2 and a multiplex circuit 8, and a memory address 9 is generated. and is output to the display memory 10. The sequencer 11 that receives the display memory access cost An address latch signal 14, a data latch signal 16 for a data latch circuit 15 that latches read data for display, and a character clock 17 that serves as an operating clock for the CRT controller 5 are generated. Note that the sequencer 11 generates various signals by inputting the master signal 19 from the oscillator 1. The read data 3 latched by the data latch circuit 15 is converted into display data 21 by a data configuration conversion circuit 20 and displayed on the CRT display 2.
2.

Figure 2 shows the state transition of the display memory access method when the present invention is used. Normally, display memory access is performed only during the display cycle 23 synchronized with the character clock 17, and when the display memory access request signal 4 becomes valid, the drawing cycle 24 is inserted immediately after the display cycle 25 being processed ends. Performs drawing processing. I finished drawing,
In order to recover from the delay caused by drawing cycle 24, subsequent display accesses are performed using high-speed display cycle 25, which is executed in the minimum access time of the display memory. High-speed display cycle 25 starts again with character clock 17 K ti
It will be at the same timing as display cycle 23, which took t period.5
After performing the fl cycle, return to the precious display cycle 26,
Repeat the process. In this display cycle 23, the display memory access request signal 4 is always accepted. The state transition diagram of FIG. 2 is shown in the timing chart of FIG. 5. Display 1, Display 6 at memory address 9,
The period in which the address of display 7 is output is the display cycle 23, and the period in which the address of drawing φ is output is the drawing cycle 24, in which the addresses of display 2, display 3, display 4, and display 5 are output. This period is the high-speed display cycle 25.

In order to realize the state transitions shown in FIG. 2 and the timing chart shown in FIG. 3, FIG. 4 shows an arbitration control circuit which is a control section that arbitrates between display access and drawing access within the sequencer 11.

The arbitration circuit 26 inputs the display memory access signal 4 and the drawing permission signal 60 generated from the outputs of the master clocks 19, 27, 28, and 29, and generates the drawing execution signal 31. The drawing execution signal 51 is input to 27 state circuits. The shift register 32 to which the master clock 19 is input is converted to a source by a 560EOR circuit 54α, 54b, 64C+54cL,
54ε is generated. The source clock of 54CL is 2
7.28.29 state circuit clock, nI
State circuit 2 to which drawing execution signal 31 is input, stores the drawing state, and trains 1 and 5.
The lease clock 54d is enabled at 5α.

The arbitration block of 35α is the same as the memory control code 110 for drawing access.
It serves as a clock for the 57RAS generation circuit for generating the SCC2 (outress strop) 56.

Again, the data stored in 27 state circuits is 28
to the state circuit, memorize the high-speed display state,
Arbitration clock 55b Niriichi clock 6
4- is valid. Arbitration link 556
is the clock that generates the RAS 56 for display access, similar to the arbitration link 7a in 55α. The display state is memorized and the lease clock 54C is enabled for the arbitration link 35I6.After the immediate display state stored in the state circuit 29 is completed, the display states 27, 28, .
Since no data is stored in any of the state circuits 29, the normal display cycle is resumed, the lease clock 54b is made valid for the arbitrage train 1 link clock of 55b, the drawing permission signal 60 is also made valid, and the display of writing 4 is performed. The memory access requirement number 4 is set to the state of reception and reception. In this way, the cycle speed of the source clock of the train 1 link a and the link 55b is increased by the storage state of the state circuit.

Next, the timing of the arbitration clock 65b in the normal display cycle and the arbitration clocks 35α and 35b due to the insertion of the drawing cycle are shown in a time chart in FIG. In the normal cycle (1), the source clock 54b is connected to the arbitration train 1 link clock 55b.
Next, it is input to the RAS generation circuit 57 and delayed by the shift register 38, and with the 7 lip blocks 59cL and 59b enabled, the flip 7a block 69α, 39
The output of b is decoded and becomes 36 RAS. Again (21
In the case of a drawing cycle of push-in display cycle, the arbitrage sink 55a becomes effective, and 40a,
The output decoding result of flip-flop 40b is for the drawing cycle.

Then, the air and train running clock 35b becomes valid, and the output decoding result of the flip 7a knob of 39α and 59b becomes the valid signal for the display cycle and becomes the RAS of 56.
generate. Here, the quick display cycle is the lease clock 5 for generating the arbitration clock 55b.
By making 4g and 54C' effective, it is possible to shorten the cycle and realize high-speed display access. In this embodiment, 37 RASs are generated and precharged for each memory access. Although a circuit example for random read/write access has been shown, the same can be said for other display memory control modes.

〔Effect of the invention〕

According to the present invention, since it is only necessary to provide a circuit for storing the state of the display memory access cycle, the control circuit can be simplified. Further, since the time required for processing display data by the CPU can be shortened, when the present invention is configured as a part of a system, it has the effect of making it possible to improve the efficiency of the entire system.

[Brief explanation of the drawing]

FIG. 1 shows the block factors of an embodiment of the present invention, and FIG. 2 shows the block factors of an embodiment of the present invention.
FIG. 3 is a state transition diagram of the display memory access method of the present invention, FIG. 3 is a timing chart of the display memory access method of the present invention, and FIG. 4 is an adjustment clock timing chart of the present invention. 2...System address 6...Display address 4.
... CRT controller 6 ... Address multiplexer 7 ... Image memory 10 ... Arbitration control circuit, /-"T
fart

Claims (1)

[Claims] 1. In the arbitration control circuit that arbitrates between the display cycle and the drawing cycle, in normal mode, the access cycle to the display memory is limited to the display cycle only, and when a drawing access request is received from the microprocessor, the display cycle being processed is Insert a drawing cycle immediately after finishing,
A display memory access method characterized in that subsequent display cycles are time-divided into display memory minimum access cycles, and when the original display cycle returns, a normal mode display cycle is performed again.