JP2000181783A - Mediation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of access times to an arbitration circuit for preventing access contention in access to one memory that two processors share and to shorten time until the execution of memory access. SOLUTION: A D flip flop 1 outputting '1' when first and second processors do not access a memory and outputting '0' when the first and second processors access the memory and a combination circuit 100 generating the input of the D flip flop 1 so that the contention in access by an arbitration circuit for obtaining access right by the first and second processors and memory access with access for two times by the reading and the writing of the arbitration circuit are installed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an arbitration circuit for preventing contention of memory access for one memory shared by two processors.

[0002]

2. Description of the Related Art FIG. 6 shows an arbitration circuit 72 provided in an environment where one memory 74 is shared by two processors 70 and 71 so that the two processors 70 and 71 do not access the shared memory 74 at the same time. FIG. 2 is a block diagram illustrating a processor system. In the figure, two processors 70, 71 and a shared memory 74 are connected by a data bus 73.

FIG. 7 is a flowchart showing a conventional operation of the arbitration circuit 72 shown in FIG. In FIG. 7, when the processor 70 first tries to execute a memory access,
In order to check whether the processor 71 is executing a memory access, the processor 70 writes a value “1” to the arbitration circuit 72 (state T1 in FIG. 7). Next, the processor 70 reads the value stored in the arbitration circuit 72 (state T2 in FIG. 7). Then, the processor 70 determines the read value (state T3 in FIG. 7), and if the value is “1”, determines that the processor 71 is not executing the memory access and executes the memory access (FIG. 7). State T
4). Then, when the processor 70 ends the memory access, the processor 70 writes the value “0” into the arbitration circuit 72 to indicate that the access of the processor 70 is completed (state T5 in FIG. 7).

When the processor 71 also attempts to execute a memory access while the processor 70 is executing a memory access, the first operation of the processor 71 sets the arbitration circuit 72 to a value “1”. Write (state T1 in FIG. 7), read the value from the arbitration circuit 72 (state T1 in FIG. 7).
2), the operation of judging the value (state T3 in FIG. 7) is performed. From the second time, the operation is read from the arbitration circuit 72 (state T2 in FIG. 7) and the value is judged (state T in FIG. 7).
3), the operation is completed. A conventional arbitration circuit realizing this operation is disclosed in, for example,
There is a semaphore bit circuit disclosed in Japanese Patent No. 7974.
FIG. 8 shows the configuration, and FIG. 9 shows the operation timing.

In FIG. 8, reference numerals 49 and 57 denote data buses of the first and second processors 70 and 71, respectively.
58 is a write signal of each of the first and second processors 70 and 71, 51 and 59 are read signals of each of the first and second processors 70 and 71, and 42 is a second processor 7
1 write signal 58 is input non-inverted and output buffer 5
6 is an AND circuit that inverts the input of the output of the first processor 70, inputs the write signal 50 of the first processor 70 and the output of the output buffer 52 in a non-inverted manner, and an AND circuit 43 inverts and inputs the output of the latch 54. AND circuits 42, 4
An OR circuit 45 for inputting the output of the third processor 45 inputs the write signal 58 of the second processor 71 and the output of the output buffer 56 in a non-inverted manner, and inverts the output of the latch 48 for the input AN.
The D circuit 47 is a write signal 50 of the first processor 70.
, And an inverting input of the output of the output buffer 52. The AND circuit 46 includes these two AND circuits 45 and 4.
7 is an OR circuit for inputting the output of 7; 41 is OR circuits 43 and 4
RS latches for inputting the output of the first processor 70 to the S input and the R input, respectively. Reference numeral 48 designates a signal from the data bus 49 of the first processor 70 and a write signal 50 of the first processor 70 as a D input and a clock (CLK) input. , 54 is a data bus 5 of the second processor 71.
7 and the write signal 58 of the second processor 71 are respectively input to the D input and the CLK input, and 53 is an AND for inputting the Q outputs of the latches 48 and 41.
55, an AND circuit for non-inverting input of the Q output of the latch 54 and inverting input of the Q output of the latch 41; 52, 56 for outputting the read signals 51, 59 of the first and second processors 70, 71, respectively; This is an output buffer that permits the outputs of the AND circuits 53 and 55 in response.

Next, the operation will be described. 8 and 9, the data bus 49 of the processor 70 outputs the value "1" to the latch 48 when the processor 70 wants to access the shared memory 74, and then reads the value. It is determined whether the memory access can be executed or not. Latch 48
Is to temporarily hold the value of the data bus 49.

The write signal 50 is a signal for permitting writing to the latch 48. The read signal 51 is output from the AND circuit 5
3 and a signal for permitting reading of a signal indicating whether or not memory access can be performed on the data bus 49 via the output buffer 52. The data bus 57, the latch 54, the write signal 58, and the read signal 59 are also processed by the processor 7.
One memory access has a similar function. The RS latch 41 inputs the state of memory access of the two processors 70 and 71. When the value of the S input is "0" and the value of the R input is "0", the Q output holds the previous value, When the input value is “1” and the R input value is “0”, the Q output outputs a value “1”. When the S input is “0” and the R input is “1”, the Q output is Q.
The output controls the output values of the latches 48 and 54 by outputting a value "0".

[0008] As for the input to the RS latch 41, the signal to the R input is supplied to the AND circuits 45 and 47 and the OR circuit 4.
6, the value becomes "1" when the processor 70 finishes the memory access or when the processor 71 requests the memory access and the processor 70 is not executing the memory access. The signal to the S input is formed by the AND circuits 42 and 44 and the OR circuit 43. When the processor 71 completes the memory access, or when the processor 70 requests the memory access, the processor 71 executes the memory access. When not performed, the value is set to “1”. Otherwise, both values are "0".

In order for the processor 70 to execute memory access, first, a value "1" is output to the data bus 49,
The value of the write signal 50 is set to "1", and the value "1" is written to the latch 48 (state C1 in FIG. 9). At this time, since the processor 71 is not operating at all, the value of the data bus 57 of the processor 71 and the value of the output Q of the latch 54 are “0”, whereby the output of the AND circuit 44 and the OR
The output of the circuit 43 becomes "1".
Since the output Q of 8 is “0”, the output of the AND circuit 45 is “0”, and the output of the AND circuit 47 is “0”, so that the output of the OR circuit 46 is “0”. This allows
Since the value of the S input of the RS latch 41 becomes “1” and the value of the R input becomes “0”, the value of the Q output becomes “1”.

Next, the value written to the latch 48 is read to the data bus of the processor 70 via the AND circuit 53 by setting the value of the read signal 51 to "1" (FIG. 9).
In the state C2), a determination is made in the processor 70 thereafter. In this case, since the output value of the RS latch 41 is "1", the value of the latch 48 is not masked by the AND circuit 53, and the read value is the output value "1" of the latch 48 itself. Judge that access is possible.

At this time, when the processor 71 also attempts to execute memory access, first, a value "1" is written to the data bus 57, and the value of the write signal 58 is set to "1". Write is performed (state D1 in FIG. 9). At this time, the outputs of the AND circuits 42 and 44 both become "0", and the output of the OR circuit 41 becomes "0". Since the processor 70 is performing memory access, A
Since the output of the ND circuit 47 is "0" and the Q output of the latch 48 is "1", the output of the AND circuit 45 is "0".
And the output of the OR circuit 46 becomes "0". For this reason, the value of both the S input and the R input of the RS latch 41 is “0”.
, And the Q output holds the value “1” of the previous state. Subsequently, the value of the read signal 59 of the processor 71 is set to “1”, and the output of the latch 54 is output to the data bus 57 of the processor 71.
(State D2 in FIG. 9), and then the processor 71
Judge within.

In this case, since the output of the latch 54 is masked by the Q output of the RS latch 1 by the AND circuit 55,
The read value is “0”, which causes the processor 71 to determine that the memory access cannot be executed, and thus, to terminate the memory access of one processor.
Perform reading and judgment operations and wait.

This end determination operation is performed by the first latch 5
The value “1” of the write to “4” is held, and the value is set to “2”.
Since the control is performed by the output of the RS latch 41 for judging the operation state of the two processors, each write operation becomes unnecessary,
Only the operation of setting the value of the read signal 59 to “1”, reading the value, and making a determination in the processor 71 is sufficient.

On the other hand, when the processor 70 terminates the memory access, it outputs a value "0" to the data bus 49 and sets the value of the write signal 50 to "1", so that the memory access to this arbitration circuit is performed. Indicates termination. At this time, the output of the AND circuit 44 is “0”, the output of the data bus 57 of the processor 71 is “1”, and the output of the AND circuit 42 is “0”, so that the output of the OR circuit 43 is “0”. ". The output of the AND circuit 47 is "1".
Therefore, the output of the OR circuit 46 becomes “1” and RS
When the value of the S input becomes “0” and the value of the R input becomes “1”, the value of the Q output of the latch 41 becomes “0”.
Then, the output of the latch 48 is masked and the output of the latch 54 is read as it is, so that the memory access of the processor 71 can be executed. Then, the memory access is executed, and upon completion, the processor 71 outputs a value “0” to the data bus 57 and changes the value of the write signal 58 to “1” to indicate that the own memory access is completed.

[0015]

The conventional arbitration circuit is configured as described above, and when two processors share one memory, it is possible to prevent contention of the memory access. . However, in the arbitration circuit according to the conventional example, before the processor performs memory access, “writing to the arbitration circuit” and “reading out of the arbitration circuit” for acquiring the access right and “ It is necessary to access the arbitration circuit a total of three times, "writing to the arbitration circuit".

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems of the related art, and it is an object of the present invention to arbitrate the conflict between accesses to a memory shared by two processors at a higher speed. It is another object of the present invention to provide an arbitration circuit which can realize the above-mentioned operation with a smaller circuit configuration as compared with the conventional example.

[0017]

In order to solve this problem, an arbitration circuit according to a first aspect of the present invention provides a arbitration circuit for a memory shared by a first device and a second device.
An arbitration circuit for preventing contention of the memory from being accessed by the device, wherein the first and second devices are not accessing the memory and are enabled to access the memory; First,
Whether any one of the second devices is accessing the memory, and the device that is not accessing the memory is in a disabled state in which the memory cannot be accessed. A first storage circuit for storing the access right information shown, and after one of the first and second devices reads the information of the first storage circuit to acquire the access right to the memory The output of the first storage circuit becomes access right information indicating that the output is in a disabled state, and the first and second storage circuits are output.
Indicating that the output of the first storage circuit is enabled when any one of the devices writes access right information indicating that the device is enabled in the first storage circuit to relinquish the access right to the memory. And an access right information generating circuit for generating access right information to be written to the first storage circuit so that the access right information becomes the first access right information.

An arbitration circuit according to a second aspect of the present invention provides a arbitration circuit for a memory shared by a first device and a second device.
An arbitration circuit for preventing contention for access to the memory by the first and second devices, wherein the first and second devices do not access the memory and can access the memory. A certain enable state, and a disable state in which one of the first and second devices is accessing the memory, and a device that is not accessing the memory cannot access the memory. , A first storage circuit for storing access right information indicating which state is in the first state, and the first storage circuit for storing one of the first and second devices to obtain an access right to the memory. After reading the information of the storage circuit, the output of the first storage circuit becomes access right information indicating that the output is in the disabled state,
An output of the first storage circuit when the first or second device writes access right information indicating that the device is enabled in the first storage circuit to relinquish the access right to the memory; An access right information generating circuit for generating access right information to be written to the first storage circuit so that the access right information indicates that the device is in an enabled state; and the first and second devices for the memory. A second storage circuit for storing access execution information indicating which one is executing access, and an output of the second storage circuit as an input, and an access right to the memory among the first and second devices. Is written to the first storage circuit, indicating that only the person who has acquired the access right is in the enabled state to give up the access right to the memory. As it can be, but which is adapted and an input control circuit for controlling the input of the access right information generating circuit.

According to a third aspect of the present invention, in the arbitration circuit according to the first aspect, the first storage circuit comprises a first D flip-flop, and the access right information The generation circuit includes a first and a second read signal for instructing the first and second devices to read data from the first storage circuit and a first signal that receives an output signal of the D flip-flop as an input. An AND circuit, and the first device inverts and inputs a first write signal for instructing the first storage circuit to write data, and the first device writes to the first storage circuit A second AND circuit for non-inverting input of the first write data, and the second device inverting and inputting a second write signal for instructing the first storage circuit to write data to the first storage circuit; 2 device A third AND circuit for non-inverting input of second write data to be written into the first storage circuit by a source, a non-inverting input of an output signal of the first to third AND circuits, and a reset signal. And a first OR circuit for inverting the input and outputting the output signal to the D input of the first D flip-flop.

The arbitration circuit according to a fourth aspect of the present invention is the arbitration circuit according to the second aspect, wherein the first storage circuit comprises a first D flip-flop and the access right information The generation circuit includes a first and a second read signal for instructing the first and second devices to read data from the first storage circuit and a first signal that receives an output signal of the D flip-flop as an input. An AND circuit, and the first device inverts and inputs a first write signal for instructing the first storage circuit to write data, and the first device writes to the first storage circuit A second AND circuit for non-inverting input of the first write data, and the second device inverting and inputting a second write signal for instructing the first storage circuit to write data to the first storage circuit; 2 device A third AND circuit for non-inverting input of second write data to be written into the first storage circuit by a source, a non-inverting input of an output signal of the first to third AND circuits, and a reset signal. And a first OR circuit for inverting and inputting the output signal to the D input of the first D flip-flop, and wherein the second storage circuit comprises a second D flip-flop Wherein the input control circuit inverts the first read signal and non-inverts the output signal of the first D flip-flop, and outputs the first write signal and the first write signal. A fifth AND circuit for non-inverting the output signal of the second D flip-flop and inverting the output signal of the first D flip-flop; and outputting the output signals of the fourth and fifth AND circuits. 2nd to be input And the logical sum circuit,
A sixth AND circuit which receives the output signal of the second OR circuit and the reset signal as inputs, and outputs the output signal to the D input of the second D flip-flop, and the sixth AND circuit An output signal of the circuit is non-inverted to the second AND circuit and inverted to the third AND circuit.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. (Embodiment 1) In Embodiment 1, a memory access is performed by a total of two accesses, "reading of the arbitration circuit" for acquiring the access right and "writing of the arbitration circuit" for relinquishing the access right. The arbitration can be prevented with a smaller circuit configuration than that of the conventional example.

FIG. 1 is a flowchart showing the operation of the present invention relating to the arbitration circuit. In FIG. 1, first, a processor 70
When the user attempts to access the shared memory 74, the stored value is read out to the arbitration circuit 72 in order to check whether the processor 71 has executed the access to the shared memory 74 (FIG. 1). State T11). Then, the read value is determined (state T12a in FIG. 1), and if the value is "0", the processor 71
Access to the arbitration circuit 72
Is read out again (state T11 in FIG. 1). This operation is repeated until the value “1” is read, and if the value “1” is read, it is determined that the processor 71 is not accessing the shared memory 74. Also, after reading the value “1” from the arbitration circuit 72, the value of the arbitration circuit 72 automatically becomes “0” (state T12b in FIG. 1), and then accesses the shared memory 74 (FIG. 1). State T13). When the processing is completed, the value “1” is written to the arbitration circuit 72, indicating that the access of the processor 70 to the shared memory 74 has been completed (state T14 in FIG. 1).
When the processor 71 attempts to execute a memory access, it is the same as the case where the processor 70 performs a memory access, and a description thereof will be omitted.

FIG. 2 shows a circuit diagram of the arbitration circuit according to the first embodiment which realizes this operation, and FIG. 3 shows its timing. In FIG. 2, 1
Is a D-type flip-flop (hereinafter, referred to as DFF) that holds the value of the D input at the rising edge of the clock signal 8 and outputs it to the Q output. And an enabled state in which access to the shared memory is possible and one of the processors 70 and 71 is accessing the shared memory, and an access to the shared memory from a processor that is not accessing the shared memory is performed. Access right information indicating which state of the disabled state is possible is stored. 6 is an AND for outputting the output Q of DFF1 to the read data 16 of the processor 70 by setting the read signal 10 of the processor 70 to "0" when the processor 70 reads the value held by DFF1.
The circuit 7 sets the read signal 11 of the processor 71 to "0" when the processor 71 reads the value held in DFF1.
The read data 17 of the processor 71
An AND circuit for outputting the output Q of DFF1 to the AND circuit 3, an AND circuit for receiving the read signals 10, 11 of the processors 70 and 71 and the output Q of the DFF1 as inputs, An AND circuit for non-inverting the write data 13 of the processor 71
The AND circuit 2 inverts the write signal 14 of the processor 71 and non-inverts the write data 15 of the processor 71.
An OR circuit for non-inverting input of the outputs of the two AND circuits 3, 4, 5 and for inverting input of the reset signal 9, and 100 composed of these AND circuits 3, 4, 5 and OR circuit 2,
After one of the processors 70 and 71 reads the information of DFF1, the output of DFF1 becomes access right information indicating that the output is in the disabled state, and the information that one of the processors 70 and 71 is enabled by DFF1. When writing the access right information of DFF1, the DFF1 output becomes the access right information that the output of DFF1 is enabled.
Is a combinational circuit as an access right information generation circuit for generating access right information to be written into the CAM.

Reference numeral 12 denotes a negative polarity signal for the processor 70 to write to DFF1, that is, a write signal valid when it is "0", 13 denotes write data for the processor 70 to write to DFF1, and 14 denotes a write data for the processor 71. Negative write signal for writing to DFF1, 15 is the processor 71,
Write data 9 for writing to DFF1 is a reset signal for determining the initial state of DFF1 to "1".

Next, the operation will be described. First, when the reset signal 9 is set to "0" (state C1 in FIG. 3) to determine the initial state, the output of the OR circuit 2, that is, the input D of DFF1 becomes "1". The output Q changes from the undefined state to "1" (state C2 in FIG. 3). A case where the processor 70 accesses the shared memory 74 in a state where the output Q of DFF1 is set to “1” by the reset operation will be described.

When the processor 70 sets the read signal 10 to "0", the output Q of DFF1 is output to the read data 16 of the processor 70 through the AND circuit 6, and the processor 70 receives the access right information from the arbitration circuit 72 as the access right information. The processor 70 reads the value “1”, and the shared memory 74
Is recognized as having "access right" (state C in FIG. 3).
3), access to the shared memory 74 is started (the state after the state C4 in FIG. 3). That is, in the state C3 of FIG. 3, since the read signal 10 of the processor 70 is "0", the output of the AND circuit 3 is "0", and the write signal 12 of the processor 70 and the write signal 14 of the processor 71 are both "0". Since the output of the AND circuits 4 and 5 is "0" and the reset signal 9 is "1", the output of the OR circuit 2, that is, the input D of the DFF1 is "0" (FIG. 3).
State C3), the output of DFF1 changes from "1" to "0" (state C4 in FIG. 3). This means that the content of the arbitration circuit 72 is read, and if it is "1", the arbitration circuit 72 is automatically reset to "0".

Next, a case where the processor 71 attempts to access the shared memory 74 while the processor 70 is accessing the shared memory 74 will be described. Processor 7
0 is accessing the shared memory 74, that is,
When the output Q of DFF1 is “0”, the processor 71 accesses the shared memory 74, and when the processor 71 sets the read signal 11 to “0”, the output Q of DFF1 becomes AN
The data is output to the read data 17 of the processor 71 via the D circuit 7, the processor 71 reads "0", and the processor 71 recognizes that "there is no access right" to the shared memory 74 (the state C5 in FIG. 3). ), The access to the shared memory 74 is not performed.

When the access of the processor 70 to the shared memory 74 is completed, the processor 70
2 to "0" and its write data 13 to "1", the output of the AND circuit 4 becomes "1", so that the output of the OR circuit 2, that is, the input D of DFF1 becomes "1" ( FIG.
State C6), the output Q of DFF1 changes from "0" to "1" (state C7 in FIG. 3).

Similarly, the processor 71 stores the shared memory 74
The case of accessing will be described. Processor 71
When the read signal 11 is set to “0”, the output Q of DFF1 is output via the AND circuit 3 to the read data 1 of the processor 71.
7, the processor 71 reads the value “1” from the arbitration circuit 72 as access right information, and the processor 70 “has access right” to the shared memory 74.
(State C9 in FIG. 3), and access to the shared memory 74 is started (state after state C10 in FIG. 3). That is, in the state C9 of FIG. 3, since the read signal 11 of the processor 71 is "0", the output of the AND circuit 3 is "0", and the write signal 14 of the processor 71 and the write signal 12 of the processor 70 are both "0". 1 "
Since the outputs of the AND circuits 4 and 5 are "0" and the reset signal 9 is "1", the output of the OR circuit 2, that is, the input D of DFF1 becomes "0" (state C9 in FIG. 3) and the output of DFF1 Changes from "1" to "0" (state C10 in FIG. 3).

Next, a case where the processor 70 attempts to access the shared memory 74 while the processor 71 is accessing the shared memory 74 will be described.

When the processor 71 is accessing the shared memory 74, that is, when the output Q of DFF1 is "0", the processor 70 accesses the shared memory 74 so that the read signal 10 When it is set to "0", the output Q of DFF1 is output to the read data 16 of the processor 70 via the AND circuit 6, and the processor 70 reads "0".
Is recognized as "no access right" (state C in FIG. 3).
11), access to the shared memory 74 is not performed.

When the access of the processor 71 to the shared memory 74 is completed, the processor 71
4 is set to "0" and its write data 15 is set to "1", the output of the AND circuit 5 becomes "1", whereby the output of the OR circuit 2, that is, the input D of DFF1 becomes "1". 3
State C12), the output Q of DFF1 changes from "0" to "1" (state C13 in FIG. 3).

In the states C4 to C5 of FIG. 3, the output Q of DFF1 is "0", whereby the output of the AND circuit 3 becomes "0".
If the write signal 12 of the processor 71 and the write signal 14 of the processor 71 are "1", that is, if there is no writing to the DFF1 from the processors 70 and 71, the outputs of the AND circuits 4 and 5 both become "0". The input D becomes "0" and DFF1
Becomes "0" (states C4 to C6 in FIG. 3).
.

That is, in order to access the shared memory 74, one of the processors 70 and 71 reads DFF1, and after the output of DFF1 becomes "0", the processor 7
Until either 0 or 71 writes “1” to DFF1,
The output Q of DFF1 holds "0" which is a disabled state.

The output Q of DFF1 is "1", and the read signal 10 of the processor 70 and the read signal 11 of the processor 71 are both "1".
If DFF1 is not read from 1, the output of the AND circuit 3 becomes "1", so that the input D of DFF1 becomes "1" (states C3 to C5 in FIG. 3), and the output Q of DFF1 becomes "1". (States C4 to C6 in FIG. 3).

That is, after the access to the shared memory 74 is completed and one of the processors 70 and 71 writes to DFF1 and the output of DFF1 becomes "1",
Until the processors 70 and 71 read DFF1 to access, the output Q of DFF1 holds "1" which is an enabled state.

Lastly, a case where the processors 70 and 71 simultaneously read DFF1 to access the shared memory will be described. Processors 70 and 71 are simultaneously DF
When the output Q of F1 is read, the processor 70 reads "1" via the AND circuit 6, and the processor 71 reads "0" via the AND circuit 7 (state C14 in FIG. 3). For this reason, the processor 70 recognizes that “there is an access right” to the shared memory 74, and the processor 71 recognizes that the “there is no access right” to the shared memory 74, and an access request occurs at the same time. In this case, access conflict can be prevented.

As described above, according to the first embodiment, AN
A combination circuit 100 is constituted by the D circuits 3, 4, 5 and the OR circuit 2, and the combination circuit 100 converts an input signal of the D flip-flop 1 storing information indicating whether or not the processor 70, 71 has an access right. Generate
In addition, since the output signal of the D flip-flop 1 is configured to be fed back to the input of the combinational circuit 100, the read of the arbitration circuit for acquiring the access right can be performed.
A total of 2 writes to the arbitration circuit to relinquish access rights
The contention of memory access can be prevented by a single access, and this arbitration can be performed with a smaller circuit scale as compared with the conventional example.

(Embodiment 2) In Embodiment 2, while one processor is accessing the shared memory, the other processor cannot write "access right" to the arbitration circuit. As described above, the first embodiment is improved. FIG. 4 is a circuit diagram for realizing the arbitration circuit according to the second embodiment of the present invention, and FIG. 5 is a timing chart thereof. In FIG. 4, 1 to 17 have the same configuration as the circuit of FIG. 2
0 inverts the read signal 10 of the processor 70 and outputs DF
An AND circuit 22 for non-inverting input of the output Q of F1; an AND circuit 22 for non-inverting input of the write signal 12 of the processor 70 and the output of the OR circuit 21 and inverting input of the output Q of DFF1;
An OR 21 receives the outputs of these AND circuits 20 and 22 as inputs.
A circuit 19 is an AND circuit to which the output of the OR circuit 21 and the reset signal 9 are non-inverted and input, and 18 is an AND circuit 1
9 is a D-type flip-flop (hereinafter, referred to as DFF) which receives the output of D at the D input, holds the value of the input D at the rising edge of the clock signal 8 and outputs it to the output Q. The access execution information indicating which of the processors 70 and 71 is executing the access is stored. 200 is the DFF 18, AND circuit 2
0, an AND circuit 22, an OR circuit 21, and an AND circuit 19. The outputs of the DFF 18 are input to the processors 70 and 71.
Out of the access right information that only the person who has acquired the access right to the shared memory 74 is in the enabled state.
This is a combination circuit as an input control circuit that controls the input of the combination circuit 100 so that it can be written into DFF1.

With this configuration, the arbitration circuit of the second embodiment has a feature in performing writing to DFF1 as compared with the first embodiment. That is, in the arbitration circuit of the second embodiment, the processor 70
While the processor 71 is accessing
Since "1" cannot be written to DFF1, the processor 70
Only "1" can be written to DFF1. Similarly, while the processor 71 is accessing the shared memory 74, the processor 70 cannot write "1" to DFF1 and the processor 71 can only write "1" to DFF1.

Next, the operation will be described. First, in order to determine the initial state, the reset signal is set to "0" (state C1 in FIG. 5) and the output of the AND circuit 19, that is, the input D of the DFF1 is inputted.
Becomes “0” and DFF18 at the rising edge of the clock signal 8.
Output from the undefined state to "0" (state C in FIG. 5).
2).

Next, as described above, the output Q of DFF18 is "0".
When the processor 70 accesses the shared memory in the state set as “1”, the processor 70 reads the output “1” of DFF1, so that the read signal 10
Is "0" and the output Q of DFF1 is "1", so that AN
The output of the D circuit 20 is "1" and the output of the OR circuit 21 is "1".
At this time, since the reset signal 9 is "1",
The output of the AND circuit 19 is "1", that is, the input D of the DFF18.
Becomes "1" (state C3 in FIG. 5), and the output Q of DFF18 changes from "0" to "1" (state C4 in FIG. 5). Further, the processor 70 reads the value “1” of the output Q of DFF1, and
The processor 70 recognizes that the shared memory 74 has “access right” (state C3 in FIG. 5), and
4 is accessed (from state C4 in FIG. 5). While the processor 70 is accessing the shared memory 74, the processor 7
When 1 sets DFF1 to "1", the write signal 14 of the processor 71 becomes "0" and the write data 15 of the processor 71 becomes "1". At this time, the output of the AND circuit 19 is "1". Therefore, the output of the AND circuit 5 is "0", and the read signal 10 and the write signal 12 of the processor 70 are "0" and "1". Therefore, the outputs of the AND circuits 3 and 4 are also "0", and the OR The output of the circuit 2, that is, the input D of DFF1 becomes "0", the writing from the processor 71 to DFF1 is masked, and "1" cannot be written to DFF1 (state C6 in FIG. 5).

After the processor 70 completes the access to the shared memory 74, the processor 70 writes "1" to DFF1.
2 is "0", and the output Q of DFF1 is "0" at this time.
Since the read signal 10 of the processor 70 is “1” and the write signal thereof is “0”, the outputs of the AND circuits 20 and 22 become “0”, whereby the outputs of the OR circuit 21 and the AND circuit 19 become "0", that is, the input D of DFF18 is "0"
(State C6 in FIG. 5), and the output Q of DFF18 becomes "1".
To "0" (state C7 in FIG. 5).

When the processor 71 accesses the shared memory, the processor 71 reads DFF1, but the output D of DFF18 remains "0" because the input D of DFF18 does not change. The processor 71 reads “1” from DFF1, and recognizes that the shared memory 74 has “access right” (state C9 in FIG. 5), and accesses the shared memory 74 (state C in FIG. 5). State after C10).

If the processor 70 attempts to set DFF1 to "1" while the processor 71 is accessing the shared memory 74, the write signal 12 of the processor 70 becomes "0" and the write data 13 of the processor 70 becomes "1". However, since the output of the AND circuit 19 is "0", the output of the AND circuit 4 is "0", and at this time, the write signal 14 of the processor 71 is "1" and the write data 15 is "0". Therefore, the output of the AND circuit 5 is “0” and the output Q of DFF1 is “0”.
Therefore, the output of the AND circuit 3 is "0", the output of the OR circuit 2, that is, the input D of DFF1 is "0", the writing from the processor 70 to DFF1 is masked, and DFF1 is set to "1". Cannot be written (state C11 in FIG. 5).

After the processor 71 completes the access to the shared memory 74, the processor 70 sets "1" to DFF1.
Is written, the write signal 12 of the processor 70 becomes "0". At this time, the output Q of DFF1 is "0", whereby the outputs of the AND circuits 20 and 22 are both "0" and the OR circuit 21 , And the output of the AND circuit 19 becomes "0", so that the input D of DFF18 becomes "0" (state C in FIG. 5).
6), the output Q of DFF18 changes from "1" to "0" (FIG. 5)
State C7). That is, the output Q of DFF18 automatically becomes "1" when the processor 70 is accessing the shared memory 74, and automatically becomes "0" when the access is completed.

If one of the processors is accessing the shared memory 74 and the other processor is not accessing the shared memory 74, it writes DFF1 which is originally "0" to "1", and the other processor is not accessing the shared memory 74. Processor is DFF1
And recognizes that "there is an access right", a problem occurs that two processors can simultaneously access the shared memory 74. On the other hand, in the second embodiment, the output Q of DFF18 can be used so that only the accessing processor can write to DFF1.

As described above, according to the second embodiment, AN
A combination circuit 200 is composed of the D circuits 20, 22, 19 and the OR circuit 21. The state of the output signal of the combination circuit 200 is stored by the D flip-flop 18 and is fed back to the input of the AND circuit 22. Since the output signal of the arbitration circuit 200 is also input to the AND circuits 4 and 5, the arbitration circuit for acquiring the access right and the arbitration circuit for relinquishing the access right are written twice. Not only can prevent memory access conflicts, but also allow only the accessing processor to write to the D flip-flop 1, and perform this arbitration with a circuit size substantially equal to that of the conventional example. It becomes possible.

In the first and second embodiments, the enable state is "1", the disable state is "0", and the read and write signals of the processors 70 and 71 are negative. Are inverted by inverting the logic constituting the circuit, that is, the enable state is "0", the disable state is "1", and the read and write signals of the processors 70 and 71 have positive polarity. It may be.

Further, in the first and second embodiments, a case has been described as an example in which contention for memory access to one memory shared by two processors is prevented. However, this is not limited to the processor. At least one of those sharing the memory may be a programmable device.

[0051]

As described above, according to the arbitration circuit according to the first aspect of the present invention, the memory shared by the first and second devices is replaced by the memory by the first and second devices. An arbitration circuit for preventing access conflicts between the first and second devices, wherein none of the first and second devices has access to the memory, and the first and second devices can access the memory; Access indicating that one of the devices is accessing the memory, and that the device that is not accessing the memory is in a disabled state in which the memory cannot be accessed. A first storage circuit for storing the right information, and a first storage circuit for storing one of the first and second devices so as to obtain the access right to the memory. After reading out the information, the output of the first storage circuit becomes access right information indicating that it is in a disabled state, and the first or second device rejects the access right to the memory. When writing the access right information indicating the enabled state to the first storage circuit, the first storage circuit writes the access right information so that the output of the first storage circuit becomes the access right information indicating the enabled state. The access right information generation circuit for generating the access right information to be provided can reduce the number of accesses to the arbitration circuit for preventing contention for access to one memory shared by the two devices Therefore, there is an effect that the time until the execution of the memory access can be shortened.

According to the arbitration circuit of the second aspect of the present invention, contention for access to the memory shared by the first and second devices by the first and second devices is prevented. And an arbitration circuit for enabling the first and second devices to access the memory and not to access the memory; One of them is accessing the memory, and the access right information indicating which state is in a disabled state in which the device that is not accessing the memory cannot access the memory is stored. A first storage circuit and one of the first and second devices read information in the first storage circuit to acquire an access right to the memory. After that, the output of the first storage circuit becomes access right information indicating that the output is in the disabled state, and the first or second device relinquishes the access right to the memory so that the first memory device relinquishes the access right. The access right to be written to the first storage circuit so that the output of the first storage circuit becomes the access right information to the effect that the output is enabled when the access right information indicating the enabled state is written to the storage circuit. An access right information generating circuit for generating information;
A second storage circuit for storing access execution information indicating which one of the second devices is executing access, and an output of the second storage circuit as an input, the second storage circuit being one of the first and second devices; The access right information so that only the person who has acquired the access right to the memory can write the access right information to the effect that the access right to the memory is enabled to abandon the access right to the memory into the first storage circuit. Since an input control circuit for controlling the input of the generation circuit is provided, the number of accesses to the arbitration circuit for preventing contention for access to one memory shared by the two devices can be reduced. Therefore, it is possible to shorten the time until execution of memory access, and when one device accesses the shared memory, the other device Al is effective in making it possible to make it impossible to write that there is access to the arbitration circuit.

According to the arbitration circuit according to the third aspect of the present invention, in the arbitration circuit according to the first aspect, the first storage circuit comprises a first D flip-flop, and The right information generation circuit receives the first and second read signals for instructing the first storage circuit to read data from the first and second devices and the output signal of the D flip-flop. 1 logical product circuit, and the first device inverts and inputs a first write signal for instructing the first memory circuit to write data, and the first device inputs the first memory signal to the first memory circuit. A second AND circuit for non-inverting input of first write data to be written, and the second device inverting and inputting a second write signal for instructing the first memory circuit to write data; The second Third the device to the non-inverting input of the second write data to be written to said first memory circuit
And a non-inverted input of an output signal of the first to third AND circuits, and an inverted input of a reset signal.
Since the first OR circuit outputs the input, the number of accesses to the arbitration circuit for preventing contention for access to one memory shared by the two devices can be reduced. Therefore, there is an effect that the time until the memory access is executed can be shortened, and this can be realized with a smaller circuit scale than before.

According to the arbitration circuit of the invention of claim 4 of the present application, in the arbitration circuit of claim 2, the first storage circuit comprises a first D flip-flop, and The right information generation circuit receives the first and second read signals for instructing the first storage circuit to read data from the first and second devices and the output signal of the D flip-flop. 1 logical product circuit, and the first device inverts and inputs a first write signal for instructing the first memory circuit to write data, and the first device inputs the first memory signal to the first memory circuit. A second AND circuit for non-inverting input of first write data to be written, and the second device inverting and inputting a second write signal for instructing the first memory circuit to write data; The second Third the device to the non-inverting input of the second write data to be written to said first memory circuit
And a non-inverted input of an output signal of the first to third AND circuits, and an inverted input of a reset signal.
A first OR circuit for outputting to the input, the second storage circuit includes a second D flip-flop, and the input control circuit inverts the first read signal. A fourth AND circuit which inputs the output signal of the first D flip-flop and inputs the output signal of the first D flip-flop in a non-inverted manner; A fifth AND circuit for inverting and inputting the output signal of the D flip-flop of
A second OR circuit that receives an output signal of the fifth AND circuit, an input signal that receives the output signal of the second OR circuit and the reset signal, and outputs the output signal of the second D flip-flop. And a sixth AND circuit for outputting to the D input. An output signal of the sixth AND circuit is non-inverted input to the second AND circuit and inverted to the third AND circuit. Since the input is made, it is possible to reduce the number of accesses to the arbitration circuit for preventing access conflicts to one memory shared by the two devices, so that the time until memory access is executed is reduced. When one device accesses the shared memory, it is possible to prevent the other device from writing that the arbitration circuit has the access right, and the same as before. There is an effect that it is possible to achieve this on a scale of circuit scale.

[Brief description of the drawings]

FIG. 1 is a flowchart of an operation of an arbitration circuit according to Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram that realizes an arbitration circuit according to the first embodiment of the present invention.

FIG. 3 is a timing diagram of the circuit of FIG. 2;

FIG. 4 is a circuit diagram that realizes an arbitration circuit according to a second embodiment of the present invention.

FIG. 5 is a timing diagram of the circuit of FIG. 4;

FIG. 6 is a block diagram showing a system including two processors sharing a memory;

FIG. 7 is a flowchart showing the operation of a conventional arbitration circuit.

FIG. 8 is a circuit diagram of the arbitration circuit of FIG. 7;

FIG. 9 is a timing diagram of the circuit of FIG. 8;

[Explanation of symbols]

1, 18 D flip-flop 41 RS latch 3, 4, 5, 6, 7, 19, 20, 22, 42, 44,
45, 47, 53, 55 AND circuit 2, 21, 43, 46 OR circuit 48, 14, 27, 34, 41, 47 Latch 49, 57 Data bus 40, 58 Write signal 41, 59 Read signal 42, 66 Output buffer 70, 71 Microprocessor 72 Arbitration circuit 73 Data bus 74 Shared memory 10 Processor 70 read signal 11 Processor 71 read signal 12 Processor 70 write signal 13 Processor 70 write data 14 Processor 71 write signal 15 Processor 71 write data 16 Read Data of Processor 70 17 Read Data of Processor 71 100, 200 Combination Circuit

Claims (4)

[Claims] An arbitration circuit for preventing contention of access to the memory by the first and second devices with respect to a memory shared by the first and second devices, wherein the first and second devices are provided. Are not accessing the memory and are able to access the memory, and one of the first and second devices is accessing the memory and accessing the memory. A first storage circuit for storing access right information indicating which state is a disabled state in which access to the memory from a device that is not available is not possible; and the first and second devices Read out the information of the first storage circuit in order to obtain the access right to the memory, and then output the first storage circuit Access right information indicating that the first storage circuit is in an enabled state in order to relinquish the access right to the memory by the first or second device. An access right information generation circuit for generating access right information to be written to the first storage circuit so that the output of the first storage circuit becomes access right information indicating that the output is in an enabled state at the time of writing. An arbitration circuit characterized in that: 2. An arbitration circuit for preventing contention of access of the memory by the first and second devices to a memory shared by the first and second devices, wherein the first and second devices are provided. Are not accessing the memory and are able to access the memory, and one of the first and second devices is accessing the memory and accessing the memory. A first storage circuit for storing access right information indicating which state is a disabled state in which access to the memory from a device that is not available is not possible; and the first and second devices Read out the information of the first storage circuit in order to obtain the access right to the memory, and then output the first storage circuit Access right information indicating that the first storage circuit is in an enabled state in order to relinquish the access right to the memory by the first or second device. An access right information generating circuit for generating access right information to be written to the first storage circuit so that the output of the first storage circuit becomes access right information indicating that the output of the first storage circuit is enabled when writing; A second storage circuit that stores access execution information indicating which of the first and second devices is executing access to the first and second devices, and an output of the second storage circuit as an input, Second
Only the device that has acquired the access right to the memory among the devices can write the access right information indicating that the device is in the enabled state to abandon the access right to the memory to the first storage circuit. And an input control circuit for controlling an input of the access right information generation circuit. 3. The arbitration circuit according to claim 1, wherein said first storage circuit comprises a first D flip-flop, and said access right information generation circuit comprises: said first and second devices. A first AND circuit that inputs first and second read signals for instructing the first storage circuit to read data and an output signal of the D flip-flop; and A first write signal for instructing data writing to one storage circuit is inverted and input,
A second AND circuit for non-inverting input of first write data written by the first device to the first storage circuit; and writing of data to the first storage circuit by the second device. Inverts a second write signal indicating
A third AND circuit for non-inverting input of second write data written by the second device to the first storage circuit; and a non-inverting input of an output signal of the first to third AND circuits. And a first OR circuit for inverting the reset signal and outputting the output signal to the D input of the first D flip-flop. 4. The arbitration circuit according to claim 2, wherein said first storage circuit comprises a first D flip-flop, and said access right information generation circuit comprises: said first and second devices. A first AND circuit that inputs first and second read signals for instructing the first storage circuit to read data and an output signal of the D flip-flop; and A first write signal for instructing data writing to one storage circuit is inverted and input,
A second AND circuit for non-inverting input of first write data written by the first device to the first storage circuit; and writing of data to the first storage circuit by the second device. Inverts a second write signal indicating
A third AND circuit for non-inverting input of second write data written by the second device to the first storage circuit; and a non-inverting input of an output signal of the first to third AND circuits. And a first OR circuit for inverting the reset signal and outputting the output signal to the D input of the first D flip-flop, wherein the second storage circuit is a second D flip-flop. A fourth AND circuit which inverts the first read signal and non-inverts the output signal of the first D flip-flop; and A fifth AND circuit for non-inverting input of a write signal and an output signal of the second D flip-flop and inverting input of an output signal of the first D flip-flop; and the fourth and fifth AND circuits Output signal A second OR circuit which receives the output signal of the second OR circuit and the reset signal, and outputs the output signal to the D input of the second D flip-flop. Arbitration, wherein an output signal of the sixth AND circuit is non-inverted input to the second AND circuit and invertedly input to the third AND circuit. circuit.