JPH0277096A - Automatic rhythm playing device - Google Patents

Abstract

PURPOSE:To enable a player to set and play an optional rhythm pattern intentionally by writing and reading the rhythm pattern by using a writable storage means. CONSTITUTION:A random access memory 6 becomes readable when a logical value '0' is inputted to its write/read command terminal W/R, and is so constituted that (n) kinds of rhythm patterns stored therein are read out and outputted as rhythm pattern signals RP1 - RPn from readout output terminals B1 - Bn according to address signals ADi (i=1, 2...m) outputted by an address generator 4. A rhythm sound source circuit 12 has a function for outputting the (n) kinds of rhythm sound signals at the same time and, for example, when a rhythm pattern signal RP1 with a logical value '1' is inputted from the random access memory 6 to a 1st input terminal C1 in order, a rhythm sound signal of, for example, cymbals is generated according to the rhythm pattern signal RP1. Consequently, the rhythm pattern can be set optionally by the intention of the player.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an automatic rhythm playing device, and more specifically to an automatic rhythm system in which a performer can set a rhythm pattern by himself or herself by operating a keyboard or the like. The present invention relates to a musical performance device.

[Prior Art and Problems to be Solved by the Invention] In a conventional automatic rhythm performance device, a plurality of rhythm patterns (for example, waltz, tamp, etc.) are stored in a read-only memory (ROM) corresponding to each rhythm sound source. The player obtains a desired rhythm pattern by selecting one of the plurality of rhythm patterns using a rhythm selection switch. (For example, Special Publication Showa 5l-311i059
There is an invention disclosed in No. ) However, in this type of automatic rhythm performance device, the rhythm pattern is determined by the contents stored in the read-only memory, and once the rhythm pattern is determined, the performer cannot arbitrarily change the rhythm pattern. . Therefore, the types of rhythms that can be played are limited, making it impossible for players to play as they wish.

In contrast to the automatic rhythm performance apparatus described above, an automatic rhythm performance apparatus has been proposed in which a rhythm pattern can be arbitrarily set using a mechanical switch. In this system, the rhythm selection switch is composed of a matrix circuit into which bins can be inserted in multiple columns and rows, and a rhythm pattern is set by appropriately inserting multiple bins into this matrix circuit (for example, the rhythm pattern is set by inserting a plurality of bins into this matrix circuit). However, an automatic rhythm playing device using such a mechanical switch (as disclosed in Japanese Patent Application No. 525) has the disadvantage that the device inevitably becomes large due to its mechanism. Therefore, even though it is possible to arbitrarily set various rhythm patterns, it is impossible to increase the capacity in order to miniaturize the device, which naturally limits the range of rhythm settings.

The present invention was developed in view of the above-mentioned drawbacks of the conventional automatic rhythm performance device, and it is possible to arbitrarily set the rhythm pattern for each rhythm sound source according to the player's will, and furthermore, compared to the conventional automatic rhythm performance device, The purpose of the present invention is to provide a miniaturized automatic rhythm performance device.

[Means and effects for solving the problem] The automatic rhythm of the present invention (*The performance device includes a clock generating means that generates a frequency signal of a predetermined period; based on the output signal from the clock generating means, the automatic rhythm of the present invention A storage position signal generating means for generating a storage position signal regarding sound generation timing; a keyboard which also serves as all or a part of the keyboard of an electronic musical instrument, and which specifies storage positions regarding all U types of music by operating this 1! board; ; The storage position for writing and reading is specified by the storage position signal generated by the storage position signal generating means and the storage position specified by the keyboard, and the rhythm pattern corresponding to each rhythm sound source is created at the storage position by operating the keyboard. A storage means for writing; a rhythm tempo display means for displaying the rhythm tempo by the output signal from the clock generation means or the storage position signal generation means; and a rhythm tempo display means for displaying a plurality of rhythm pattern signals read from the storage means; A rhythm sound source circuit that outputs a signal is provided.

[Examples] The present invention will be described in more detail below with reference to examples shown in the accompanying drawings.

FIG. 1A shows a first embodiment of the invention,
An output terminal of a clock generator 1 having a variable resistor 3 is connected to an input terminal of an address generator 4 .

The movable contact of the start switch 2 is grounded, and the fixed contact is connected on one side to a constant voltage source +V via a resistor and on the other hand to the reset terminal R of the clock generator 1 and the reset terminal R of the address generator 4, respectively. The output side of the address generator 4 is connected on the one hand to an address input of a random access memory 6 and on the other hand to a read address input of a read only memory 7. Further, the write input terminal group A1 to An of the random access memory 6 is configured so that a logical value "1" is manually applied via the corresponding automatic return type switches S1 to Sn of the pattern forming switch unit 5, respectively. ing. The rhythm pattern forming switch section 5 is also used as all or part of the keyboard of an electronic musical instrument equipped with an automatic rhythm performance device according to the wooden embodiment. The output side of the read-only memory 7 is connected on one side to a first input terminal of an AND circuit 10, and on the other side is grounded via a resistor and a light emitting diode 9.

Further, the first output terminal B1 among the read output terminal groups B1 to Bn of the random access memory 6 is connected to the second input terminal of the OR circuit 11, and the other output terminal groups 82 to Bn
are directly connected to the input terminal group C2 to Cn of the rhythm sound source circuit 12. Furthermore, the write/read command terminal W/R of the random access memory 6 is connected to the movable contact of the write/read designation switch 8, and the logical value "l" is manually input to the fixed contact W of the write/read designation switch 8, which is the fixed contact. A logical value "0" is input to R. Further, the movable contact of the write/read designation switch 8 is connected to the second input terminal of the AND circuit 10.
The output side of 0 is connected to the first input terminal of the OR circuit 11. The output side of this OR circuit 11 is the rhythm sound source circuit 1
2, and is connected to the first input terminal C1 of 2.

The output side of the rhythm sound source circuit 12 is connected to a sound system 13 consisting of an amplifier, speakers, and the like.

Here, the clock generator 1 is configured such that the generation cycle of the generated clock pulse CP is adjusted by adjusting the variable resistor 3. Further, the address generator 4 is composed of a counting circuit consisting of a shift register, a counter, and a decoder, and counts the clock pulses CP generated by the clock generator 1, and corresponds to the output line according to the counted value. Address signal ADi (+=1.2...m) (logical value "1") is output to. A desired rhythm pattern is stored in advance in the read-only memory 7, and upon receiving the read address signal ADi outputted from the address generator 4, the stored rhythm pattern is converted into a rhythm pattern signal r.
It is configured to read out sequentially as P.

The random access memory 6 enters a writable state when a logical value "1" is input to its write/read command terminal W/R, and the switches 31 to Sn are connected to the write input terminals A1 to An of the random access memory 6, respectively.
The logic value "1" which is manually input as appropriate by opening and closing the gate is sequentially stored as a rhythm pattern at the address specified by the address generator 4. Here, the random access memory 6 has mxn addresses as shown in FIG. 1B, and each address has the coordinates (1%j)i=1.
2...m, j=1.2...n. Each of these addresses is an address signal ADi (i=1.2...
・It is specified by m) as follows. That is, n addresses (1,1) (1,2
)...(1, n) is specified, and generally the n addresses (i, j) in the first column are specified by the address signal ADi.
j=1.2...n is specified. Therefore, the signal group of logical value "1" which is sequentially input to the input terminal A1 of the random access memory 6 in synchronization with each address signal ADi is the m address (1, 1, 1) (2,1
)...(m, 1) is stored as one rhythm pattern. Generally, each address signal ADi, i=1.2
...The signal group of logical value ゛°1'' which is sequentially input to the input terminal Aj corresponding to m is the address of m in the third row (
i, j), i;1.2...m are stored as one rhythm pattern. That is, the illustrated random access memory 6 has the ability to store one rhythm pattern corresponding to each of the input terminals Ai, for a total of n types of rhythm patterns. In addition, the random access memory 6 has a logic value “0” at the write/read command terminal W/R.
is in a readable state when it is manually input, and the address signal ADi, which is output from the address generator 4,
n already stored according to i=1.2...m
It is configured such that different kinds of rhythm patterns are read out from the readout output terminals 81 to Bn as rhythm pattern signals RPI to RPn, respectively. The rhythm sound source circuit 12 has a function of simultaneously outputting n types of rhythm sound signals,
Each of the input terminals C1 to Cn is configured as an input terminal for rhythm pattern signals RP1 to RPn for one rhythm sound.

For example, each of the input terminals 01 to Cn corresponds to one rhythm sound, such as the first input terminal C1 to a cymbal and the second input terminal C2 to a bass drum. Therefore, for example, when a rhythm pattern signal RPI with a logical value of "1" is sequentially input from the random access memory 6 to the first input terminal C1, a cymbal rhythm sound signal is generated in accordance with the rhythm pattern signal RPI.

The effects of the first embodiment of the present invention having the above configuration will be described next.

When the start switch 2 is set to the "open" position, a positive voltage +V is applied to the clock generator 1 and the reset terminal R of the address generator 4.
Both clock generator 1 and address generator 4 are in a reset state. Therefore, the automatic rhythm playing device is in a stopped state.

In the following explanation, for convenience, the random access memory 6
A rhythm pattern writing operation for writing a rhythm pattern into a rhythm pattern and a rhythm pattern reading operation for reading it will be explained separately.

Rhythm pattern writing operation When a performer writes a rhythm pattern into the random access memory 6, he or she first sets the write/read designation switch 8 to the fixed contact W side. As a result, the logical value "1'° is input to the write/read command terminal W/R of the random access memory 6, so the random access memory 6 becomes in a writable state. Next, when the start switch 2 is depressed, the clock Since the reset terminal R of each of the generator 1 and the address generator 4 is grounded, the reset state of both the clock generator 1 and the address generator 4 is released.Therefore, the clock generator 1 receives the clock pulse C
The address generator 4 sequentially counts the clock pulses CP and sends the logical value "°1" to the output line of the tree corresponding to the counted value as the address signal ADi,
Output sequentially as i=1.2...m. Therefore, the same address signal ADi (logical value "1") is applied to the address input sides of the random access memory 6 and the read-only memory 7.
´°) is done manually. The read-only memory 7 receives this address signal ADi and sequentially outputs pre-stored predetermined rhythm patterns as a rhythm pattern signal rP. The light emitting diode 9 receives this rhythm pattern signal rP and starts blinking in the predetermined rhythm pattern. Moreover, this rhythm pattern signal rP is transmitted to the AND circuit 10.
The input signal is input manually to the first input terminal of the input terminal.

At this time, since the logical value "1" is input to the second input terminal of the AND circuit 10 via the write/read designation switch 8, the AND condition is established in the AND circuit 10, and the rhythm pattern signal rP is The first input terminal C1 of the rhythm sound source circuit 12 via an AND circuit 10 and an OR circuit 11
is man-powered. Therefore, the sound source circuit (cymbal sound) corresponding to the first input terminal C1 of the rhythm sound source circuit 12 is driven in synchronization with the blinking of the light emitting diode 9, and the above-mentioned rhythm pattern signal r stored in the read-only memory 7 is driven.
In response to P, the sound system 13 starts generating cymbal sounds.

The performer uses his eyes and ears to detect the blinking of the light emitting diode 9 and the sound of the cymbal sound, which occur in synchronization.
The generation tempo of the address signal ADi (i=1 to m) can be sensed. The reason for this is that, as mentioned above, the blinking cycle of the light emitting diode 9 and the sounding cycle of the cymbal sound are set manually by the address signal ADi inputted into the read-only memory 7.
This is because it is determined by the rhythm pattern signal rP read out from the read-only memory 7 with i=1.2...m. Therefore, while sensing the generated tempo of the address signal ADi by the blinking of the light emitting diode and the cymbal sound, the performer follows each of the switches S1 to S1 of the pattern forming switch section 5 (all or part of the keyboard) according to the generated tempo.
By appropriately immersing Sn, it is possible to store n types of rhythm patterns in the random access memory 6.

Part of the address signal ADi from the address generator 4
is being input to the random access memory 6 every moment.

Therefore, at a certain timing, the switch Sj in the rhythm pattern forming switch section 5 is engaged, and at that timing, the address signal A is output from the address generator 4.
If Di is manually input, the rhythm pattern corresponding to the switch Sj is written to the first address (i, j) in the first row of the random access memory 6.

That is, when a performer wants to write a specific rhythm pattern at a specific timing during a performance, by turning on the switch Sj corresponding to the specific rhythm pattern and specifying a row, the address signal A representative of that timing is written.
A column is specified by Di, and the above-mentioned specific rhythm pattern is written to the address ci, j) in the random access memory 6 determined as a result.

At this time, if it is difficult to operate all the switches S1 to Sn of the pattern forming switch section 5 in one rhythm pattern writing operation, the rhythm pattern writing operation described above may be repeated several times. However, in this case, it is necessary to take measures to prevent the rhythm patterns already written in each row of the random access memory 6 from being erased by the repeated rhythm pattern writing operations. As an example, a row of the writable random access memory 6 (corresponding to each switch S1 to Sn) can be specified from outside the random access memory 6.
What is necessary is to configure the random access memory 6. In addition, if the generation speed of the address signal ADi is fast and the tempo of writing the rhythm pattern (blinking of the light emitting diode 9 and the sound generation period of the cymbal sound) is too fast for the performer, the variable resistor 3 provided in the clock generator 1 By adjusting the period of the generated clock pulse, the address signal ADi sequentially outputted from the address generator 4 can be generated slowly, thereby slowing down the writing tempo of the rhythm pattern.

9 pieces of rhythm pattern readout (tora player reads rhythm patterns from random access memory 6)
In order to read out and play, first, set the write/read designation switch 8 to the fixed contact R side. As a result of this 7, the logical value "0°" is input to the write/read command terminal W/R of the random access memory 6, so the random access memory 6 becomes in a readable state.Next, when the start switch 2 is depressed, , since the reset terminals R of clock generator 1 and address generator 4 are both grounded, clock generator 1
and the address generator 4 are both released from the reset state. Therefore, the clock generator 1 starts generating clock pulses CP, and the address generator 4 sequentially counts the clock pulses CP and sets the logical value °°1'' to the output line corresponding to the counted value as the address signal ADi,i.
Output as =1.2...m. Since the random access memory 6 is in a readable state as described above,
In response to this address signal ADi (logical value "1"), n types of rhythm patterns stored in the rhythm pattern writing operation are read out and output from output terminals 81 to Bn as rhythm pattern signals RPI to RPn, respectively. For example, when it comes to the "specific timing" that I mentioned when writing,
Address signal ADi is input from address generator 4 to designate column i in random access memory 6 to be read. In this column i, there is a row j, that is, an address (
Since a "specific rhythm pattern" is written in i, j), this is read out. This "specific rhythm pattern" is specified by the performer by pressing the switch Sj at the "specific timing" when writing. The rhythm sound source circuit 12 receives the rhythm pattern signals RPI to RPn at input terminals C1 to Cn, respectively (only the rhythm pattern signal RPI passes through the OR circuit 11), and generates n types of rhythm sounds according to each rhythm pattern signal RPI to RPn. Output signals sequentially. These n types of rhythm sound signals are manually input to the sound system 13,
As a result, sounds are generated according to each rhythm pattern stored in the random access memory 6.

At this time, the read-only memory 7 also receives the address signal A.
Since Di is inputted, the lead memory 7 outputs the rhythm pattern signal rP.

However, this rhythm pattern signal rP is
Since the logical value "0" is manually input to the second input terminal of 0 and the AND condition is not satisfied in the AND circuit 10, the input terminal C of the rhythm sound source circuit 12 is cut off by the AND circuit 10.
1 is not man-powered.

Therefore, the rhythm sound generation by the rhythm pattern stored in the random access memory 6 is not affected in any way.

FIG. 2 shows a second embodiment of the present invention, in which an automatic rhythm playing device is provided with a synchronized start function with an electronic musical instrument. The synchronized start function is a function that automatically drives the automatic rhythm performance device at the same time as the electronic musical instrument starts playing, when a performer uses both an automatic rhythm performance device and an electronic musical instrument to perform. In a rhythm performance device that is not provided with a key, the timing of a key press on the electronic musical instrument often does not coincide with the start time of the rhythm performance device, and it is inevitable that the start of the performance will be very unnatural. Incidentally, in FIG. 2, the same parts as in FIG. 1 are given the same reference numerals, and the explanation thereof will be omitted. In addition, the clock generator 1 in FIG. 1 is a variable resistor 3.
The address generator 4 in FIG. 1 is replaced by an oscillator 1 whose oscillation frequency can be adjusted.

In FIG. 2, the movable contact of the start switch 2 is connected to the positive voltage source +V, and its fixed contact is connected to the capacitor 2.
Connected to one end of 2. The other end of the capacitor 22 is connected to a second input terminal of an OR circuit 24 on one side and grounded via a resistor 23 on the other side. A logic value "l" is input to one end of the automatic return type stop switch 21, and the other end is connected to the first input terminal of the OR circuit 24. The output side of the OR circuit 24 is connected to the offset terminal S of the Rs type rough flip-flop 2. The pattern forming switch section 5 includes switches 51 to Sn, Sn+1
A logical value "1" is input to one end of each switch Sl to Sn, Sn+1, and the other end is connected to the input side of the OR circuit 26, respectively. These switches S1 to Sn and Sn+11 are used as all or part of the keyboard of an electronic musical instrument equipped with the automatic rhythm performance device of this embodiment. Further, the signal line 25 is led from the electronic musical instrument, and is a key-on signal KON (logical value "
1"). This signal line 25 is connected to the input end of the OR circuit 26. Further, the other end of each switch 51 to Sn of the pattern forming switch section 5 is connected to the first
It is connected to the 8th write input terminal A1xAn of the random access memory 6 as in the embodiment.

The output terminal Q of the flip-flop 27 is connected to the oscillator 1 and the reset terminal R of the shift register 4 on the one hand, and to the input terminal of the differentiating circuit 28 on the other hand. In this case, the differentiating circuit 28 uses the logical value of the human input signal "
The output side of the differentiating circuit 28 is connected to the second input terminal of an OR circuit 30 via a delay circuit 29. Further, the output side of the oscillator 1 is connected to the first input terminal of the OR circuit 30, and the output side of the OR circuit 30 is connected to the shift input terminal S of the shift register 4. is connected to the address input terminal of the random access memory 6 and the read address input terminal of the read-only memory 7 on the one hand as in the first embodiment, and on the other hand to the input terminal C of the shift register 4 via the NOR circuit 31. Hereinafter, for convenience, the rhythm pattern writing operation and the rhythm pattern reading operation will be explained separately.

Rhythm pattern writing operation When a performer writes and sets a rhythm pattern, first,
The write/read designation switch 8 is set to the fixed contact W side. As a result, the random access memory 6 becomes writable as in the first embodiment. Next, start switch 2 is set to immersion. As a result, the positive voltage +V is differentiated by a differentiating circuit made up of a capacitor 22 and a resistor 23 to form one pulse. This pulse is input to the set terminal S of the flip-flop 27 via the OR circuit 24. Therefore, the output terminal Q of the flip-flop 27 outputs the logical value "1" (positive potential). The oscillator 1 and the shift register 4 receive this logical value "1°" at their reset terminals R and are reset together. In this case,
The differentiating circuit 28 also receives this logical value "1", but as mentioned above, the differentiating circuit 28 is configured to function for a change from the logical value "1°" to the logical value "0". , the differentiating circuit 28 does not operate and generates no pulses.

Therefore, the shift register 4 maintains the reset state, and all the outputs of each stage appearing on the output side of the shift register 4 have a logical value of "0". Therefore, the logical value ``1'' is input to the input terminal C of the shift register 4 via the NOR circuit 31.

Next, the switches S1 to Sn are activated by the player.

When at least one switch among Sn+f is turned on, a logical value "t" is input to the OR circuit 26. Here, as an example, it is assumed that the switch St is set to be on. By setting the switch S1, the reset 1 of the flip-flop 27;
1°° is input, which causes flip-flop 27
is inverted, and the output terminal Q outputs the logic value "Ooo". Therefore, the logic value "0" is input to the reset terminal R of the oscillator 1 and the shift register 4, and the reset state of both is released.

At the same time, the difference circuit 28 detects that the output terminal Q of the flip-flop 27 changes from the logic value "1" to the logic value "0".
Since the differential circuit 28 is manually operated, the differentiating circuit 28 generates one pulse. After this pulse is delayed by a minute time by the delay circuit 29, it is inputted to the shift input terminal S of the shift register 4 via the OR circuit 30. As mentioned above, the logical value “ is input to the input terminal C of the shift register 4 via the NOR circuit
1" is manually input, so when the above pulse is input to the shift input terminal S, the logical value "1" is stored in the first stage of the shift register 4. In this case, the delay time caused by the delay circuit 29 is extremely long. Because the setting is short, the first shift register 4 is turned on almost simultaneously with the switch S1 being engaged.
A logical value "1" is stored in the stage. Therefore, the shift register 4 outputs the address signal ADI (logical value "1°") to its first output line almost simultaneously with the retraction of the switch S1.
Output. This address signal ADI selects n addresses (1, 1) in the first column of the random access memory 6.
), (1, 2), . . . (1, n) are specified and become writable. In this case, as described above, switch S1
is input, the logical value “
1” is stored.

In the above explanation, we have explained the case where only switch S1 is set to close, but even if multiple switches are set to be closed, output is performed from these switches to random access memory 6 in exactly the same way. The logical value ``1'' is stored at each address (1,j) j=1.2...n in the first column of the random access memory 6. Here, the switch Sn+1 is used when the first beat of the rhythm pattern is a rest for all n types of rhythm tones.

In parallel with the above operations, the reset state of the oscillator 1 is released. Therefore, the oscillator 1 starts generating a clock pulse CP, and the generated clock pulse CP is transmitted to the OR circuit 3.
0 to the shift input terminal S of the shift register 4. The shift register 4 receives this clock pulse C.
According to P, the logic value "1" stored in the first stage is shifted to the second and third stages one after another. As a result, the shift register 4 receives the address signal ADt.

1==2.3...m are output one after another. At this time, the input terminal C of the shift register 4 receives the address signal ADi.
, i=1.2...m (logical value "1") is inverted by the three NOR circuits, so the logical value "0" is input. Therefore, only one initially written logic value "1" exists in the shift register 4, and as described above, this is sequentially shifted to form the address signal ADi.

The subsequent rhythm pattern writing operation is performed in exactly the same manner as in the first embodiment. That is, the performer operates the rhythm pattern forming switch 5, that is, the keyboard, while sensing with his eyes and ears the blinking of the light emitting diode 9 and the sound of the cymbal sound, which occur in synchronization with each other, to create n different types of data in the random access memory 6. Rhythm patterns for rhythm sounds can be memorized.

Rhythm Pattern Reading Operation When a performer reads a rhythm pattern from the random access memory 6 and performs it, the write/read designation switch 8 is first set to the fixed contact R side. As a result, similar to the first embodiment, the random access memory 6
becomes readable. Next, the performer turns on the start switch 2. As a result, the oscillator 1 and shift register 4 are placed in a reset state, just as in the rhythm pattern writing operation of the second embodiment described above. At this time, all outputs of each stage of the shift register 4 have a logical value of "0".

Next, when the performer presses the key of the electronic musical instrument and starts playing, a key-on signal KON is sent from the electronic musical instrument to the signal line 25 at this moment.
(Logic value “1”) is output.

Since this key-on signal KON is input to the reset terminal R of the flip-flop 27 via the OR circuit 26, the flip-flop 27 is inverted and its output terminal Q is a logic value "
0". Therefore, oscillator 1 and shift register 4
A logical value "0°" is input to the reset terminal R of the two, and the reset state of both is released. At this time, the logic value of the output terminal Q of the flip-flop 27 changes from the logic value "1" to the logic value "0".
Since the change to is input manually to the differentiating circuit 28, the differentiating circuit 2
8 generates one pulse. This pulse is input to the shift input terminal S of the shift register 4 via the delay circuit 29 and the OR circuit 30, and the input terminal C of the shift register 4 is supplied to the input terminal C of the shift register 4 through the NOR circuit. 31, the logical value “1” is input manually, so the logical value “1” is input to the first stage of the shift register 4.
°1". In this case, since the delay time of the delay circuit 29 is set to be very short as described above, the shift register 4 receives the address signal A at the same time as the key of the electronic musical instrument is pressed.
Outputs DI (logical value “1”). This address signal A
n of the first column of the random access memory 6 by DI
addresses (1,1), (1,2)..., (1,n
) is specified and its contents are rhythm pattern signals RPI~R.
It is output as Pn.

In parallel with the above operation, the reset state of the oscillator 1 is released. Therefore, the shift register 4 starts generating clock pulses CP, and the generated clock pulses CP are sequentially input to the shift input terminal S of the shift register 4 via the OR circuit 30. The shift register 4 sequentially shifts the logical value "1" stored in the first stage to the second and third stages in accordance with the clock pulse CP.

As a result, the address signal ADi (i=2, 3...
m) are output one after another.

Address signals ADi% i sequentially generated in this way
=2.3...m, the n types of rhythm patterns stored in each column of the random access memory 6 by the rhythm pattern writing operation are the rhythm pattern signals RPI~
They are read out one after another as RPn. The rhythm sound source circuit 12 is driven by the rhythm pattern signals RPI to RPn, and various rhythm sounds are generated from the sound system 13, just as in the first embodiment.

When the performance is finished, by pressing the stop switch 21, the logic value "1" is changed to the flip-flop 27.
Manual input is applied to the set terminal S of.

Flip-flop 27 is therefore inverted and its output terminal Q
outputs a logical value “1”. As a result, both the oscillator 1 and the shift register 4 are reset again.

As is clear from the above description, according to the second embodiment of the present invention, the key-on signal KON (logical value "1") is output to the signal line 25 at the same time as the key of the electronic musical instrument is pressed, and thereby Since the shift register 4 is configured to output the address signal ADI, the automatic rhythm performance device is driven at the same time as the key is pressed.

Therefore, a synchronized start with a so-called electronic musical instrument can be performed reliably.

In addition, in this invention, by increasing the storage capacity of the random access memory 6 (for example, by configuring the random access memory 6 with a plurality of chips of memory).
In addition to storing rhythm patterns for a song, it is also possible to store a plurality of different rhythm patterns so that a performer can perform different songs in succession. In this case, the random access memory 6 is divided into a plurality of groups (for example, when the random access memory 6 is composed of a plurality of chips, each chip may be treated as one group), and each group is A designated switch for designation may be provided in the random access memory 6.

[Effects of the Invention] As is clear from the above description, the automatic performance device according to the present invention can create any rhythm pattern according to the player's will by writing and reading rhythm patterns using a writable storage means. It allows you to set up and play.

In addition, the sound generation timing (column) and sound source type (row) for specifying the storage position in the storage means is automatically advanced at a predetermined period based on the output from the clock generation means. It eliminates the need for manual input and reduces the number of manipulators in memory locations. Furthermore, by displaying the output signal from the clock generating means or the address generating means as a rhythm tempo, it is easy to sense the timing of sound generation. Therefore, according to the apparatus of the present invention, the player can freely and easily set or change the rhythm pattern, and can easily and quickly perform the settings or changes in parallel with the performance. Further, since the rhythm pattern can be written using a keyboard, there is no need to provide a switch for this purpose, and the device can be made much smaller than conventional ones.

[Brief explanation of the drawing]

FIG. 1A is a block diagram showing a first embodiment of the present invention;
FIG. 1B is an explanatory diagram showing the contents of a random access memory, and FIG. 2 is a block diagram showing a second embodiment of the invention. 1... Clock generator, 2...
Start switch, 4...address generator, 5...pattern formation switch section, 6...
... Random access memory, 7 ... Read only memory, 8 ... Write/read designation switch, 9 ... Light emitting diode, 10 ...
...AND circuit, 11,24°26.30...
...OR circuit, 12...Rhythm sound source circuit, 13
...Sound system, 21...Stop switch, 28...Differential circuit, 29...
...Delay circuit, KON...Key-on signal, A
Di...address signal, RPI~RPn...
...Rhythm pattern signal. Kuζ Kuζ

Claims (1)

[Claims] (1) A clock generating means for generating a frequency signal of a predetermined period, a memory position signal generating means for generating a memory position signal regarding the sound timing based on the output signal from the clock generating means, and all or part of the keyboard of the electronic musical instrument. a keyboard which also functions as a keyboard and specifies a storage position related to the type of sounding instrument by operating the keyboard, and a storage position signal generated by the storage position signal generating means and a storage position specified by the keyboard, which performs writing and reading. A storage location is specified, and in the storage location,
a storage means in which a rhythm pattern corresponding to each rhythm sound source is written by the operation of the keyboard; a rhythm tempo display means for representing a rhythm tempo by an output signal from the clock generation means or the storage position signal generation means; An automatic rhythm performance device comprising: a rhythm sound source circuit that receives a plurality of read rhythm pattern signals and outputs a plurality of rhythm sound signals.