JPH0275825U - - Google Patents
Info
- Publication number
- JPH0275825U JPH0275825U JP15530588U JP15530588U JPH0275825U JP H0275825 U JPH0275825 U JP H0275825U JP 15530588 U JP15530588 U JP 15530588U JP 15530588 U JP15530588 U JP 15530588U JP H0275825 U JPH0275825 U JP H0275825U
- Authority
- JP
- Japan
- Prior art keywords
- converter
- reference voltage
- resistor
- circuit
- voltages
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Analogue/Digital Conversion (AREA)
Description
第１図は本発明の実施例を示す回路図、第２図
は第１図の実施例のクロツク信号用バツフア回路
の具体例を示す回路図、第３図は第２図のクロツ
ク信号用バツフア回路からのクロツク信号の供給
される回路の一例としての排他的論理和回路の具
体例を示す回路図、第４図は従来例を示す回路図
である。
１はＡ／Ｄ変換器、２は基準電圧発生用抵抗器
、３はレベル比較器、４はトランジスタ、５はク
ロツク信号用バツフア回路である。
1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a specific example of the clock signal buffer circuit of the embodiment of FIG. 1, and FIG. 3 is a circuit diagram of the clock signal buffer circuit of the embodiment of FIG. FIG. 4 is a circuit diagram showing a specific example of an exclusive OR circuit as an example of a circuit to which a clock signal is supplied from the circuit, and FIG. 4 is a circuit diagram showing a conventional example. 1 is an A/D converter, 2 is a reference voltage generating resistor, 3 is a level comparator, 4 is a transistor, and 5 is a clock signal buffer circuit.
Claims (1)
するための抵抗器の一端に第１の基準電圧を与え
、該抵抗器の他端に、上記第１の基準電圧とは異
なる第２の基準電圧を与えるようにしたＡ／Ｄ変
換器において、 上記抵抗器の他端と、上記第１及び第２の基準
電圧とは異なる第３の基準電圧の与えれる点との
間に、上記Ａ／Ｄ変換器に使用される回路を接続
するようにして成るＡ／Ｄ変換器。[Claims for Utility Model Registration] A first reference voltage is applied to one end of a resistor for generating a plurality of reference voltages to be supplied to a plurality of comparators, and the first reference voltage is applied to the other end of the resistor. In an A/D converter configured to provide a second reference voltage different from the voltage, the other end of the resistor and a point where a third reference voltage different from the first and second reference voltages is provided. An A/D converter, in which a circuit used in the A/D converter is connected between the A/D converter and the A/D converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15530588U JPH0275825U (en) | 1988-11-29 | 1988-11-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15530588U JPH0275825U (en) | 1988-11-29 | 1988-11-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0275825U true JPH0275825U (en) | 1990-06-11 |
Family
ID=31432817
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15530588U Pending JPH0275825U (en) | 1988-11-29 | 1988-11-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0275825U (en) |
-
1988
- 1988-11-29 JP JP15530588U patent/JPH0275825U/ja active Pending
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