JPH0274096A - Manufacture of circuit substrate - Google Patents
Manufacture of circuit substrateInfo
- Publication number
- JPH0274096A JPH0274096A JP22574388A JP22574388A JPH0274096A JP H0274096 A JPH0274096 A JP H0274096A JP 22574388 A JP22574388 A JP 22574388A JP 22574388 A JP22574388 A JP 22574388A JP H0274096 A JPH0274096 A JP H0274096A
- Authority
- JP
- Japan
- Prior art keywords
- plating
- pattern
- fusing
- electrolytic
- metal resist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 title 1
- 238000007747 plating Methods 0.000 claims abstract description 50
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000011248 coating agent Substances 0.000 claims abstract description 5
- 238000000576 coating method Methods 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 abstract description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011889 copper foil Substances 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 description 5
- PEDCQBHIVMGVHV-UHFFFAOYSA-N Glycerine Chemical compound OCC(O)CO PEDCQBHIVMGVHV-UHFFFAOYSA-N 0.000 description 2
- 239000011888 foil Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000011187 glycerol Nutrition 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/062—Etching masks consisting of metals or alloys or metallic inorganic compounds
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は回路基板の製造方法に関し、さらに詳しく言
えば、パターンメッキ法による配線パターン形成時のサ
イドエツチング防止方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a circuit board, and more specifically, to a method for preventing side etching when forming a wiring pattern by pattern plating.
パターンメッキ法によると、まず、銅張積層板上にドラ
イフィルムフォトレジストがラミネートされ、その上に
所定の回路パターンを有するワークフィルムが載置され
、Ｕｖ（紫外線）露光が行なわれる。そして、現像によ
り例えば未露光部分が除去され、その除去部分に電解パ
ターンメッキが施される６同電解パターンメッキ上に金
属レジストメッキが形成され、しかるのち上記ドライフ
ィルムフォトレジストが除去される１次に、上記金属レ
ジストメッキをマスクとして不要の金属が除去され、引
き続き上記金属レジストメッキを剥離することにより、
上記電解パターンメッキよりなる配線パターンが得られ
る。According to the pattern plating method, first, a dry film photoresist is laminated on a copper-clad laminate, a work film having a predetermined circuit pattern is placed thereon, and UV (ultraviolet rays) is exposed. Then, for example, unexposed areas are removed by development, and electrolytic pattern plating is applied to the removed areas.6 Metal resist plating is formed on the electrolytic pattern plating, and then the dry film photoresist is removed. Next, unnecessary metal is removed using the metal resist plating as a mask, and by subsequently peeling off the metal resist plating,
A wiring pattern made of the electrolytic pattern plating described above is obtained.
しかしながら、従来においては、金属レジストメッキを
マスクとして不要の金属を除去する際に。However, in the past, metal resist plating was used as a mask when removing unnecessary metal.
電解パターンメッキの両側部分までもがエツチング（サ
イドエツチング）されてしまい、パターン幅が狭くなっ
てしまうという問題が生ずる。A problem arises in that even both sides of the electrolytic pattern plating are etched (side etching), resulting in a narrow pattern width.
この発明は上記従来の事情に鑑みなされたもので、その
目的は、サイドエツチングを防止して、所定のパターン
幅が得られるようにした回路基板の製造方法を提供する
ことにある。The present invention has been made in view of the above-mentioned conventional circumstances, and its object is to provide a method for manufacturing a circuit board in which side etching can be prevented and a predetermined pattern width can be obtained.
上記目的を達成するため、この発明においては、金属張
積層板上にドライフィルムフォトレジストをラミネート
するとともに、その上に所定の回路パターンを有するワ
ークフィルムを載置し、露光、現像したのち１回路とな
る部分に電解パターンメッキを施し、同電解パターンメ
ッキ上に金属レジストメッキを形成し、上記ドライフィ
ルムフォトレジストを除去し、上記金属レジストメッキ
をマスクとして不要の金属を除去したのち、上記金属レ
ジストメッキを剥離することにより、上記電解パターン
メッキよりなる配線パターンを得る回路基板の製造方法
において、
上記ドライフィルムフォトレジストを除去したのち、フ
ュージングを行ない、上記金属レジストメッキを溶融さ
せて、配線パターンとなる上記電解パターンメッキの側
部にまで同金属レジストメッキの被覆を形成することを
特徴としている。In order to achieve the above object, in this invention, a dry film photoresist is laminated on a metal-clad laminate, a work film having a predetermined circuit pattern is placed thereon, exposed and developed, and then one circuit is formed. Electrolytic pattern plating is applied to the portions that will become In the method for manufacturing a circuit board, in which a wiring pattern made of the electrolytic pattern plating is obtained by peeling off the plating, the dry film photoresist is removed and then fusing is performed to melt the metal resist plating to form the wiring pattern. The present invention is characterized in that a coating of the same metal resist plating is formed even on the sides of the electrolytic pattern plating.
上記のように、フュージングを行うことによって、電解
パターンメッキの側部にまで金属レジストメッキが被覆
されるため、サイドエツチングが防止される。As described above, by performing fusing, the sides of the electrolytic pattern plating are covered with the metal resist plating, thereby preventing side etching.
以下、この発明の実施例を添付図面を参照しながら詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
この実施例においては、金属張積層板として紙−フェノ
ール樹脂板６ｂ上に銅箔６ａを形成してなる銅張積層板
６が用いられている。第１図（ａ）を参照すると、まず
、銅張積層板６上にドライフィルムフォトレジスト３が
ラミネートされ、その上に例えば回路パターン部分を黒
色部１ｂ、その他の部分を透明部１ａとしたネガワーク
フィルム１が載置される。そして、Ｕｖ（紫外線）が照
射され、透明部１ａに対応するドライフィルムフォトレ
ジスト３が露光される０次に、黒色部１ｂに対応する未
露光部分が現像により除去される（同図（ｂ）参照）、
この除去部分に、配線パターンとなる電解パターンメッ
キ４が施される（同図（Ｃ）参照）。In this embodiment, a copper-clad laminate 6 is used as the metal-clad laminate, in which a copper foil 6a is formed on a paper-phenol resin board 6b. Referring to FIG. 1(a), first, a dry film photoresist 3 is laminated on a copper-clad laminate 6, and then a negative film is formed on the copper-clad laminate 6, with a black portion 1b for the circuit pattern portion and a transparent portion 1a for the other portions. A work film 1 is placed. Then, the dry film photoresist 3 corresponding to the transparent area 1a is exposed to Uv (ultraviolet rays). Next, the unexposed area corresponding to the black area 1b is removed by development (FIG. 1(b)). reference),
Electrolytic pattern plating 4, which will become a wiring pattern, is applied to this removed portion (see FIG. 4C).
さらに、この電解パターンメッキ４上に金属レジストメ
ッキ、この例ではハンダメツキ５が施される（同図（ｄ
）参照）。ドライフィルムフォトレジスト３が除去され
たのち（同図（ｅ）参照）、フュージング（Ｆｕｓｉｎ
ｇ）が行なわれる。これにより、ハンダメツキ５が溶融
し、同図（ｆ）に示されているように、電解パターンメ
ッキ４のサイド部分にまでハンダメツキ５の被覆が形成
される。そして、エツチングにより不要な同箔６ａが除
去され、引き続き、ハンダメツキ５がエツチングにより
除去される。このようにして、最終的に同図（ｇ）に示
されているように、残された電解パターンメッキ４とそ
の下地としての銅箔６ａよりなる配線パターンが形成さ
れるのであるが、この方法によると、不要な同箔６ａを
エツチングにより除去する際、電解パターンメッキ４の
サイド部分がエツチングされないため、所望とする幅の
配線パターンが形成される。Furthermore, metal resist plating, in this example, solder plating 5 is applied on this electrolytic pattern plating 4 (see figure (d).
)reference). After the dry film photoresist 3 is removed (see (e) in the same figure), fusing is performed.
g) is carried out. As a result, the solder plating 5 is melted, and the side portions of the electrolytic pattern plating 4 are covered with the solder plating 5, as shown in FIG. 5(f). Then, the unnecessary foil 6a is removed by etching, and subsequently the solder plating 5 is removed by etching. In this way, a wiring pattern consisting of the remaining electrolytic pattern plating 4 and the copper foil 6a as its base is finally formed, as shown in FIG. According to the above, when unnecessary foil 6a is removed by etching, the side portions of electrolytic pattern plating 4 are not etched, so that a wiring pattern with a desired width is formed.
なお、フュージングは１例えば２００〜２２０℃の市販
のフュージングオイルまたはグリセリン液中に浸漬する
オイルフュージング、もしくは赤外線ランプを有する装
置内における赤外線フュージングのいずれでもよい。Incidentally, the fusing may be performed by either oil fusing, which involves immersion in a commercially available fusing oil or glycerin liquid at 200 to 220° C., or infrared fusing in a device equipped with an infrared lamp.
以上説明したように、この発明によれば、パターンメッ
キ法において、ドライフィルムフォトレシストを除去し
たのち、フュージングを行ない、金属レジストメッキを
溶融させて、配線パターンとなる電解パターンメッキの
側部にまで同金属レジストメッキの被覆を形成するよう
にしたことにより、電解パターンメッキのサイドエツチ
ングが確実に防止される。As explained above, according to the present invention, in the pattern plating method, after the dry film photoresist is removed, fusing is performed to melt the metal resist plating and reach the sides of the electrolytic pattern plating that will become the wiring pattern. By forming a coating of the same metal resist plating, side etching of the electrolytic pattern plating can be reliably prevented.
第１図（ａ）〜（ｇ）はこの発明による回路基板の製造
方法をその工程にしたがって示した要部断面図である。
図中、１はワークフィルム、３はドライフィルムフォト
レジスト、４は電解パターンメッキ、５はハンダメツキ
、６は銅張積層板である。
（ｅ）
特許出願人 エルナー株式会社
代理人 弁理士 大 原 拓 也（ｆ）FIGS. 1(a) to 1(g) are cross-sectional views of essential parts showing the process of manufacturing a circuit board according to the present invention. In the figure, 1 is a work film, 3 is a dry film photoresist, 4 is electrolytic pattern plating, 5 is solder plating, and 6 is a copper-clad laminate. (e) Patent applicant: ELNA Co., Ltd. Agent: Patent attorney: Takuya Ohara (f)
Claims (3)
をラミネートするとともに、その上に所定の回路パター
ンを有するワークフィルムを載置し、露光、現像したの
ち、回路となる部分に電解パターンメッキを施し、同電
解パターンメッキ上に金属レジストメッキを形成し、上
記ドライフィルムフォトレジストを除去し、上記金属レ
ジストメッキをマスクとして不要の金属を除去したのち
、上記金属レジストメッキを剥離することにより、上記
電解パターンメッキよりなる配線パターンを得る回路基
板の製造方法において、 上記ドライフィルムフォトレジストを除去したのち、フ
ュージングを行ない、上記金属レジストメッキを溶融さ
せて、配線パターンとなる上記電解パターンメッキの側
部にまで同金属レジストメッキの被覆を形成することを
特徴とする回路基板の製造方法。(1) Laminate a dry film photoresist on a metal-clad laminate, place a work film with a predetermined circuit pattern on top of it, expose it to light, develop it, and then apply electrolytic pattern plating to the part that will become the circuit. , a metal resist plating is formed on the electrolytic pattern plating, the dry film photoresist is removed, unnecessary metal is removed using the metal resist plating as a mask, and the metal resist plating is peeled off. In a method for manufacturing a circuit board that obtains a wiring pattern by pattern plating, after removing the dry film photoresist, fusing is performed to melt the metal resist plating and apply it to the sides of the electrolytic pattern plating that will become the wiring pattern. A method of manufacturing a circuit board, comprising forming a coating of the same metal resist plating.
求項１記載の回路基板の製造方法。(2) The method for manufacturing a circuit board according to claim 1, wherein the fusing is oil fusing.
求項１記載の回路基板の製造方法。(3) The method for manufacturing a circuit board according to claim 1, wherein the fusing is infrared fusing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22574388A JPH0274096A (en) | 1988-09-09 | 1988-09-09 | Manufacture of circuit substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22574388A JPH0274096A (en) | 1988-09-09 | 1988-09-09 | Manufacture of circuit substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0274096A true JPH0274096A (en) | 1990-03-14 |
Family
ID=16834143
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22574388A Pending JPH0274096A (en) | 1988-09-09 | 1988-09-09 | Manufacture of circuit substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0274096A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113133217A (en) * | 2020-01-15 | 2021-07-16 | 鹏鼎控股(深圳)股份有限公司 | Preparation method of circuit board |
-
1988
- 1988-09-09 JP JP22574388A patent/JPH0274096A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113133217A (en) * | 2020-01-15 | 2021-07-16 | 鹏鼎控股(深圳)股份有限公司 | Preparation method of circuit board |
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