KR880001191A - Manufacturing Method of Printed Circuit Board - Google Patents

Manufacturing Method of Printed Circuit Board Download PDF

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Publication number
KR880001191A
KR880001191A KR1019860005011A KR860005011A KR880001191A KR 880001191 A KR880001191 A KR 880001191A KR 1019860005011 A KR1019860005011 A KR 1019860005011A KR 860005011 A KR860005011 A KR 860005011A KR 880001191 A KR880001191 A KR 880001191A
Authority
KR
South Korea
Prior art keywords
plating
layer
copper foil
manufacturing
resist
Prior art date
Application number
KR1019860005011A
Other languages
Korean (ko)
Other versions
KR890002447B1 (en
Inventor
이동만
문길상
Original Assignee
이동만
문길상
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이동만, 문길상 filed Critical 이동만
Priority to KR1019860005011A priority Critical patent/KR890002447B1/en
Publication of KR880001191A publication Critical patent/KR880001191A/en
Application granted granted Critical
Publication of KR890002447B1 publication Critical patent/KR890002447B1/en

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Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

내용 없음No content

Description

인쇄회로 기판의 제조 방법Manufacturing Method of Printed Circuit Board

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제1도는 본 발명에 따라 완성된 인쇄회로 기판의 요부 발췌 사시도. 제3도(가) 내지(차)는 제2도의 A-A 선을 절단한 상태에서의 본 발명의 일 실시예를 나타낸 제조 공정도.1 is a perspective view of main parts of a printed circuit board completed according to the present invention. 3 (a) to (d) are manufacturing process diagrams showing an embodiment of the present invention in the state cut along the line A-A of FIG.

Claims (3)

표면에 동박(3)이 접합되고 홀(2)이 가공된 적층판(1)상에 배선패턴 형태를 따라 인쇄 또는 사진방식으로 에칭 레지스트부(4)를 형성시킨 다음, 상기 에칭 레지스트부(4)를 제외한 동박(3) 부위를 부식액으로 부식 제거 시킨후 에칭 레지스트부(4)를 제거하여 잔여동박에 의한 배선도체를 구성한 다음, 배선 도체가 형성된 적층판(1)의 전체부위에 무전해동도금으로 전도성 동 피막층(6)을 형성한후, 홀(2)과 그 주위에 랜드부(31)를 제외한 전체 동 피막층(6) 상에 도금 레지드트층(7)을 도포 및 건조하고 나서, 상기 홀(2)과 랜드부(31)의 동피막층(6) 상에 전기 동도금에 의한 전기 동 도금층(8)을 형성하고, 그 상부에 전기 솔더 도금에 의한 전기 솔더 도금층(9)을 형성한뒤, 도금 레지스트층(7)을 제거시키면서 그 하부에 피막된 동 피막층(6)을 부식액으로 부식제거하여 완전한 배선도체를 만든 다음, 후처리 공정을 거쳐 제조 완성됨을 특징으로 하는 인쇄회로 기판의 제조방법.The etching resist portion 4 is formed on the laminated plate 1 on which the copper foil 3 is bonded to the surface and the hole 2 is processed, by printing or photographing method in accordance with the wiring pattern. After the corrosion of the copper foil (3), except for the portion of the copper foil (3) to remove the etching resist portion (4) to form a wiring conductor by the remaining copper foil, and then conduct the electroless copper plating on the entire portion of the laminated plate (1) where the wiring conductor is formed After the copper film layer 6 is formed, the plating resist layer 7 is applied and dried on the entire copper film layer 6 except the land portion 31 around the hole 2 and the surroundings thereof, and then the hole ( 2) and the electroplating layer 8 by electrocopper plating on the copper film layer 6 of the land part 31, the electroplating layer 9 by electrosolder plating is formed on the upper part, and then plating While removing the resist layer 7, the copper film layer 6 coated thereon is removed by corrosion. Made over the full power supply conductor, and then, after the treatment step of the manufacturing method of manufacturing a printed circuit board, characterized in that after completion. 제1항에 있어서, 에칭 레지스트부는 동박(3) 상에 도금 레지스트재를 역배선 패턴으로 도포하여 도금 레지스트층을 형성한뒤, 잔여 배선 패턴부위에 닉켈, 주석 또는 주석합금을 이용한 전기도금을 행하고 나서, 상기 도금 레지스트층을 제거하므로서 잔여 도금부로서 형성함을 특징으로 하는 인쇄회로 기판의 제조 방법.The etching resist portion is formed by applying a plating resist material on the copper foil 3 in a reverse wiring pattern to form a plating resist layer, and then performing electroplating using nickel, tin, or tin alloy on the remaining wiring pattern portions. And then forming the remaining plating portion by removing the plating resist layer. 제1항에 있어서, 에칭 레지스트부(4)에 의하여 배선도체가 형성된 적층판(1) 상에는 홀(2)과 랜드부(31)를 제외한 전체 표면에 솔더 레지스트부(5)를 인쇄 도포함을 특징으로 하는 인쇄회로 기판의 제조 방법.The method of claim 1, wherein the solder resist portion 5 is printed on the entire surface except the hole 2 and the land portion 31 on the laminated plate 1 having the wiring conductor formed by the etching resist portion 4. The manufacturing method of the printed circuit board. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019860005011A 1986-06-23 1986-06-23 Pcb making method KR890002447B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019860005011A KR890002447B1 (en) 1986-06-23 1986-06-23 Pcb making method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860005011A KR890002447B1 (en) 1986-06-23 1986-06-23 Pcb making method

Publications (2)

Publication Number Publication Date
KR880001191A true KR880001191A (en) 1988-03-31
KR890002447B1 KR890002447B1 (en) 1989-07-03

Family

ID=19250665

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019860005011A KR890002447B1 (en) 1986-06-23 1986-06-23 Pcb making method

Country Status (1)

Country Link
KR (1) KR890002447B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332970B1 (en) * 1998-12-08 2002-09-17 주식회사 심텍 Blind Via Hole for PCB and Method for Formation Thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100332970B1 (en) * 1998-12-08 2002-09-17 주식회사 심텍 Blind Via Hole for PCB and Method for Formation Thereof

Also Published As

Publication number Publication date
KR890002447B1 (en) 1989-07-03

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