JPH0273593A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent a potential reduction due to the time of a word line and to ensure a writing by connecting only a selected word line with a boosting means and pumping. CONSTITUTION:A clock CL1, when it is made into an H and a word line WL1 or the like is selected, is boosted by a capacitor Co through a word line driving circuit, a word selector or the like and nodes N and N1 turn to be a power source potential Vcc or more. Transistors (TR) Q1-Q3 are turned on, a pumping circuit is connected to the word line WL1, a time is leaked together through a capacitor C1 connecting with an oscillation circuit, the reducing potential of the nodes N and N1 is boosted, it is held to a higher potential for a long time and the writing of a sufficient potential is surely executed into selected memory cells MC1 and MC2....

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device which prevents potential drop in word lines and performs stable operation.

The memory operation of a dynamic random access memory (hereinafter abbreviated as DRAM), which is a conventional synchronous semiconductor memory device, is generally performed as follows. First, row decoding is performed, and then a word line is selected in accordance with the row decoding. Information of the memory cell selected by this selected word line appears on the bit line. Next, a sense operation amplifies the potential change appearing on the bit line. Next, column decoding is performed to extract one specific piece of information from among the information of each memory cell appearing on the plurality of bit lines, and after amplification, the output is determined and the read operation is completed. Here, the most important and difficult operation in a series of memory operations, reading information from a memory cell onto a bit line, will be explained using FIG. 2 of a conventional example. First, the word line drive circuit operates to drive the word line, and then the word line selector operates to drive only the word line selected by row decoding. Therefore, from clock CLI to CLN, N
One of the clocks, for example CLI, is selected and changes from low level to high level. Therefore, from the node N1 to the node NN, only the node N1 has the power supply voltage Vc
From c to the threshold voltage VT of the MOS transistor (hereinafter v
(abbreviated as T), and the other nodes remain at ground potential. Next, the word line drive circuit operates, and the node N goes from the ground potential to the normal power supply voltage, and the MOS
) The potential becomes higher than the threshold voltage of the transistor. As a result, the gate of transfer gate QTI and node N
Due to capacitive coupling with the node N1, the potential of the node N1 becomes sufficiently high, and the selected word line WLI becomes the same potential as the node N. The other word lines remain at ground potential because the gate potential of the transfer gate is sufficiently low. Next, access transistor Ql+ is connected to selected word line WLI.

Q12... turns on, memory cells MCII,
Information on MCI2... is transferred to bit line BL1. BL
2. Appears in... Here, since DRAM is characterized by a small chip area and a large capacity, the memory cell capacity usually has only a small capacity of several + fF. In order to obtain stable operation with such a small capacitance, it is necessary to increase the amount of charge stored in the memory cell as much as possible. Normally, the maximum potential of a bit line is the power supply voltage and the minimum potential is the ground potential, so the maximum potential written into the memory cell is also the power supply voltage, and the minimum potential is the ground potential. However, in order to write the power supply potential into the memory cell, the gate potential of the access transistor needs to be higher than the power supply voltage by the threshold value vT of the MOS transistor. Therefore, the word line is controlled by a word line drive circuit that boosts the voltage above the power supply voltage. In the case of a dynamic type, this voltage boosting stores charge in a capacitor Co, and connects the ground potential side of this capacitor to inverters I, , 1 . The ground potential is increased from the ground potential to the power supply voltage using the delay of , the node N is boosted to a potential sufficiently higher than the power supply voltage, and a sufficiently high potential is supplied to the selected word line WLI by capacitance distribution.

However, the potential of the node N decreases over time due to junction leakage current in the source and drain portions of the MOS transistor, for example. Therefore, the potential of the selected word line WL1 also decreases with time. , read, and write operations must be guaranteed.Therefore, the potential drop of the selected word line over time is a major cause of insufficient operating margin and unstable operation.

As a countermeasure against this, one method is to provide a pumping circuit (not shown) at the node N to compensate for the drop in potential at the node N.

Problems to be Solved by the Invention The conventional method is effective in reducing the potential of the node N in order to supply a sufficiently high potential to the selected word line WLI. However, the gate N of the transfer gate Qt+
1 similarly decreases in potential due to leakage current, so even if the potential decrease at node N is prevented, the gate potential of transfer gate QTI decreases in word line WLI, and charge cannot be replenished.

Therefore, the potential of word line WL1 decreases over time due to leakage current. access transistor Qll,
When the gate potential of memory cells MCl1. It becomes impossible to write to MCI2... up to the power supply voltage. This is a major drawback that hinders the stability of DRAM memory operation.

Means for Solving the Problems In order to solve the conventional problems, the present invention provides a plurality of memory cells arranged in rows and columns in a matrix, a plurality of word lines for row selection, and each of the plurality of word lines. A configuration comprising means for pumping and means for boosting to a voltage higher than a power supply voltage, wherein only a selected word line is connected to the boosting means, and only the selected word line is pumped by the pumping means. It is a semiconductor memory device equipped with

According to the present invention, only the pumping circuit connected to the selected word line operates, and the selected word line is constantly replenished with charge, preventing potential drop in the selected word line due to junction leakage current, etc. Information writing is always performed up to the power supply voltage, resulting in stable operation.

EXAMPLE An implementation If of the present invention is shown in FIG. To explain the most important exchange of information between memory cells in a series of memory operations of a DRAM, for example, CLI is selected from clocks CLI to CLN to select a word line, and changes from low level to high level. Other clocks remain low. Next, the word line drive circuit operates and boosts the voltage using the capacitor CO, so that a potential sufficiently higher than the power supply voltage is obtained at the node N. Transfer game-h Q
The gate node N1 of TI is lower than the power supply voltage Vcc.
The transistor has been charged to a potential lower by the threshold voltage VT, and due to capacitive coupling with node N, node N1 has a sufficiently high potential, and the selected word line ~ VLI has the same potential as node N, so that the power supply electrician can control the MOS transistor. The level becomes higher than the threshold value 71. As a result, it becomes possible to write to the selected memory cells M-C++, MC12, . . . via the bit lines BLI, BL2°, . . . up to the power supply voltage. On the other hand, the potential of the nodes N and N1 decreases over time due to leakage current at the junction, etc. The node N is replenished with charge by a pumping circuit (not shown) and the potential decrease is prevented, but the potential of the node N1
, a potential drop occurs. On the other hand, the selected word AIIWLI turns on the MOS transistor Q1, and the node NO is charged to a potential lower than the power supply voltage by the threshold value VT of the MOS transistor.
O is boosted and connected to word IWLI via Mos transistor Q3 at node N.

Charge is supplied from Therefore, no potential drop occurs in word IWLI. This replenishment of charges by the pumping circuit is always performed as long as the word line is selected, so the level of the word line is always kept sufficiently high, and the write potential to the memory cell does not drop.

Effects of the Invention According to the present invention, when the selected word line is kept at a high level for a long time to perform read and write operations, such as in page mode operation of DRAM, it is possible to prevent the level of the word line from dropping, and to prevent the level of the word line from decreasing. Sufficient potential can be written,
Stable operation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a circuit for reading and writing to a memory cell in an embodiment of the present invention, and FIG. 2 is a circuit diagram of a circuit for reading and writing to a memory cell in a conventional example. w r-1 ~ w L n, , , , word line, BLI
~BLn...Bit line, Ql ~Q3...
...MOS transistor, Qll, Ql2. QN
II QN2・・・Access transistor, QR
I, QRN, QTI, QTN...Decoding transistor, 1. ．． 12...Inverter. Name of agent: Patent attorney Shigetaka Awano and one other person Figure 1

Claims (1)

[Claims] comprising a plurality of memory cells arranged in rows and columns in a matrix, a plurality of word lines for row selection, means for pumping each of the plurality of word lines, and means for boosting the voltage to a level higher than a power supply voltage; A semiconductor memory device, wherein only a word line is connected to the boosting means, and only the selected word line is pumped by the pumping means.