JPH01307092A - Semiconductor memory and its driving method - Google Patents

Abstract

PURPOSE:To prevent the level fall of a word line and to attain a stable action by conducting a transfer gate connected to the word line, boosting it at >=a supply voltage, and holding a gate potential with a pumping circuit. CONSTITUTION:Out of clock signal input terminals CL1-CLn to select the word line, a signal to change from an L to an H is inputted, for example, to the CL1. A word line driving circuit 1 is operated, boosting is executed with the use of a capacitor C0 and inverters I1 and I2, and the potential sufficiently higher than the supply voltage is applied to a node N. On the other hand, a gate node N1 of a transfer gate QT1 is set at the lower potential than the supply voltage by a threshold VT of a MOS transistor, the voltage of the node N1 goes to sufficiently high by the capacity combination with a node N, a selective word line WL1 is set at the same potential as that of the node N, and set at the higher level than the supply voltage by >=VT. The selected memory cells MC11-MC1M are made writable through bit lines BL1-BLM, and the potential fall is prevented by a pumping circuit 5 connected to the node N1.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device that prevents potential drop in word lines and operates stably, and a method for driving the same.

A read operation of a dynamic random access memory (hereinafter abbreviated as DRAM), which is a conventional synchronous semiconductor memory device, is generally performed as follows. First, row decoding is performed, and then a word line is selected according to the row decoding. Information of the memory cell selected by this selected word line appears on the bit line. Next, by sense operation,
The potential change appearing on the bit line is amplified. Next, column decoding is performed to extract one specific piece of information from among the information of each memory cell appearing on the plurality of bit lines, and after amplification, the output is determined and the read operation is completed. Here, we will discuss the most important and difficult operation in a series of memory operations, which is reading information from memory cells to the bit line.
This will be explained with reference to the circuit diagram of a conventional DRAM shown in FIG. First, word lines WLI, WL2 .・・・・・・、
The word line drive circuit 1 is operated for WLN driving, and then the word line selector circuit 2 is operated to drive only the word line selected by row decoding. This selects one of the N clock signal input terminals from clock signal input terminals CL+ to CLN, for example, clock signal input terminal CL+, and inputs a clock signal that changes from low level to high level to this input terminal. . As a result, from node N1 to node NN, only node N has the power supply voltage (V
cc) to a potential lower by the threshold value (hereinafter referred to as vT) of the MOS transistor, and the other nodes remain at the ground potential. Next, the word line drive circuit 1 operates, and the node N changes from the ground potential to a potential higher than the normal power supply voltage and higher than the threshold voltage of the MOS transistor. As a result, the node N1 becomes a sufficiently high potential due to capacitive coupling between the gate of the transfer gate QT+ and the node N, and the selected word line W L + becomes the same potential as the node N. The other word lines remain at ground potential because the gate potential of the transfer gate is sufficiently low. Next, access transistor Q11 . connected to the selected word line WLI.
QI2. .......

QIM becomes conductive, and memory cells M C+ + , M
CI 2,...

MCIM information is transmitted to bit lines B Ll, B L2 . ...
...appears on BL Mei. Here, since DRAMs are highly integrated within a chip area of several square meters, the capacity of one memory cell is usually only a few tens of fF. In order to obtain stable operation with such a small capacitance, it is necessary to increase the amount of charge stored in the capacitor in the memory cell as much as possible. Normally, the maximum potential of the bit line is the power supply voltage and the minimum potential is the ground potential, so the maximum potential written into the memory cell is also the power supply voltage, and the minimum potential is the ground potential. However, in order to write a power supply potential to a memory cell, access transistors QllI, Q10. ...
..., the gate potential of the QNM needs to be higher than the power supply voltage by more than the threshold value Vt of the MOS transistor.

Therefore, the word line is controlled by a word line drive circuit 1 that boosts the voltage above the power supply voltage. In the case of dynamic type,
This boosting involves storing charge in the capacitor Co, raising the ground potential side of the capacitor Co from the ground potential to the power supply voltage using the delay of the inverter If and 2, and boosting the node N to a potential sufficiently higher than the power supply voltage. , a sufficiently high potential is supplied to the selected word line WL by capacitance distribution. but,
For example, transfer gate QTI, QT2 T・
..., the potential of the node N decreases with time due to junction leakage current in the source or drain region of QTH (.Therefore, the potential of the selected word line W L + also decreases with time. In page mode, which is one of the common uses of DRAM, read/write operations must be guaranteed even if a sufficient amount of time has passed after word line selection is completed.Therefore,
The potential drop of the selected word line WLI over time becomes a major cause of insufficient operating margin and unstable operation. As a countermeasure against this, in the conventional method, a pumping circuit (not shown) is provided at the node N to compensate for the drop in potential at the node N.

Problems to be Solved by the Invention The conventional method is effective in reducing the potential of the node N in order to supply a sufficiently high potential to the selected word line W L +. However, the potential of the node N1 at the gate of the transfer gate QT+ similarly decreases due to leakage current, so even if the potential decrease of the node N is prevented, the word line W
Since the gate potential of the transfer gate QTI decreases at I, t, charge cannot be replenished. Therefore, the potential of the selected word line wLI decreases over time due to leakage current.

For this reason, access transistor Q+QI2+...
..., when the gate potential of QIM decreases, the memory cell M
C11, MCI21...+MCI It becomes impossible to write to MCI up to the power supply voltage. This is DRAM
This was a major drawback that hindered the stability of memory operation.

Means for Solving the Problems A semiconductor memory device of the present invention includes a plurality of memory cells arranged in rows and columns in a matrix, a plurality of word lines for selecting rows of the same memory cells, and a plurality of word lines for selecting the same memory cells in columns. A plurality of bit lines, a word line drive circuit for boosting and driving the word line to a voltage higher than a power supply voltage, a plurality of transfer gates for connecting the word line and the word line drive circuit, and a gate of the transfer gate. This drive method includes a decoder transistor and a pumping circuit connected to each other, and this driving method involves inputting a pulse signal to the decoding transistor connected to the gate of the transfer gate connected to the word line to be selected. The gate is made conductive so that the selected word line is boosted to a voltage higher than the power supply voltage by a word line drive circuit, and the pulse signal causes a pumping circuit connected to the transfer gate to operate to maintain the gate potential of the transfer gate. be.

According to the present invention, the gate voltage of the transfer gate can be maintained at a high level for a long time, and a drop in the level of the word line can be prevented.

Embodiment An embodiment of a semiconductor memory device and a method for driving the same according to the present invention will be described with reference to the circuit diagram shown in FIG.

This semiconductor memory device has memory cells MCl11MCI2... arranged in rows and columns in a matrix.

MCNII and the word lines WLI, WL2, which are connected to the gates of the access transistors Q10, Q10, and QN that constitute the memory cell.
, WLN and the bit line BL1 . connected to one terminal of the memory cell. BL2. ......, BLm and
A word line drive circuit 1 consisting of a power supply 3, inverters I+ and 2, and a capacitor Co, and a transfer gate Qt+ connected between the word line drive circuit 1 and the word line.
QT2...+ QTN and decoding transistor QR connected to the gate of each transfer gate
I + QR2*..., connected to QRN and the gate of each transfer gate, and connected to the oscillation circuit 4. M.O.S.
Transistor Q1゜Q2. It consists of a pumping circuit 5 consisting of Q3 and a capacitor C1. In addition,
VCC is the power supply terminal, VCP is the cell plate power supply terminal, C
L+.

CL2...CLN is a clock signal input terminal, N
.

No, Nl, N2...NN are nodes.

Next, the exchange of information between memory cells, which is the most important part of a series of memory operations in a DRAM, will be explained. For word line selection, clock i input terminal CL, to CL
For example, a clock signal input terminal CL+ is selected from N, and a clock signal changing from a low level to a high level is input to this terminal. The other clock signal input terminals remain at low level. Next, the word line drive circuit 1 is operated, and the voltage is boosted using the capacitor Co and the inverters 1 and 12, so that a potential sufficiently higher than the power supply voltage is obtained at the node N. On the other hand, the gate node N1 of the transfer gate QT+ is
It is charged to a potential lower than the power supply voltage by the threshold value vT of the MOS transistor, and the node N1 becomes a sufficiently high potential due to capacitive coupling with the node N, and the selected word line W
L is at the same potential as node N, and MO is lower than the power supply voltage.
The level becomes higher than the threshold value 71 of the S transistor.

As a result, the selected memory cell MC is selected.

MC, 2, ......, MCIMi is bit line B
L.I.

BL2. ..., BL, it becomes possible to write up to the power supply voltage. By the way, due to leakage current at the junction of the MOS transistor, if left unchecked, the node N
The potentials of N1 and N1 decrease with time. However, a pumping circuit 5 is connected to the node NI, and a pumping circuit (not shown) is also connected to the node N, so that charges are replenished to the nodes N and N1 and a drop in potential is prevented. Ru.

Next, the operation of the pumping circuit 5 will be described.

Since node N+ rises to a potential sufficiently higher than the power supply voltage due to coupling with node N, MOS transistor Q1 becomes conductive, and node NO is charged to a potential lower than the power supply voltage by the threshold value vT of the MOS transistor, and the oscillation circuit 4 and capacitor C1, the node NO is boosted,
Charge is supplied from node NO to node Nl via MOS transistor Q3. Therefore, the gate of the transfer gate QTI maintains a sufficiently high potential, and the word line W L + and the node N are connected at low impedance, so that no potential drop occurs on the word line W L I.

The supply of charge by the pumping circuit 5 is always performed as long as the word line is selected, so the level of the word line is always kept sufficiently high, and the write potential to the memory cell does not drop.

Effects of the Invention According to the present invention, when a selected word line is kept at a high level for a long period of time and a read/write operation is performed, as in the page mode operation of a DRAM, it is possible to prevent the level of the word line from dropping, and to ensure that the memory cell has sufficient access to the selected word line. Potential can be written and stable operation can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor memory device of the present invention and its driving method, and FIG. 2 is a circuit diagram showing a conventional semiconductor memory device. 1... Word line drive circuit, 2... Word line selector circuit, 3... Power supply, 4...
・Oscillation circuit, 5... Pumping circuit, W L
+ , W L 21..., WLN...
Word line, Bt, 1. BL2. ......BLM・
...Bit line, Qt+ + QT2 r...
・・・＋QTN・・・・・・Transfer gate, Ql
ll Ql2.・・・・・・IQNM・・・Access transistor, QRII RR2, ・・・・・・,
RRN...Decoding transistor, Il,
12...Inverter, CLl, Cl3.
......+ CL H...Clock signal input terminal, N+ No, N,, N2...NN...
...Node, Ql, Q2. Qs-=・MOS transistor, COT C+・・・・capacitor, VC
C...Power supply terminal, VCP/old...Cell plate power supply terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person/---Food a Rinko-ku 2---Food at! Lecter riJ, Nz, Pigeon, N, Nz, =z7VI-Node 1st Figure Vcp ---v Full Sheet Ryugen jlh3/ -11 Hood Shoulder and Two Movement Rotation? ---Word Bead Selector 5J5 Figure 2

Claims (2)

[Claims] (1) A plurality of memory cells arranged in rows and columns in a matrix, a plurality of word lines for selecting rows of the memory cells, a plurality of bit lines for selecting columns of the memory cells, and the word lines. A word line drive circuit for boosting the voltage to a voltage higher than a power supply voltage, a plurality of transfer gates for connecting the word line and the word line drive circuit, a decoding transistor connected to the gate of the transfer gate, and a pumping circuit. A semiconductor storage device equipped with. (2) A pulse signal is input to the decoding transistor connected to the gate of the transfer gate connected to the word line to be selected, the transfer gate is made conductive, and the word line drive circuit drives the word line to be selected at a voltage higher than the power supply voltage. 1. A method for driving a semiconductor memory device, characterized in that the gate voltage of the transfer gate is maintained by boosting the voltage of the transfer gate, and operating a pumping circuit connected to the transfer gate using the pulse signal.