JPH07244987A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To stabilize the read-out operation in a low power source voltage by constituting a memory cell with MOS transistors Trs having voltages of specific threshold values and constituting a pull-up means with MOS transistors Trs having threshold values lower than above-mentioned voltages. CONSTITUTION:The level of a bit line BL1 is lowered even to a lower level as compared with a pull-up system because a leak compensation current supplied to the line BL1 from a power source voltage VCC via a Tr Q4 is sufficiently small as compared with a current quantity which is absorbed by an inverter 1 via the Tr Q2. As to a bit line BL0, the electric charges on the line BL0 do not flow-in into an inverter because the output terminal of the inverter 2 is an H and then a precharge level is maintained. The difference between voltage levels of lines BL0 and BL1 is emphasized by a sense amplifier circuit as a differential signal to be outputted as read-out data. Thus, this device has a wide operation margin and performs a stable read-out operation even when reductions in voltage levels of bit lines in the read-out operation are generated and even in an operation in the low power source voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which operates stably with a low power supply voltage.

[0002]

2. Description of the Related Art A circuit around a memory cell in a conventional semiconductor MOS memory has a structure shown in FIG. In the figure, reference numeral 11 denotes inverters 1 and 2 that constitute flip-flops 12 by being connected in parallel in opposite directions so that their inputs and outputs cross each other, and both ends of these flip-flops 12 and bit lines BL0, BL1 and NchMOS transistors Q1 and Q2 for controlling connection based on a memory cell selection signal from the word line WL.

The inverters 1 and 2 constitute a flip-flop 12 having two stable states, one output of which is high level "H" and the other output of which is low level "L". It stores 1-bit data depending on the state. In reality, such a memory cell 1
A large number of 1's are arranged on the word lines WL and the bit lines BL0, BL1 to form a memory cell array and store various data. The transistors Q1 and Q2
Has a certain threshold voltage, for example, a threshold voltage of about 0.6V, in order to suppress the leak current when the memory cell 11 is in the non-selected state (standby state) to a predetermined value or less. .

Q6 and Q7 are always bit lines BL0 and BL
1 is a load transistor for pulling up 1 to the power supply voltage V _CC side, and is particularly composed of an NchMOS transistor. This is because an Nch MOS transistor is used in consideration of the sensitivity of a current mirror type sense circuit (not shown) for further enhancing the voltage levels of both bit lines BL0 and BL1 during the data read operation from the memory cell 11. By the bit line BL during the read operation
The voltage levels of 0 and BL1 are set to a low level to some extent, whereby the sense circuit operates in the high sensitivity region.

In this case, the load transistors Q6 and Q7
The same transistors as the transistors Q1 and Q2 used in the memory cell 11 are used due to factors such as the manufacturing process, and the threshold voltages thereof are also the same as Q1 and Q2. As will be described later, the bit lines BL0, BL1
"H" signal of the power supply voltage V _CC and the load transistor Q
Since it is determined by the difference with the threshold voltage of Q6 and Q7, when PchMOS transistors are used as the load transistors Q6 and Q7, "H" becomes the power supply voltage V _CC and the voltage levels of the bit lines BL0 and BL1. Is too high to obtain stable operation of the sense circuit.

Next, the data write operation in the pull-up type semiconductor MOS memory will be described with reference to FIG. Normally, the word line WL is controlled to "L", the transistors Q1 and Q2 are non-conductive, and the memory cell 11 is non-selected. The control signal φ is controlled to “H”, and the load transistors Q6 and Q7 are
Becomes conductive, and the bit lines BL0 and BL1 are pulled up to the power supply voltage V _CC side via the load transistors Q6 and Q7, thereby suppressing generation of pseudo writing due to the voltage level reduction of the bit lines BL0 and BL1. ing.

Here, when writing data to a predetermined memory cell 11, first, the word line WL is set to "H".
The memory cell 11 is set to the selected state by controlling the above, and the transistors Q1 and Q2 are made conductive. After that, the load transistors Q6 and Q7 are made non-conductive by controlling the control signal φ to "L", and one of the load transistors Q6 and Q1 is connected to one end of the bit lines BL0 and BL1 by using a driver (not shown). The bit line of "1" is controlled to "L" and the other bit line is controlled to "H".

The voltages on the bit lines BL0 and BL1 are applied to both ends of the flip-flop 12 via the transistors Q1 and Q2, respectively, whereby the state of the flip-flop 12 is selectively set to either state. 1
Bit data will be stored. After that, by controlling the word line WL to "L", the transistor Q
1, Q2 are made non-conductive and the memory cell 11 is made non-selected, and the control signal φ is controlled to “H” to end the write operation. As a result, the load transistor Q
6 and Q7 become conductive, and bit line BL from power supply V _CC
The charges flow into the bit lines BL0 and B0
It is stored in the parasitic capacitance of L1. In this case, when the threshold voltage of the load transistors Q6 and Q7 is V _{TH NH} , the pull-up level for the bit lines BL0 and BL1 is V
_CC- V _THN-H .

Next, referring to FIG. 4, a data read operation in the pull-up type semiconductor MOS memory will be described. As the state of the flip-flop 12 before the read operation, the output terminal of the inverter 1 is “L”,
It is assumed that the output terminal of the inverter 2 is "H". First, the word line WL is controlled to "H" to bring the transistors Q1 and Q2 into a conductive state, whereby a current _flows from the power supply voltage V _CC to the output terminal of the inverter 1 via the load transistor Q7 and the transistor Q2 which are in a conductive state. Flowing in, a voltage drop occurs between the drain and source of the load transistor Q7, and the voltage level of the bit line BL1 drops.

As for the bit line BL0, since the output terminal of the inverter 2 is at "H", the current from the power supply voltage V _CC does not flow and the pull-up level, that is, V _CC.
-V _THN-H is maintained and these bit lines BL0, BL1
The difference in the voltage level at the bit line B is the differential signal.
It is emphasized by a sense circuit (not shown) provided at one end of L0 and BL1 and is output as read data.

[0011]

Therefore, in such a conventional semiconductor memory device, the load transistors Q6 and Q6 are provided.
7, the transistor Q of the memory cell 11 has a lower limit of the threshold voltage and a relatively high threshold voltage.
Since the same ones as 1 and Q2 are used, the pull-up level defined by the difference between the power supply voltage and the threshold voltage becomes a relatively low level, and some factor such as electrical noise causes during the read operation. , When the voltage level of the output side of the inverter 2 that outputs "H", that is, the voltage level of the bit line BL0 pulled up by the power supply voltage V _CC via the load transistor Q6 drops to some extent or more, writing to the memory cell 11 is performed. There is a problem in that the voltage level state equivalent to the operation is reached and the stored contents in the memory cell 11 may be destroyed.

[0012] Further, in a portable terminal or the like, operation with a low power supply voltage is required due to restrictions on the weight and volume of the battery,
When the power supply voltage is lowered, the pull-up level indicating “H” of the bit line during the read operation is inevitably lowered from the low power supply voltage by the threshold voltage of the MOS transistor, and therefore the semiconductor As a MOS memory, there is a problem that the operation margin is reduced. The present invention is for solving such a problem and has a wide operation margin, and is stable even when the voltage level of a bit line is lowered during a read operation or when an operation is performed at a low power supply voltage. It is an object of the present invention to provide a semiconductor memory device capable of realizing the read operation described above.

[0013]

To achieve the above object, in a semiconductor memory device according to the present invention, a memory cell is composed of a MOS transistor having a first threshold voltage, and a pull-up means is provided. , A MOS transistor having a second threshold voltage lower than the first threshold voltage. Further, the memory cell is composed of a MOS transistor having a first threshold voltage, and the precharge means is composed of a MOS transistor having a second threshold voltage lower than the first threshold voltage. There is something. In addition, the precharge means
A first MOS transistor having a second threshold voltage and operating based on a predetermined control signal, and a second MOS transistor having a second threshold voltage are provided to compensate for a leak current of a memory cell. The leak current compensating means is connected in parallel. Furthermore,
The leakage current compensating means is composed of a second MOS transistor whose gate is connected to the power supply voltage and a resistive element connected in series.

[0014]

Therefore, the bit line is pulled up by the pull-up means composed of the MOS transistor having the second threshold voltage lower than the first threshold voltage, and the pull-up level becomes high. Further, the bit line is precharged by the precharge means composed of the MOS transistor having the second threshold voltage lower than the first threshold voltage, and the precharge level becomes high. Further, the memory cell has a first MOS transistor having a second threshold voltage and operating based on a predetermined control signal, and a second MOS transistor having a second threshold voltage to prevent a leak current of the memory cell. The bit line is precharged by the precharge means composed of parallel connection of the leak current compensation means for compensation, and the precharge level and the voltage level of the bit line at the time of leak current compensation are increased. Furthermore, the leak current value of the leak current compensating means is determined from the threshold voltage of the second MOS transistor and the resistance value of the resistive element.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the periphery of a memory cell in a semiconductor memory device which is an embodiment of the present invention. In the figure, the same or equivalent parts as those described above are designated by the same reference numerals, and 3 and 4 are load elements connected between the power supply voltage V _CC and the bit lines BL0 and BL1, respectively.
FIG. 2 is a circuit diagram showing the configuration of the load element. Q3 is a predetermined threshold voltage lower than the NchMOS transistors Q1 and Q2 of the memory cell 11, for example, about 1/3 of the transistors Q1 and Q2 ( Load transistors composed of NchMOS transistors having a threshold voltage of about 0.2 V), T _A and T _B are power supply voltage V _CC and bit line B
These terminals are connected to L0 and BL1, respectively.

A data write operation in the pull-up type semiconductor MOS memory will be described as an operation of the present invention with reference to FIGS. Usually word line WL
Is controlled to a low level "L", and the transistors Q1 and Q2 are
Is in a non-conducting state, that is, the memory cell 11 is in a non-selected state, and the control signal φ supplied to the load elements 3 and 4 is controlled to a high level "H", so that the load in both load elements 3 and 4 is reduced. Transistor Q3 becomes conductive and bit line B
L0 and BL1 are pulled up to the side of the power supply voltage V _CC via the load transistor Q3, whereby bit lines BL0 and BL1
Generation of pseudo writing due to a decrease in the voltage level of BL1 is suppressed. In this case, the pull-up level is set to the threshold voltage of the load transistor Q3 by V _THN-L.
If (V _THN-L <V _THN-H ), the bit lines BL0, B
The pull-up level for L1 is V _CC -V _THN-L .

Here, when writing data to a predetermined memory cell 11, first, the word line WL is set to "H".
The memory cell 11 is set to the selected state by controlling the above, and the transistors Q1 and Q2 are made conductive. Then, by controlling the control signal φ to "L", the load transistor Q3 is made non-conductive and the bit line B
Driver (not shown) connected to one end of L0 and BL1
Is used to control one bit line to "L" and the other bit line to "H".

The voltages on the bit lines BL0 and BL1 are applied across the flip-flop 12 via the transistors Q1 and Q2, respectively, whereby the state of the flip-flop 12 is selectively set to either state. 1
Bit data will be stored. After that, by controlling the word line WL to "L", the transistor Q
1, Q2 are made non-conductive and the memory cell 11 is made non-selected, and the control signal φ is controlled to “H” to end the write operation. As a result, the load transistor Q
6 and Q7 become conductive, and bit line BL from power supply V _CC
The charges flow into 0 and BL1 and bit lines BL0 and B
It is stored in the parasitic capacitance of L1.

A data read operation in the pull-up type semiconductor MOS memory will be described below with reference to FIG. It is assumed that the output side of the inverter 1 is "L" and the output side of the inverter 2 is "H" as the state of the flip-flop 12 before the read operation.
First, the word line WL is controlled to "H" to bring the transistors Q1 and Q2 into a conductive state, which causes the power supply voltage V _CC.
Current flows into the output terminal of the inverter 1 through the load transistor Q3 and the transistor Q2 which are in a conductive state, a voltage drop occurs between the drain and source of the load transistor Q3, and the voltage level of the bit line BL1 decreases.

As for the bit line BL0, since the output terminal of the inverter 2 is at "H", the current from the power supply voltage V _CC does not flow and the pull-up level, that is, V
_CC- V _THN-L is maintained and these bit lines BL0, BL
The difference in voltage level at 1 is emphasized as a differential signal by a sense circuit (not shown) provided at one end of the bit lines BL0 and BL1 and is output as read data. Therefore, the voltage level of the bit line BL0, that is, the pull-up level, is the same as the conventional threshold voltage V _THN-H.
It is possible to set the voltage higher by V _THN-H- V _{THN-L as} compared with the case of using a transistor having a load transistor as a load transistor, and the voltage level of the "H" side bit line is lowered during the read operation. In some cases, even if the operation is performed at a low power supply voltage, the operation margin leading to malfunction can be widened by V _THN-H −V _{TH NL} compared to the conventional case.

Next, as another embodiment of the present invention, a precharge type semiconductor memory device will be described. The memory cell peripheral circuit has the same configuration as the pull-up method (see FIG. 1) described above. FIG. 3 is a circuit diagram showing the configuration of the load element. In FIG. 3, Q3 ′ is a precharge transistor formed of an NchMOS transistor having a predetermined threshold voltage lower than the transistors Q1 and Q2 of the memory cell 11. , Q4 is a transistor formed of an NchMOS transistor whose gate is connected to the power supply voltage V _CC and has a threshold voltage equal to that of the precharge transistor Q3 ', and R1 is a resistor formed of polysilicon or a diffusion layer. , Q5 are PchMOS transistors whose gates are connected to the ground voltage and have a high threshold voltage, and T _A and T _B are terminals connected to the power supply voltage V _CC and the bit lines BL0 and BL1, respectively.

Particularly in FIG. 3, (a) shows terminals T _A and T
_A precharge transistor Q3 'and a transistor Q4 are connected in parallel between _B , and (b) and (c) show that a resistor R1 and a transistor Q4 are connected in series between terminals T _A and T _B. , To which a precharge transistor Q3 'is connected in parallel, (d),
(E) is a PchMOS transistor Q between terminals T _A and T _B
5 and the transistor Q4 are connected in series,
On the other hand, the precharge transistor Q3 'is connected in parallel. The transistor Q4 and the resistive element connected in series with the transistor Q4, that is, the resistor R1 or the transistor Q5 constitute a means for compensating for the leak current of the bit lines BL0 and BL1 after precharging. In (e), in order to effectively obtain a high resistance value, a resistor R1 or a PchMOS transistor Q5 having a high threshold voltage is connected to the transistor Q4.

Next, referring to FIGS. 1 and 3A,
As an operation of another embodiment of the present invention, a data write operation in a precharge type semiconductor MOS memory will be described. Normally, both the word line WL and the control signal (precharge signal) φ'are controlled to "L", and the transistors Q1 and Q2 and the precharge transistor Q3 'in both load elements 3 and 4 are in the non-conductive state. . Here, when writing data to a predetermined memory cell 11, first, the control signal φ ′ is controlled to be “H” for a predetermined period to make the precharge transistor Q3 ′ conductive.

As a result, the precharge transistor Q3 'from the power supply voltage V _CC is applied to the bit lines BL0 and BL1.
An electric charge is supplied via the capacitor and accumulated in the parasitic capacitance of the bit lines BL0 and BL1. Here, assuming that the threshold voltage of the precharge transistor Q3 'is V _{TH NL} , the voltage level of the bit lines BL0 and BL1 after precharge is V _CC.
-V _THN-L . Thereafter, the control signal φ'is controlled to "L" to bring the precharge transistor Q3 'into a non-conducting state, and the precharge to the bit lines BL0 and BL1 is completed. When the memory cell 11 in the non-selected state has a leak current, the voltage level of the bit line gradually decreases from the precharge level, so that the conduction resistance value of the above-described leak current compensating means is compensated for. Have been decided.

Next, by controlling the word line WL to "H", the memory cell 11 is set to the selected state to make the transistors Q1 and Q2 conductive, and the bit lines BL0 and BL0.
Using the driver connected to one end of 1, one bit line is controlled to "L" and the other bit line is controlled to "H". The voltages on the bit lines BL0 and BL1 are applied to both ends of the flip-flop 12 via the transistors Q1 and Q2, respectively, whereby the state of the flip-flop 12 is selectively set to any one state, and 1 bit is set. Then, the write operation is completed by controlling the word line WL to "L" to bring the transistors Q1 and Q2 into the non-conductive state and the memory cell 11 into the non-selected state.

Next, referring to FIGS. 1 and 3A,
A data read operation in the precharge type (synchronous type) semiconductor MOS memory will be described. As the state of the flip-flop 12 before the read operation,
It is assumed that the output side of the inverter 1 is "L" and the output side of the inverter 2 is "H". Regarding the data read operation, similarly to the above-described data write operation, after precharging the bit lines BL0 and BL1 before the read operation, the word line WL is controlled to “H” to turn on the transistors Q1 and Q2. State. As a result, the charges accumulated in the bit line BL1 flow into the output terminal of the inverter 1 via the transistor Q2, and the transistor Q4
To the voltage level specified by the leakage compensation current supplied via the.

Here, from the power supply voltage V _CC to the transistor Q
Since the leakage compensation current supplied to the bit line BL1 via 4 is sufficiently smaller than the amount of current absorbed by the inverter 1 via the transistor Q2, the voltage level of the bit line BL1 is higher than that of the pull-up method described above. It drops to even lower levels. For the bit line BL0,
Since the output terminal of the inverter 2 is at "H", the charge on the bit line BL0 does not flow in and the precharge level, that is, V _CC -V _{THN -L} is maintained and these bit lines BL 0
The difference in voltage level between 0 and BL1 is emphasized as a differential signal by the sense circuit provided at one end of the bit lines BL0 and BL1 and is output as read data.

Therefore, the voltage level of the bit line BL0, that is, the precharge level is the threshold voltage V of the prior art.
Compared with the case where a transistor having _THN-H is used as a precharge transistor, it can be set higher by V _THN-H −V _THN-L , and “H” during read operation can be set.
Even if the voltage level of the side bit line drops, or even if the operation is performed at a low power supply voltage, the operation margin leading to malfunction can be widened by V _{TH NH} −V _THN-L compared to the conventional case. . In the above description of the data write / read operation in the precharge method, the description has been given with reference to FIG. 3A. However, as shown in FIGS. As a leakage current compensation means, a resistor R1 or PchM is connected in series with the transistor Q4.
The same applies to the case where the OS transistor Q5 is connected, and it is possible to obtain an effective high resistance as compared with the case where only the transistor Q4 is used, and it is possible to more appropriately set the minute leak current value. Become.

[0029]

As described above, according to the present invention, the memory cell is composed of the MOS transistor having the first threshold voltage, and the pull-up means is the second threshold voltage lower than the first threshold voltage. Since the MOS transistor having the threshold voltage is used, in the pull-up type semiconductor memory device, the pull-up level of the bit line has a relatively high threshold voltage M used for the memory cell as in the conventional case.
Compared with the case where an OS transistor is used as a load transistor, the difference can be set higher by the threshold voltage difference between both MOS transistors, and "H" during read operation can be set.
Even when the voltage level of the side bit line drops, or even when the operation is performed at a low power supply voltage, it is possible to widen the operation margin leading to a malfunction.

Further, the memory cell is composed of a MOS transistor having a first threshold voltage, and the precharge means is composed of a MOS transistor having a second threshold voltage lower than the first threshold voltage. Therefore, in the precharge type semiconductor memory device, the precharge level of the bit line is compared with the conventional case where a transistor having a relatively high threshold voltage used for a memory cell is used as a load transistor, It can be set higher by the difference between the threshold voltages of both MOS transistors, and malfunction occurs even if the voltage level of the “H” side bit line drops during the read operation, or even if the operation is at a low power supply voltage. It is possible to widen the operation margin up to the above.

Further, as a precharge means, a first transistor having a second threshold voltage and operating based on a predetermined control signal, and a second transistor having a second threshold voltage.
Since it is configured by connecting in parallel the leak current compensating means for compensating the leak current of the memory cell having the above MOS transistor, not only the precharge level but also the voltage level of the bit line at the time of leak current compensation can be set high. Therefore, it is possible to widen the operation margin leading to malfunctions as compared with the conventional case. Furthermore, as a leakage current compensation means, a second MO whose gate is connected to the power supply voltage is used.
Since the S transistor and the resistive element are connected in series, it is possible to obtain an effective high resistance as compared with the case where only the MOS transistor is used, and to set the minute leak current value more appropriately. It becomes possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram around a memory cell in a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a load element in FIG.

FIG. 3 is a circuit diagram showing a configuration of a load element according to another embodiment of the present invention.

FIG. 4 is a circuit diagram around a memory cell in a conventional semiconductor memory device.

[Explanation of symbols]

1, 2 ... Inverter, 11 ... Memory cell, 12 ... Flip-flop, Q1, Q2 ... NchMOS transistor,
Q3, Q3 ', Q4 ... NchMOS transistor (low threshold voltage), Q5 ... PchMOS transistor, BL0,
BL1 ... Bit line, WL ... Word line, φ, φ ′ ... Control signal, V _CC ... Power supply voltage.

Claims (4)

[Claims] 1. A semiconductor memory device comprising: a memory cell connected to a word line and a bit line; a plurality of memory cells arranged vertically and horizontally; and a pull-up means for pulling up the bit line to a power supply voltage side. Is a MOS having a first threshold voltage
A semiconductor memory device comprising a transistor, wherein the pull-up means is a MOS transistor having a second threshold voltage lower than the first threshold voltage. 2. A semiconductor memory device comprising: memory cells connected to a word line and a bit line and arranged in a plurality of rows and columns; and a precharge means for precharging the bit line, wherein the memory cell is a first memory cell. MOS with threshold voltage
A semiconductor memory device comprising a transistor, wherein the precharge means is a MOS transistor having a second threshold voltage lower than the first threshold voltage. 3. The semiconductor memory device according to claim 2, wherein the precharge means has a first MOS transistor having the second threshold voltage and operating based on a predetermined control signal, and the second MOS transistor. Second MO having a threshold voltage of
A semiconductor memory device comprising an S-transistor and a leak current compensating means for compensating for a leak current of the memory cell, which are connected in parallel. 4. The semiconductor memory device according to claim 3, wherein the leakage current compensating means is configured by serially connecting the second MOS transistor whose gate is connected to a power supply voltage and a resistive element. A semiconductor memory device characterized in that.