JPH09274793A - Dynamic random access memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a test operation time required for a refresh time test. SOLUTION: When a refresh test mode signal T is a K state, the device is in a normal operation mode. When it is a H state, the device is in a refresh test mode. In the normal operation mode, a charge pump is operated using capacitors C2 and C3 in parallel, and boosting voltage VB for driving a word line is effectively boosted. On the other hand, in the refresh test mode, a charge pump is operated using only the capacitor C2, and boosting voltage VB for driving a word line is kept lower than the normal operation mode. When boosting voltage VB for driving a word line is kept lower, as a refresh margin time is shortened, a test operation time required for a refresh time test is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention selects a memory cell, which stores bit data by accumulated charges and uses memory capacitors arranged in a matrix, by a word line driven by a word line driver and a column selector. The present invention relates to a dynamic random access memory that is selected by a selected bit line, and performs write access and read access through the bit line, and in particular, according to the passage of time of accumulated charge for storing bit data in a memory cell. As a result of the attenuation, it is ensured that the stored bit data is not lost after the refresh margin time defined by the refresh time specification rule has passed after writing the bit data into the memory cell, thereby satisfying the refresh time specification rule. To ensure that it is a good product By shortening the test work time required for fresh time test, efficiency improvement of the refresh time test, a dynamic random access memory capable of reducing the test cost reduction.

[0002]

2. Description of the Related Art Conventionally used RAM (random
access memory is a dynamic random access memory (DRA).
Called M). In this DRAM, the charge accumulated in the memory capacitor of each memory cell causes
Store bit data. In a DRAM, bit data is stored depending on the presence / absence of charge accumulated in a memory capacitor and the amount of charge. In a DRAM, such memory cells arranged in a matrix are selected by a word line driven by a row decoder and a bit line selected by a column selector, and write access and read are performed via the bit line. Access and further refresh operations are performed.

In the DRAM, the accumulated charge corresponding to the bit data to be stored is a MOS (metal oxide semiconductor).
) It decreases over time due to transistor leakage current and recombination on the semiconductor substrate surface. For this reason, D
The RAM is characterized in that the refresh operation is performed on each memory cell at a constant cycle.

FIG. 1 is a block diagram showing a structure of a general DRAM which has been conventionally used.

In the conventional example shown in FIG. 1, memory cells MC are arranged in a matrix to form a memory matrix. For such a memory matrix, the word lines WL0 and WL1 driven by the word line driver WD using the word line driving boost voltage VB from the word line driving boost circuit BT and the column selector CSEL are selected. Bit lines BL0 to BL3, (B
A desired memory cell MC is selected by L0 bar) to (BL3 bar), and the selected bit line BL0 to BL
3, write access, read access, or refresh operation access is performed via (BL0 bar) to (BL3 bar). The column selector CSEL includes an N-channel MOS transistor TNA for each pair of bit lines BL0 to BL3 and (BL0 bar) to (BL3 bar).
And TNB. These N channel MOS transistors TNA and TNB are connected to the signal Y output by the column decoder.
It operates according to 0 to Y3.

Here, at the time of write access, input data is input to the column selector CSEL via DI and (DI bar), buffer gates B1 and B2, data lines DL and (DL bar), and the column selector CSEL. Is transmitted to the pair of bit lines BL0 to BL3, (BL0 bar) to (BL3 bar) selected by and is written in the desired memory cell MC to be selected.

On the other hand, at the time of read access, the bit data stored in the desired memory cell MC to be read is the bit lines BL0 to BL3, (BL0 bar) to (BL3) selected by the column selector CSEL. Input to the column selector CSEL via the data line DL and (DL bar) and the buffer gates B3 and B4 to the outside of the DRAM, and the bit data is read as the output data DO and (DO bar). . During such read access, the bit lines BL0 to BL3, (B
The bit data stored in the selected memory cell MC in the L0 bar) to (BL3 bar) is the sense signal SAP output from the sense amplifier timing circuit (not shown).
And a sense amplifier S controlled by (SAN bar)
Amplified by A.

FIG. 2 is a circuit diagram of a word line drive booster circuit BT used in this conventional example. FIG. 3 is a circuit diagram of the word line driver WD also used in this conventional example.

First, as shown in FIG. 2, the word line drive booster circuit BT has an N channel MOS transistor TN1.
And TN2 and a capacitor C1. As shown in FIG. 3, the word line driver WD includes a decoder G1, an inverter I1, an N channel M
It is composed of OS transistors TN3 to TN5. Here, although the decoder G1 is shown in the symbol diagram symbol of the AND logic gate in FIG.
Is not limited to a general AND logical operation, and the DRA
A predetermined logical operation for decoding M is performed.

FIG. 4 shows the word line drive booster circuit BT.
7 is a time chart showing the operation of the word line driver WD.

Here, using the time chart of FIG.
The operation of the word line drive booster circuit BT and the word line driver WD will be described.

First, when accessing the memory cell MC of the DRAM, the address signal AD is input. When the address signal AD selects the DRAM, the decoder G
The signal B output by 1 rises at time t1. here,
When the signal B rises at the time t1, the time t
At 2, the signal C on the output side of the N-channel MOS transistor TN3 also starts to rise.

At time t3, the signal φ starts rising. Then, at time t4, the boosted voltage VB for driving the word line starts to rise and the word line WL also starts to rise with the rise of the signal φ. When the word line WL rises in this way, the signal C is raised by the parasitic capacitor Ca shown in FIG. 3, so that the signal C rises further after the time t5 as shown in the time chart of FIG. It rises above VDD.

Then, at time t6, the signal A starts to rise. Then, as the signal A rises, the time t
In 7, the rising of the boosted voltage VB for driving the word line is further boosted, and the rising of the word line WL is further boosted with the boosting of the boosted voltage VB for driving the word line. The boosted voltage VB for driving the word line and the word line WL are boosted in this way after the time t7, and thus become equal to or higher than the power supply voltage VDD. Further, when the word line WL rises and is boosted to increase the voltage in this manner, the memory cell MC corresponding to the word line WL of the DRAM is selected and accessible.

When the period during which the memory cell MC can be accessed ends, the address signal AD is changed and the time t1 is reached.
At 0, the signal B starts to fall. When the signal B falls, the signal C also begins to fall at time t11, and the word line WL also begins to fall. Word line WL at time t12
Is the voltage VSS, and the selection of the memory cell MC is completely completed.

After this, at time t13, the signal (φ bar) starts to rise. When the signal (φ bar) rises in this manner, the boosted voltage VB for driving the word line starts to fall at time t14.

As described above with reference to the time chart of FIG. 4, the word line driver WD of FIG. 3 selects the word line WL corresponding to the input address signal AD and the memory corresponding to the word line WL. The cell MC can be selected. At this time, the voltage of the selected word line WL is boosted to the power supply voltage VDD or higher by the word line drive booster circuit BT shown in FIG. When the voltage of the word line WL is increased in this way, it becomes possible to more reliably store the charge corresponding to the bit data in the memory cell MC in the write access, and in the read access. The voltage corresponding to the electric charge stored in the memory cell MC can be read more reliably.

Here, the memory cell MC shown in FIG.
Is the access transistor TG, as shown in FIG.
And a memory capacitor CM. V
p is a plate potential (voltage).

In the DRAM, bit data is stored by the accumulated charge of a memory capacitor such as CM shown in FIG. 5 which a memory cell has.
This accumulated charge decreases over time due to leakage current of the MOS transistor and recombination on the surface of the semiconductor substrate. Further, if the accumulated charge of the memory capacitor is reduced too much, the written bit data will be lost.

Although the accumulated charge is gradually reduced with the passage of time, a time (hereinafter referred to as a refresh margin time) in which the bit data written in the memory cell is guaranteed to be retained is a refresh time in a general DRAM. It is specified as a specification and guarantees that bit data can be held. Therefore, when using a DRAM for which such a refresh time specification is defined,
If the refresh operation is performed on each memory cell within the refresh margin time, the bit data written in the memory cell will not be lost due to the decay of the accumulated charge over time.

FIG. 6 is a time chart showing a write access operation in the conventional DRAM.

In FIG. 6, the voltage timing of each signal indicated by the symbol (XXX) is indicated as indicated by "V (XXX)". In this conventional example, in FIG. 6, the time chart of the word line WL0 is shown by the solid line WLA, and the time chart of the memory capacitor voltage DT is shown by the solid line DA. The word line W in FIG.
One-dot chain line WLB of L0 and memory capacitor voltage DT
The dashed-dotted line DB is a time chart of an embodiment of the present invention described later.

As shown in FIG. 6, D of the conventional example is
At the time of write access in the RAM, first, at time t31
At, the word line WL0 rises. Then, time t
At 32, the input data DI is input. In addition, the word line WL0 that rises to the power supply voltage VDD at time t31 is
The voltage is further increased at time t33. This is because the word line driver WD uses the boosted voltage VB for driving the word line supplied from the word line driving booster circuit BT described above with reference to FIG.

Then, when the sense signal (SAN bar) falls at time t34, the fall of the bit line BL is amplified by the sense amplifier SA. Further, at time t35, the sense signal SAP rises, so that the sense amplifier SA
Thus, the rising edge of the bit line BL1 is amplified.

Here, in the sense amplifier SA of the conventional example, when the sense signal (SAN bar) falls, the fall of the bit line BL is amplified or the bit line (B
The falling edge of (L bar) is amplified. That is, when the sense signal (SAN bar) falls, the bit line BL or bit line (BL bar) that is falling is amplified. On the other hand, when the sense signal SAP rises, the sense amplifier SA amplifies the rising bit line BL,
Alternatively, the rising bit line (BL bar) is amplified.

When the write signal WE rises at time t36, the input data DI is passed through the buffer gate B1 in FIG.
Is output to the data line DL. In addition, the input data (DI bar) passes through the buffer gate B2 and the data line (DL bar).
Output to

Then, the decode signal Y0 output according to the input address signal rises at time t37. Then, the signal of the data line DL is output to the bit line BL, and the signal of the data line (DL bar) is output to the bit line (B
L bar). Along with this, at time t38 in FIG. 6, the logical states of the bit line BL and the bit line (BL bar) change. Immediately after the time t38, the word line WL0 and the bit line BL0 or the bit line (B
In the memory cell MC selected by L0 bar), as shown in FIG.
The memory capacitor voltage DT shown in FIG. 3 rises, the accumulated charge is stored in the memory capacitor CM of the memory cell MC, and the bit data is written.

Note that at time t39, the word line WL0
Completely falls. Then, the access transistor TG shown in FIG. 5 of the memory cell MC which has been selected until now is turned off. After the time t39, the magnitude of the memory capacitor voltage DT depends on the amount of accumulated charge stored in the memory capacitor CM.
Further, the accumulated charges decrease with time due to the leakage current of the access transistor TG and recombination on the surface of the semiconductor substrate. Therefore, also in the time chart of FIG. 6, the memory capacitor voltage DT gradually decreases after time t39.

Here, in the manufactured DRAM, the leakage current of the MOS transistor becomes large for some reason or the degree of recombination on the surface of the semiconductor substrate becomes strong. If the degree of attenuation of the accumulated charge according to the bit data stored in 1 is increased over time, a product defect that does not meet the above-described refresh time specification may occur.

In such a defective product, the bit data written in the memory cell is lost even though the refresh operation is performed according to the refresh margin time defined by the DRAM refresh time specification. There is. Therefore, such defective products are identified and removed during the DRAM manufacturing process.

A product test (hereinafter referred to as a refresh time test) for discriminating a good product or a defective product depending on whether the manufactured DRAM meets the refresh time specification is generally performed on all memory cells. After the bit data is written to or the refresh operation is performed, the bit data written in each memory cell is read immediately after the refresh margin time defined by the refresh time specification. . Further, in such a refresh time test, in order to more surely remove defective products, a series of bit data write (or refresh operation) and bit data read operations on such memory cells are performed on all memory cells. It is common to repeat what is done to the person.

[0032]

The test work time required for such a refresh time test is the refresh margin time and all memory cells when a one-cycle test is performed for all memory cells. This is the sum of the time required to access. Here, if such a test is performed for N cycles, such a test time will be N times as long.

As described above, the refresh time test requires a predetermined time, and the test cost is accordingly generated. As such test time and cost are reduced, DR
This is more preferable in terms of reduction of man-hours for manufacturing AM and cost reduction.

The present invention has been made to solve the above-mentioned conventional problems, and bit data is written to a memory cell by attenuating the accumulated charge for storing the bit data in the memory cell over time. In order to guarantee that the stored bit data is not lost after the refresh margin time defined by the refresh time specification rule is satisfied, it is possible to guarantee that the refresh time specification rule is a good product. By shortening the test work time required for the refresh time test to be performed,
It is an object of the present invention to provide a DRAM capable of improving the efficiency of the refresh time test and reducing the test cost.

[0035]

In a DRAM of the present invention, memory cells using memory capacitors arranged in a matrix for storing bit data by accumulated charges, word lines driven by a word line driver, and Refresh to test whether the dynamic random access memory is selected by the bit line selected by the column selector, and the write access and the read access are performed via the bit line in the normal operation mode or whether the refresh time specification is satisfied. A mode selection circuit that sets any one of the time test modes and obtains a refresh test mode signal indicating the setting, and a power source for a boosted voltage for driving a word line used as a power source for driving a word line by the word line driver. Has a function that is generated from voltage Along with the magnitude of the boosted voltage for driving the word line in the normal mode, a word line drive booster circuit having a function of suppressing the magnitude of the boosted voltage for driving the word line in the refresh time test mode. By providing the above, the above-mentioned problems are solved.

The operation of the present invention will be briefly described below.

In recent DRAMs, it is common to use a voltage higher than the power supply voltage as a power supply when the word line is driven by a word line driver according to an input address signal. As a result, the selected word line can be driven to a higher voltage, and write access, read access, or refresh operation for the target memory cell can be performed more reliably and quickly. Particularly in the case of write access, by driving the word line to a higher voltage in this way, more accumulated charge can be stored in the memory capacitor of the memory cell, and along with this, the refresh time specified in the refresh time specification The extra time can be extended.

Here, the voltage of the power supply used for driving the word line by the word line driver will be referred to as a word line driving boost voltage hereinafter. Then, in the present invention, a mode called a refresh time test mode, which is particularly suitable for performing a refresh time test, is newly added in addition to the normal operation mode for performing the write access, the read access, and the refresh operation as usual. I am trying to provide it. In the present invention, the magnitude of the word line driving boosted voltage in the refresh time test mode described above is suppressed to be lower than the magnitude of the word line driving boosted voltage in the normal operation mode.

Then, in the write access and refresh operation in this refresh time test mode,
Since the voltage of the word line driven by the word line driver becomes low, the accumulated charge stored in the memory capacitor of the memory cell becomes small, and therefore the refresh margin time also becomes short.

In the present invention, the refresh margin time defined by the refresh time specification regulation in the normal operation mode and the refresh margin time in the refresh time test mode in which the magnitude of the voltage of the boosted voltage for driving the word line is suppressed to be small. Is assumed to have a certain relationship with. Under such a premise, in the refresh time test mode in which the refresh margin time is shortened as compared with the normal operation mode as described above, after writing data to all the memory cells,
Alternatively, a refresh time test is performed by performing a read access after the refresh margin time has elapsed after performing the refresh operation. Since the refresh time in the refresh time test mode is shorter than that in the normal operation mode, the refresh time test performed in the refresh time test mode can shorten the test time and reduce the test cost. Can be planned.

As described above, according to the present invention, since the accumulated charge for storing the bit data in the memory cell is attenuated with the passage of time, the bit data is written into the memory cell and then the refresh time specified by the refresh time specification is specified. Test work time required for the refresh time test to ensure that the bit data to be stored is not lost after the lapse of the allowance time to ensure that it is a non-defective product that meets the refresh time specification. By shortening, the excellent effect that the efficiency of the refresh time test can be improved and the test cost can be reduced can be obtained.

[0042]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 7 is a circuit diagram of the word line drive booster circuit BT used in the embodiment of the DRAM to which the present invention is applied.

The DRAM of this embodiment is basically the same as the DRAM of FIG. 1 described above. This embodiment is different from the conventional example of FIG. 1 in which only the word line drive boosting circuit BT shown in FIG. 7 is described above. A word line drive booster circuit BT as shown is used.

In FIG. 7, the word line drive booster circuit BT of this embodiment has inverters I2 to I4 and a NOR circuit.
It is composed of a logic gate G2, capacitors C2 and C3, and N-channel MOS transistors TN6 and TN7. Of these, the N-channel MOS transistors TN6 and TN7 correspond to the N-channel MOS transistors TN1 and TN2 of the conventional word line drive booster circuit BT shown in FIG.

Here, as compared with the conventional word line drive booster circuit BT of FIG. 2, this embodiment of FIG.
A refresh test mode signal TM is newly added. The refresh test mode signal TM is a signal to which the present invention is applied, which sets either the normal operation mode or the refresh time test mode. The refresh test mode signal TM of this embodiment
In the L state, the normal operation mode is shown, and in the H state, the refresh time test mode is shown.

The refresh test mode signal TM is input from the outside of the DRAM in this embodiment. The means for obtaining such a refresh test mode signal TM in the DRAM is called a mode selection circuit in the present invention, but in the present embodiment, the mode selection circuit is a terminal for inputting the refresh test mode signal TM or Wiring. However, the present invention does not specifically limit this mode selection circuit. For example, such a refresh test mode signal TM is DR.
It may be generated inside the AM.

In this embodiment, first, in the normal operation mode, the refresh test mode signal TM is in the L state. Then, the NOR logic gate G2 operates as if it were an inverter with respect to the output of the inverter I4. At this time, with respect to the signal A, the output of the inverter I3 and NO
The outputs of the R logic gate G2 are in the H state at the same time or in the L state at the same time.
As if it were connected in parallel to the signal A. Therefore, in the word line drive booster circuit BT of the present embodiment, in the normal operation mode, in the operation as the charge pump, the capacitors C2 and C3 are used as being connected in parallel.

On the other hand, in the refresh time test mode of this embodiment, the refresh test mode signal TM is in the H state. Then, regardless of the signal A, the output of the NOR logic gate G2 is always in the L state. Therefore, only the capacitor C2 is used in the refresh time test mode for the operation of the word line drive booster circuit BT as a charge pump.

As described above, in the operation as the charge pump of the word line drive booster circuit BT of this embodiment, the capacitors C2 and C3 are used as being connected in parallel in the normal operation mode, while the capacitors are used in the refresh time test mode. Only C2 is used. Therefore, in the normal operation mode of the word line drive booster circuit BT, more charges can be supplied by using the capacitors C2 and C3 in parallel, and the word line drive boosted voltage V can be efficiently supplied.
B can be raised. On the other hand, in the refresh time test mode, since only the capacitor C2 is used, the charge that can be supplied as the charge pump is smaller than that in the normal operation mode. Therefore, compared with the normal operation mode, the word line drive boosted voltage VB Voltage tends to be kept lower.

The operation of the word line drive booster circuit BT shown in FIG. 7 and the word line driver WD shown in FIG. 3 is as shown in the time chart of FIG.

In FIG. 4, the time chart of the boosted voltage VB for driving the word line is shown by the alternate long and short dash line VBB in the present embodiment in contrast to the solid line VBA of the conventional example. As shown by the alternate long and short dash line VBB, according to the present embodiment, the boosted voltage VB for driving the word line can be suppressed lower than in the conventional example.

Next, consider the word line WL in FIG. Word line WL time chart is solid line WL
A shows a conventional example, and a one-dot chain line WLB shows the present embodiment. Here, this one-dot chain line WL
As shown in B, the voltage of the word line WL of the present embodiment is suppressed lower than that of the conventional example.

Regarding the signal C, a conventional example is shown by a solid line CA, and this embodiment is shown by a one-dot chain line CB. As is clear from the one-dot chain line CB, the signal C
Regarding this, in the present embodiment, it is suppressed to be lower than the conventional example.

As described above, in this embodiment, by using the word line drive booster circuit BT shown in FIG. 7, a DRAM to which the present invention is applied can be provided. Therefore,
According to the present embodiment, since the accumulated charge for storing bit data in the memory cell decays over time, after writing the bit data to the memory cell, after the refresh margin time defined by the refresh time specification regulation has elapsed. By shortening the test work time required for the refresh time test performed to guarantee that the stored bit data is not lost and that it is a non-defective product that satisfies the refresh time specification. Further, it is possible to obtain an excellent effect that it is possible to provide a DRAM capable of improving the efficiency of the refresh time test and reducing the test cost.

[0056]

As described above, according to the present invention, the refresh time specification is defined after the bit data is written to the memory cell due to the decay of the accumulated charge for storing the bit data in the memory cell over time. The refresh time test performed to guarantee that the bit data to be stored is not lost after the refresh allowance time defined in 1. By shortening the required test work time, it is possible to obtain an excellent effect that it is possible to provide a DRAM capable of improving the efficiency of the refresh time test and reducing the test cost.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a conventional DRAM.

FIG. 2 is a circuit diagram of a word line drive booster circuit used in the conventional example.

FIG. 3 is a circuit diagram of a word line driver used in the conventional example.

FIG. 4 is a time chart showing operations of the word line drive booster circuit and the word line driver.

FIG. 5 is a circuit diagram of a memory cell used in the conventional example.

FIG. 6 is a time chart showing the operation of the conventional example.

FIG. 7 is a circuit diagram of a word line drive booster circuit used in an embodiment of a DRAM to which the present invention is applied.

[Explanation of symbols]

MC ... Memory cell SA ... Sense amplifier TG ... Access transistor CM ... Memory capacitor BT ... Word line drive booster circuit WD ... Word line driver CSEL ... Column selector C1-C4 ... Capacitor G1 ... Decoder G2 ... NOR logic gate I1-I4 ... Inverter WL, WL0, WL1, WLi ... Word lines BL0 to BL3, (BL0 bar) to (BL3 bar) ... Bit lines DL, (DL bar) ... Data lines DI, (DI bar) ... Input data DO, (DO bar) Output data Vp Plate potential VB Word line driving boost voltage AD Address signals A to C, φ, (φ bar) Signal VDD power supply voltage VSS Ground SAP, (SAN bar) Sense signals Y0 to Y3 Decode signal DT Memory capacitor voltage TM Refresh test mode Issue t1~t7, t10~t14, t31~t39 ... time TN1~TN7, TNA, TNB ... N-channel MOS transistor B1~B4 ... buffer gate

Claims (1)

[Claims] 1. A memory cell using memory capacitors arranged in a matrix for storing bit data by accumulated charges is selected by a word line driven by a word line driver and a bit line selected by a column selector. Then, in the dynamic random access memory that is configured to perform the write access and the read access through the bit line, set either the normal operation mode or the refresh time test mode for testing whether the refresh time specification is satisfied. A mode selection circuit for obtaining a refresh test mode signal indicating the setting, and a function for generating a boosted voltage for driving a word line used as a power source for driving the word line by the word line driver from the power source voltage, and The above in the normal mode A word line drive booster circuit having a function of suppressing the magnitude of the word line drive boosted voltage in the refresh time test mode as compared with the magnitude of the word line drive boosted voltage is provided. Dynamic random access memory.