JPH08249885A - Dynamic semiconductor storage - Google Patents

Abstract

PURPOSE: To reduce power required for charging and discharging and to enable random access by inserting large capacitors of intermediate potentials between each of power sources VCC and VSS and a precharge potential and charging and discharging bit lines through these capacitors. CONSTITUTION: Large capacitors C2 , C1 are connected to sense amplifier driver lines/SAN. SAN through switching elements SEN,/SEN to be held at an intermediate potential Vm2 between VSS and 1/2VCC and at an intermediate potential Vm1 between VCC and 1/2VCC respectively. If, this time, Vm1 is set at 3/4VCC and Vm2 at 1/4VCC, power consumption for bit line charging and discharging in all cases of bit line sensing, memory cell writing, bit line equalizing and bit line precharge becomes 1/32CBtotal.VCC<2> . Consequently the energy consumption at one cycle becomes 1/4CBtotal.VCC<2> . Like this, power consumption is reduced and array can be arbitrarily selected, enabling random access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic semiconductor memory device (DRAM), and more particularly to a DRAM for reducing charge / discharge current of bit lines.

[0002]

2. Description of the Related Art In a DRAM, the charge accumulated in a memory cell capacitor leaks over time and is destroyed when read, so that rewriting of data is necessary. It is necessary to fully swing the bit line pair and return the data to the memory.

A conventional example of this operation is shown in FIGS. FIG. 11 is a circuit configuration diagram showing a general-purpose DRAM circuit,
FIG. 12 is an operation timing chart thereof. After the word line WL is selected, the data read to the bit line BL is amplified by the sense circuit S / A. In this example, the bit lines / BL0, B
L0 is restored to Vcc and Vss.

The energy consumed at this time is assumed to be one bit line capacitance C _B when the bit lines / BL0, BL0 are charged or discharged from (1/2) Vcc to Vcc, Vss, respectively. _{1/2) C B {Vcc- (1/2} ) Vcc} 2 = (1/8) C B Vcc 2 (1/2) C B {(1/2) Vcc-Vss} 2 = (1/8 ) It becomes C _B Vcc ² . This energy is constant regardless of speed,
It depends on the potential change and capacitance of the capacitor.

Also, when / EQL becomes High level and the bit line pair BL0, / BL0 is shorted to (1/2) Vcc, the bit line pair / BL0, BL0 is Vcc, Vss.
Energy consumption changes from (1/2) Vcc to (1/2) Vcc, (1/2) C _B {Vcc- (1/2) Vcc} ² = (1/8) C _B Vcc
_{^{2, (1/2) C B {}} (1/2) Vcc-Vss} 2 = (1/8) C B Vcc 2 , and the one column in one cycle, one bit line pair / BL _o, BL _o requiring energy consumption per (1/2) C _B Vcc ^2.

Normally, a DRAM selects a word line with a row address and a column bit line pair with a column address, so that bit line pairs corresponding to column addresses are charged and discharged at one time. Therefore, the number of columns per cycle × (1/2)
It consumes the energy of C _B Vcc ² and occupies most of the power consumption of the chip. Further, as the generation advances, the capacity will be quadrupled and the number of columns will be doubled, and the power required for charging / discharging the bit lines will be further increased.

Therefore, recently, a method for solving the above-mentioned problem only at the time of refreshing has been proposed (Japanese Patent Laid-Open No. Hei 5 (1999) -53977).
-135580). This conventional example is shown in FIGS. FIG. 13 is a circuit configuration diagram showing a DRAM circuit,
FIG. 14 is an operation timing chart thereof.

The bit lines D11 and / D11 of the array A are Vcc,
After recovering to Vss, the sense drive lines P of the two cell arrays
By shorting the switch SP between P1 and PP2 and the switch SN between PN1 and PN2, the charge of the bit line of array A is passed to the array B, and by using this, the bit lines / D21 and D21 of array B are connected. From (1/2) Vcc to (1/4) Vc
c, sense to (3/4) Vcc. Then, the switch is turned off to restore / D21 and D21 to Vcc and Vss.
Similarly, the bit lines D11, / D11 of the array A are equalized to (1/2) Vcc after Vcc, Vss are changed to (3/4) Vcc, (1/4) Vcc by a short circuit.

That is, due to a short circuit between Vcc and (1/2) Vcc
(3/4) Vcc, due to a short between Vss and (1/2) Vcc
It becomes (1/4) Vcc, and energy consumption per column is (1/2) C of the conventional one by recycling the charge.
_B half (1/4) of Vcc ² is reduced to C _B Vcc ^2.

However, this type of system has the following problems. First, after selecting the array A, it is necessary to raise the word line of the next other array B for sensing. That is, the equalization of the array A must be performed at the same time as the sensing operation of the array B, and it is not effective if they are not always operated in sequence. Second, the same array A cannot be selected by equalizing after selecting the array A. In other words, you can't select another word line in the same array,
Random access is not possible.

Further, it can be applied only where there is a switch between the arrays, and there is a problem that the degree of freedom in array selection is reduced. Although the power is reduced, it can be applied only to a refresh method such as a special self-refresh, and it is externally applied. There was a problem that normal random access to put an address was not possible.

[0012]

As described above, the conventional DR
In AM, there is a problem that the power required for charging and discharging the bit line is large. To solve this, Japanese Patent Laid-Open No. Hei 5
If the method as disclosed in Japanese Patent Laid-Open No. 135580 is adopted, the power required for charging / discharging the bit lines can be reduced to half, while the DRAM is used.
However, there was a problem that the important random access function was impaired.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to provide a DR capable of random access while reducing the power required for charging and discharging the bit line.
To provide AM.

[0014]

In order to solve the above problems, the present invention employs the following configurations. That is, according to the present invention, a plurality of memory cells arranged at a ratio of one to at least two intersections of a plurality of bit lines and a plurality of word lines, and a plurality of nMOS senses connected to each pair of bit lines. Amplifier circuit and pMOS sense amplifier circuit, and nMO
A first drive line for driving the S sense amplifier circuit and pMO
In a dynamic semiconductor memory device including a memory cell array including a second drive line that drives an S sense amplifier circuit, the first drive line is connected to a first power supply via a first switch element, The second drive line is connected to the second power supply having a higher potential than the first power supply via the second switch element, and the second drive line is connected to the third power supply via the third switch element.
And a fourth power source having a lower potential than that of the third power source through the fourth switch element.

According to the present invention (claim 2), a plurality of memory cells arranged at a ratio of at least two intersections of a plurality of bit lines and a plurality of word lines, and each pair of bit lines. NMOS sense amplifier circuits and p connected to
A dynamic semiconductor memory device including a memory cell array including a MOS sense amplifier circuit, a first drive line for driving an nMOS sense amplifier circuit, and a second drive line for driving a pMOS sense amplifier circuit is provided. The drive line is connected to the first power source via the first switch element or directly, the second drive line is connected to the third power source via the third switch element, and the fourth switch element. And a fourth power source having a lower potential than the third power source.

According to the present invention (claim 3), a plurality of memory cells arranged at a ratio of at least two intersections of a plurality of bit lines and a plurality of word lines, and each pair of bit lines. NMOS sense amplifier circuits and p connected to
A dynamic semiconductor memory device including a memory cell array including a MOS sense amplifier circuit, a first drive line for driving an nMOS sense amplifier circuit, and a second drive line for driving a pMOS sense amplifier circuit is provided. The drive line is connected to the first power supply via the first switch element, and is connected to the second power supply having a higher potential than the first power supply via the second switch element. Is
It is characterized in that it is connected to the third power source directly or through the third switch element.

The preferred embodiments of the present invention are as follows. (1) The first power supply is Vss and the third power supply is Vcc. (2) The potential of the second power supply is set to an intermediate potential (eg (1/4) Vcc) between the bit line precharge potential (eg (1/2) Vcc) and the first power supply (Vss). (3) The potential of the fourth power source should be an intermediate potential (eg (3/4) Vcc) between the bit line precharge potential (eg (1/2) Vcc) and the third power source (Vcc). (4) The second and fourth power supplies should be generated from the first and third power supplies in the chip. (5) The second and fourth power supplies are generated in two periods in which the third and fourth switch elements are off, that is, one of the bit line rewriting time or the bit line equalization to before bit sensing. Can occur in the time of. (6) Each of the second and fourth power supplies is connected to a stabilizing capacitor that is more than half the bit line capacitance of the cell array that is activated at one time. (7) The stabilizing capacitor is formed of the same insulating film as the memory cell capacitor. (8) A plurality of switch elements and a plurality of power sources having different potentials from the first and second power sources are connected to the first drive line, and a plurality of switch elements and a plurality of switch elements and the same are connected to the second drive line. Connecting multiple power supplies with different potentials from the third and fourth.

[0018]

In the present invention, the bit line precharge potential is (1/2) Vcc, the first power source is Vss, and the third power source is Vcc. Also, Vss and (1/2) Vcc are used as the second power source.
Has a large capacitor C2 having an intermediate potential Vm2 of
It is assumed that the fourth power supply has a capacitor C1 having a large capacity of an intermediate potential Vm1 between Vcc and (1/2) Vcc. Further, the first drive line is / SAN and the second drive line is SAP.

In this case, the precharge is, for example, (1/2) V
When cc is set, Vm1 is set to (3/4) Vcc, and Vm2 is set to (1/4) Vcc, the sense drive line / SAN and Vm1 are short-circuited at the time of bit line sensing, and the bit line is passed through capacitors C1 to / SAN. A current flows due to the charge distribution, and the potential of one of the bit line pair / BL0, BL0 rises. Here, as C1 is larger than half of the bit lines that are charged and discharged at one time, that is, the total capacitance (C _B total) of the bit lines that becomes "1", Vm1 approaches after the short circuit. The energy consumed at this time is the potential difference between Vm1 and (1/2) Vcc when C1 >> C _B total.
Since there is only (1/4) Vcc, the energy consumed through the resistor is (1/2) C _B total {(3/4) Vcc- (1/2) Vcc} ² = (1/32) C _B total ・ Vcc ² . At the same time, since the sense drive line SAP and Vm2 are short-circuited, when the capacitor C2 is larger than C _B total, the bit line which becomes “0” starts from (1/2) Vcc due to the charge distribution between C 2 and C _B total. (1/4) Vcc, and the energy consumption is (1/2) C _B total {(1/2) Vcc- (1/4) Vcc} ² = (1/32) C _B total · Vcc ² Becomes

Next, / SAN and SAP are set to Vss and Vcc, respectively.
Switch the connection to the line and set the bit line / BL0 (RL) to Vs
It is restored to s and Vcc, and the potential is written in the memory cell. The energy consumption at this time is (1/32) C _B to
It becomes tal.

Next, after lowering the word line, when equalizing the bit line, first, SAP and Vm1 are short-circuited, / S
If AN and Vm2 are short-circuited, a current will flow from the SAP and the bit line connected thereto to the capacitor C1 of Vm1, and the potential will be (3/4) Vcc. At this time, the charge flows in at the time of sensing, and since the charge is input at this time, it returns to the original (3/4) Vcc, so that the Vm1 potential is kept constant. Therefore, when the power is turned on (3 /
4) It is only necessary to set the voltage to Vcc and then correct the amount of fluctuation due to leakage in precharge, for example. The energy consumption at this time is (1/32) C _B total · Vcc ² .

Similarly, a current flows from the capacitor C2 of Vm2 to / SAN and the bit line connected thereto, and its potential becomes (1/4) Vcc. Since the amount of charge that has entered during sensing is discharged at this time, it returns to the original (1/4) Vcc, and Vm2 maintains a constant potential. Therefore, it is only necessary to set (1/4) Vcc once when the power is turned on, and then correct the fluctuation due to the leak at the precharge. The energy consumption at this time is (1/32) C _B total ・
It is Vcc ² .

Then, / SAN and SAP are switched to be short-circuited, and / SAN and SAP are set to (1/2) Vcc,
Precharge all bit line pairs to (1/2) Vcc. The power at this time is also (1/32) C _B total · Vcc ² .

Therefore, the energy consumption of one cycle is
_{(1/4) C B total · Vcc} 2 next can be reduced to half the conventional (1/2) Vcc precharge scheme. Further, the present invention can reduce energy in one cycle, as compared with the conventional method of recycling charge between other arrays. That is, since the charge is recycled by the sense and the equalize, the present invention may select the same cell array every time, arbitrarily select another array, and set the time to activate the array and the time to activate the next array. There may be a gap. That is, normal random access is possible.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIGS. 1 and 2 are for explaining a DRAM according to a first embodiment of the present invention. FIG. 1 is a circuit configuration diagram and FIG. 2 is an operation waveform diagram.

A normal one-transistor / one-capacitor memory cell, word line WL and bit line pair / BL0, B
L0, ..., / BLm-1, BLm-1, a sense amplifier composed of nMOS connected to a bit line pair, a sense amplifier composed of pMOS, and a sense amplifier drive line (first drive line) for driving the nMOS sense amplifier. / SAN and pMO
Sense amplifier drive line (second drive line) SAP for driving the S sense amplifier, and first switch elements (SEN10, ..., SEN1 (k−) connecting / SAN and Vss (first power supply)
1)) and a third switch element (/ SEP10, ..., / SEP1 (k-1)) that connects SAP and Vcc (third power supply), and a plurality of cell arrays are arranged. There is.

The structure up to this point is the same as that of the conventional DRAM, but in the present embodiment, in addition to this, the following switch element and power supply are provided. That is, the sense amplifier drive line /
For SAN, the second switch element (SEN00, ...,
SEN0 (k-2), SEN0 (k-1)) and Vss and (1/2)
A power source having a large capacitance C2 having a potential Vm2 during Vcc precharge is connected. Further, for the sense amplifier drive line SAP, a fourth switch element (/ SEP00,
,, / SEP0 (k-2), / SEP0 (k-1)) via Vcc
A power source having a large capacitance C1 having a potential Vm1 between (1/2) Vcc precharge and is connected.

Here, the stabilizing capacitors C1 and C2 are preferably formed of the same insulating film as the memory cell capacitors. In this embodiment, when the bit line precharge potential is (1/2) Vcc, Vm1 = (3/4) Vcc, Vm2 = (1 /
4) Vcc is desirable.

In operation, when the cell array 0 is operated, first the bit line precharge is stopped, the bit line is floated, and then the word line WL0 is selected. When performing the sense operation of amplifying the minute signal read from the memory cell to the bit line by the sense amplifier, first, / SEP00
LOW and SEN00 High, the sense drive line / SAN and Vm1 are short-circuited and the capacitor C1 to /
Current flows through the SAN to the bit lines due to charge distribution,
The potential of one of the bit line pair / BL0, BL0 rises, and C
1 approaches Vm1 half the bit line charge and discharge, i.e. after a short larger than the total volume of "1" becomes the bit line (C _B total) once. At this time, the energy consumed is the voltage difference between Vm1 and (1/2) Vcc when C1 >> C _B total.
Since there is only (1/4) Vcc, the energy consumed through the resistor is (1/2) C _B total {(3/4) Vcc- (1/2) Vcc} ² = (1/32) C _B total ・ Vcc ² . At the same time, when the capacitor C2 for shorting the SAP and Vm2 is large relative to C _B, "0" becomes bit lines by the charge distribution between C2 and C _B total (1/2) V
From cc to (1/4) Vcc, the energy consumption is also (1/2) C _B total {(1/2) Vcc- (1/4) Vcc) ² = (1/32) C _B total ・It becomes Vcc ² .

Next, return / SEP00 to High and SEN00 to Low, set / SEP10 to Low and SEN10 to High.
set to h. That is, / SAN and SAP are switched to the Vss and Vcc lines respectively to switch the bit line / BL0 RL to Vss and Vcc.
And the potential is written in the memory cell. The energy consumption at this time is (1/32) C _B total · Vcc
It becomes ² .

Next, when equalizing the bit lines after lowering the word lines, / SEP10 is set to High and SEN10 is set to Low, then / SEP00 is set to Low and SEN00 is set to H.
Turn to high. That is, when equalizing the bit lines, first, SAP and Vm1 are short-circuited, and / SAN and Vm2 are short-circuited. Then, current flows from SAP and the bit line connected to it to the capacitor of Vm1, and the potential is (3/4)
It becomes Vcc. Because the charge flows in at the time of sensing, the charge comes in at this time, so it returns to the original (3/4) Vcc. The Vm1 potential remains constant. Therefore, when the power is turned on, it is only necessary to set it to (3/4) Vcc and then correct the amount of fluctuation due to leakage in precharge, for example. Energy consumption at this time is (1/32) C _B tota
l · Vcc ² .

Similarly, a current flows from the Vm2 capacitor to / SAN and the bit line connected to it, and its potential is
It becomes (1/4) Vcc. Since the amount of charge that has entered during sensing is discharged at this time, it returns to the original (1/4) Vcc, and Vm2 maintains a constant potential. Therefore, it is only necessary to set it to (1/4) Vcc once when the power is turned on, and then correct the amount that has changed due to leakage during precharge. The energy consumption at this time is (1/32) C _B total ・
It is Vcc ² .

Next, / SEP00 is set to High and SEN00 is set to L.
Return to ow and set / EQL0 to High. That is, / S
Switch to short between AN and SAP / SA
Set N and SAP to (1/2) Vcc, and all bit line pairs (1/2)
Precharge to Vcc. The power at this time is also (1 /
32) C _B total ・ Vcc ² .

Therefore, the energy consumption of one cycle is
_{(1/4) C B total · Vcc} 2 next can be reduced to half the conventional (1/2) Vcc precharge scheme. Further, in the present embodiment, the energy can be reduced in one cycle as compared with the conventional method in which the charge is recycled between the arrays.
That is, since the charges are recycled by the sense and the equalize, the present embodiment may select the same cell array every time, other arrays may be arbitrarily selected, and the time for activating the array and the time for activating the next array may be selected. Ordinary random access can be performed because it may take a while.

In the operation of FIG. 2, the same word line of the same array (cell array 0) is read and written twice in succession, and then a certain word line of another array (cell array 2) is selected and read and written. An example is shown.
From this, it can be seen that random access is possible.

In order to minimize the power, Vm1 =
(3/4) Vcc, Vm2 = (1/4) Vcc. The larger the stable capacitors C1 and C2, the more stable Vm1 and Vm2. This capacitance can be realized in a small area when a cell capacitor is used.

In the normal memory cell array, 128 to 256 memory cells are connected to one bit line, and the capacity ratio of the memory cell capacity C _S to the bit line capacity C _B is 5 to 10.
Therefore, in order to realize the same bit line capacitance with only the memory cell capacitors, 5 to 10 memory cells are required.
In other words, in terms of area, it can be realized with a maximum of 10/128 to a minimum of 5/256. For example, even if C1 and C2 are set to 5 times the bit line capacity, the maximum (10 × 5) / 128 to the minimum (5 × 5) / 2
Can be realized with 56. These C1 and C2 can be used in common with a plurality of other non-operating arrays, and as the DRAM generation progresses, as shown in FIG. 10, the number of cell arrays activated at one time is reduced to half or half. That is, the number of cell arrays that can be shared by the present invention is increased, and as a result, the ratio of the area occupied by the capacitors C1 and C2 in the chip can be reduced.

For example, in the case of activating 1/64 cell array in a 1 Gbit DRAM, if C1 and C2 are set to 5 times the bit line capacitance and the ratio of the memory cell area to the chip is 50%, the chip of the C1 and C2 capacitors is The occupying ratio is maximum (10 × 5) / (128 × 64) × 0.5 to minimum (5 × 5) / (256 × 64) × 0.5 and 0.3% to
The chip overhead is small at 0.1%.

Further, by providing a plurality of potentials and switches different from the potentials of Vm1 and Vm2, for example, when SAP is lowered from Vcc to (1/2) Vcc, the power source is switched from higher to lower. In principle, the power can be reduced to 1 / n by going (when dividing into n and lowering). (Embodiment 2) FIG. 3 shows the D according to the second embodiment of the present invention.
It is a circuit block diagram which shows RAM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The operation waveform diagram is the same as that in FIG.

This embodiment is different from the first embodiment in that C
In the first embodiment, the power supplies at the opposite terminals of the capacitors C1 and C2 are connected to Vcc or Vss, whereas in this embodiment, C1 is connected to Vss and C2 is connected to Vcc. Is.

A current flows from outside the chip for charging the capacitor, and no current flows from outside the chip for discharging.
The time during which the current flows is different between the first embodiment and this embodiment. In the first embodiment, a current flows from the outside of the chip due to sensing and equalization, and in this embodiment, a current flows from the outside of the chip at the time of sensing C1 and C2. These can be selected by designing the peak current of the chip. (Embodiment 3) FIG. 4 shows the D according to the third embodiment of the present invention.
It is a circuit block diagram which shows RAM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The operation waveform diagram is the same as that in FIG.

The difference of this embodiment from the first embodiment is that
In the first embodiment, the power supplies at the opposite terminals of the capacitors C1 and C2 are connected to Vcc or Vss, whereas in this embodiment V1 is connected to C1 and Vss is connected to C2. Is.

A current flows from outside the chip for charging the capacitor, and no current flows from outside the chip for discharging.
The time during which the current flows is different between the first embodiment and this embodiment. In the first embodiment, current flows from the outside of the chip due to sensing and equalization, and in the present embodiment, current flows from outside the chip during equalization. These can be selected by designing the peak current of the chip. (Embodiment 4) FIG. 5 shows a D according to a fourth embodiment of the present invention.
It is a circuit block diagram which shows RAM. The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted. The operation waveform diagram is the same as that in FIG.

In this embodiment, the capacitor C0 is inserted between Vm1 and Vm2. As a result, despite the apparent capacitance of C0, it appears that there is 2C0 capacitance on the Vm1 side and 2C0 capacitance on the Vm2 side, and the area of the stable capacitance can be halved. (Embodiment 5) By the way, in contrast to the (1/2) Vcc bit line precharge system, the Vcc precharge system was applied in the previous generation of 256 kbit DRAM or less. This method requires twice as much power as the (1/2) Vcc precharge method. An embodiment in which the present invention is applied to the previous method, the Vcc precharge method, or the reverse Vss precharge method will be described below.

FIG. 6 shows a DR according to the fifth embodiment of the present invention.
FIG. 7 is a circuit configuration diagram showing the AM, and FIG. 7 is an operation waveform diagram thereof.
The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The first sense amplifier drive line / SAN is connected to Vss via the first switch elements (SEN10, ..., SEN1 (k-1)), and the switch elements (EQL0, ..., Equal) for equalization. It is connected to Vcc via EQLk-1) and further has a second switch element (SEN00, ..., SEN).
0 (k-1)) via Vss and Vcc precharge potential V
It is connected to a power supply with a large capacity C2 of m2. Second
Although the sense amplifier drive line SAP is directly connected to Vcc, it may be connected to Vcc through a switch element.

In this embodiment, the Vcc precharge system is used, and the intermediate power source Vm is preferably (1/2) Vcc. When selecting and sensing the word line after Vcc precharge, / SA
Short N and Vm and lower them to near (1/2) Vcc, then short Vss and / SAN to Vss. At the time of equalization, / SAN and Vm are shorted and raised to (1/2) Vcc. / SAN and Vcc are shorted and raised to Vcc.

Also in this embodiment, the power of the conventional Vcc precharge system can be reduced by half. (Sixth Embodiment) FIG. 8 shows a DR according to a sixth embodiment of the present invention.
FIG. 9 is a circuit configuration diagram showing the AM, and FIG. 9 is an operation waveform diagram thereof.
The same parts as those in FIG. 1 are designated by the same reference numerals, and detailed description thereof will be omitted.

The second sense amplifier drive line SAP has a third
, SEP1 (k-1), and Vss via the switch elements (EQL0, ..., EQLk-1) for equalization, and further connected to Vss. Switch element (SEP00, ..., SEP
0 (k-1)) via Vss and Vcc precharge potential V
It is connected to a power supply with a large capacity C1 of m2. First
Although the sense amplifier drive line / SAN is directly connected to Vss, it may be connected to Vss via a switch element.

This embodiment is of the Vss precharge type, and its intermediate power source Vm is (1/2) V as in the fifth embodiment.
cc is desirable, and SAP and Vm are shorted at the time of sensing (1 /
2) Set to Vcc, then short-circuit SAP and Vcc to sense up to Vcc. When equalizing, short SAP and Vm to (1/2) Vcc, short SAP and Vss to Vss
To

Also in the present embodiment, there is an advantage that the power of the system simply precharged to Vss can be halved. This V
The cc precharge and Vss precharge methods are opposite to DRAM
This is effective when the generation advances and Vcc becomes lower and the threshold voltage cannot be lowered below (1/2) Vcc, and power can be reduced even at this time.

The present invention is not limited to the above embodiments. It is desirable that the capacitors as the second and fourth power supplies are large, but it is sufficient that the capacitors each have a capacitance of at least half the bit line capacitance of the cell array activated at one time.
In addition, a plurality of switch elements and a plurality of power sources having different potentials from the first and second terminals are connected to the first drive line, and a plurality of switch elements and a plurality of switch elements are connected to the second drive line. You may make it connect several power supply of the electric potential different from the 3rd and 4th. As a result, the power required for charging / discharging the bit line can be further reduced. Other,
Various modifications can be made without departing from the scope of the present invention.

[0053]

As described above in detail, according to the present invention, V
By charging the cc and the precharge potential, and the potential with a large intermediate capacitor between Vss and the precharge potential, and charging and discharging the bit line once through this capacitor, the charge of the bit line is increased as compared with the conventional method. D that enables random access while reducing the power required for discharge
A RAM can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a DRAM according to a first embodiment.

FIG. 2 is an operation waveform diagram in the first embodiment.

FIG. 3 is a circuit configuration diagram showing a DRAM according to a third embodiment.

FIG. 4 is a circuit configuration diagram showing a DRAM according to a third embodiment.

FIG. 5 is a circuit configuration diagram showing a DRAM according to a fourth embodiment.

FIG. 6 is a circuit configuration diagram showing a DRAM according to a fifth embodiment.

FIG. 7 is an operation waveform diagram in the fifth embodiment.

FIG. 8 is a circuit configuration diagram showing a DRAM according to a sixth embodiment.

FIG. 9 is an operation waveform diagram in the sixth embodiment.

FIG. 10 is a diagram showing the relationship between the generation of DRAM and the ratio of cell arrays operated at one time.

FIG. 11 is a circuit configuration diagram showing a conventional DRAM.

12 is an operation timing chart of the DRAM of FIG.

FIG. 13 is a conventional D in which the charge / discharge power of the bit line is reduced.
FIG. 3 is a circuit configuration diagram showing a RAM.

14 is an operation timing chart of the DRAM of FIG.

[Explanation of symbols]

 BL ... bit line WL ... word line Vss ... first power supply Vcc ... third power supply Vm1 ... fourth power supply Vm2 ... second power supply SAP ... sense amplifier drive line (second drive line) / SAN ... sense amplifier Drive line (first drive line) SEN10 to SEN1 (k-1) ... First switch element SEN00 to SEN0 (k-1) ... Second switch element / SEP10 to / SEP1 (k-1) ... Third Switch element / SEP00 to / SEP0 (k-1) ... Fourth switch element

Claims (3)

[Claims] 1. A plurality of memory cells arranged at a ratio of one to at least two intersections of a plurality of bit lines and a plurality of word lines, and a plurality of nMOSs connected to each pair of bit lines.
A sense amplifier circuit and a pMOS sense amplifier circuit, and n
A first drive line for driving the MOS sense amplifier circuit, p
In a dynamic semiconductor memory device including a memory cell array including a second drive line that drives a MOS sense amplifier circuit, the first drive line is connected to a first power supply via a first switch element, And the second drive line is connected to the second power supply having a higher potential than the first power supply via the second switch element, the second drive line is connected to the third power supply via the third switch element, and A dynamic semiconductor memory device, characterized in that it is connected to a fourth power source having a lower potential than the third power source via a switch element of No. 4. 2. A plurality of memory cells arranged at a ratio of one to at least two intersections of a plurality of bit lines and a plurality of word lines, and a plurality of nMOSs connected to each pair of bit lines.
A sense amplifier circuit and a pMOS sense amplifier circuit, and n
A first drive line for driving the MOS sense amplifier circuit, p
In a dynamic semiconductor memory device including a memory cell array including a second drive line that drives a MOS sense amplifier circuit, the first drive line is directly connected to a first power supply via a first switch element. The second drive line is connected to the third power supply via the third switch element, and is connected to the fourth power supply having a lower potential than the third power supply via the fourth switch element. A dynamic semiconductor memory device characterized by the above. 3. A plurality of memory cells arranged at a ratio of one to at least two intersections of a plurality of bit lines and a plurality of word lines, and a plurality of nMOSs connected to each pair of bit lines.
A sense amplifier circuit and a pMOS sense amplifier circuit, and n
A first drive line for driving the MOS sense amplifier circuit, p
In a dynamic semiconductor memory device including a memory cell array including a second drive line that drives a MOS sense amplifier circuit, the first drive line is connected to a first power supply via a first switch element, Further, the second drive line is connected to the second power source having a higher potential than the first power source via the second switch element, and the second drive line is directly connected to the third power source via the third switch element. And a dynamic semiconductor memory device.