JPH022237B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to one-device FET dynamic random access memory arrays, and more particularly, in which a portion of a word line is used as an electrode of a memory cell storage capacitor. Apparatus for avoiding problems caused by short-channel effects in single polysilicon, one device FET dynamic RAM arrays.
When such a word line is interrogated, a boosted voltage develops across the source-drain of the FET devices of the un-addressed memory cells, causing them to conduct and erroneously erasing information. More specifically, the present invention shortens channels in such memory arrays by opening a pair of bit line switches such that the potential on the unselected bit line remains at a pre-charged potential. It pertains to techniques for avoiding problems arising from effects. In this way, the potential difference at the source-drain of the FET of an unselected memory cell can be ensured such that all bit lines do not exceed the pre-charged potential.

BACKGROUND OF THE INVENTION To the extent that a memory cell in an array of memory cells is considered in isolation from other memory cells in the array, if a memory cell is considered in relation to its neighboring memory cells, Problems detected when the system is used are often recognized at a later stage of development and require equipment and circuitry to solve the problems. In many instances,
A problem arises when array dimensions are reduced to increase memory array density. for example
A phenomenon that does not appear in 2.5 μm line width technology is
This becomes noticeable when 1.0 μm linewidth technology is used. For example, if the linewidth is reduced and the source-drain spacing of the memory cell FET device is reduced without similarly reducing the memory cell voltage, the result of a boosted voltage on the memory cell storage capacitor is As such, a phenomenon known as the short channel effect appears, especially when the memory cell word line is used as the electrode of a storage capacitor. A short channel effect occurs when the depletion region adjacent to the drain extends to the vicinity of the source.
Lower device thresholds. In such an environment, the FET device becomes conductive and the information stored in the associated capacitor is inadvertently discharged to ground.

In commercially available 64K bit chips, a single layer of polysilicon was used to form a high density memory array. In that array, one memory
Storage capacitors for cells use adjacent word lines for capacitor electrodes. By using a solution technique called folded bit line, adjacent pairs of bit lines are connected to a sense amplifier that operates according to the differential signal between the two lines, as is known in the art. Sensing is performed in this way. However, if writing or rewriting a memory cell that has been destructively read is done by energizing the selected word line and bit line, then the memory cell associated with the selected line and unselected bit line Information stored in the network may be lost due to short channel effects. This is especially true for
This is the case in high density memory arrays where the minimum spacing between the source and drain of a cell FET device greatly contributes to achieving high density. If the FET of a memory cell has a minimum spacing between the drain and source, the depletion region from the drain due to large applied voltages as described above will extend into the vicinity of the source, lowering the switching threshold of the device. This is the short channel effect, and in such an environment,
A device receiving a high potential between its source and drain discharges its series-arranged storage capacitor, thereby losing the data to be held. This problem will become clearer when the conventional memory array shown in FIG. 1 is discussed in more detail below. In cases where the problem of short channel effects exists, it is
The problem can be solved by deenergizing the bit line switch associated with the bit line of the unselected memory cell by a method described in more detail below in connection with the figures.

Single polysilicon 1-device FET memory
The cell is well known and is called “A 34 μm ² DRAM Cell”.
Fabricated With a 1μm Single-Level
Polyoide FET Technology”by HHChaoet
al.1981 IEEE International Solid−State
Circuits Conference, Digest of Technical
Papers, February 1981, p. 152.

Regarding the use of bit line switches, refer to “A”.
High Performance Sense Amplifier For a
5V Dynamic RAM” by JJBarnes et al.
IEEE Journal of Solid State Circuits, Vol.
Disclosed in SC15, No. 5, October 19, 1980, page 831. When bit line switches are used in environments where the particular problem solved by the present invention (short channel effect) does not occur, the function of these bit line switches is quite different.

In US Pat. No. 4,103,342 a bit line switch device is shown in which the upper and lower parts of a pair of bit lines are connected simultaneously to a shared sense amplifier.

“Field Effect Transistor Memory” by R.
Kruggel in the IBM Technical Disclosure
Bulletin, Vol.14, No.9, February 1972,
Page 2714 shows a memory array in which a boost voltage can be applied to the capacitors that form the storage element for unselected memory cells by applying a potential to the word line. has been done.

For using switched bit lines, see “A 64Kb MOS Dynamic RAM” by I.Lee.
et al.1979 IEEE International Solid State
As shown in Circuits Conference February 1979, p146. A bit line switch is utilized in this document to reduce the capacitance of the bit line.

In these references, specific circuit configurations such as shared sense amplifiers and bit line switches are known, while single polysilicon circuits such as the word line is used as the top electrode for the memory cell storage capacitor. It is apparent that there is no explanation for the problems associated with short channel effects in memory arrays using memory cells.

It is therefore a primary object of the present invention to provide a memory array in which problems associated with short channel effects are avoided without increasing the threshold values in the array devices or without increasing the drain-source spacing in these devices. It is to be.

Another object of the present invention is to maintain precharge on the bit lines of certain unselected memory cells during read, write, and refresh memory array cycles, thereby eliminating problems associated with short channel effects. It is an object of the present invention to provide a memory array using a shared sense amplifier and a single polysilicon memory cell, such that the invention is avoided.

Still another object of the invention is that the paired bit lines share a single sense amplifier, the unselected one of the bit lines of the pair is connected to the sense amplifier from its associated sense amplifier and all the bit lines are The object is to provide a memory array which is simultaneously insulated from any potential different from the potential to which it is pre-charged.

Still another object of the present invention is to provide a memory cell FET.
Methods such as increasing the threshold voltage of these devices or increasing the drain-to-source spacing of these devices, with concomitant reductions in density and other device dimensions achieved by decreasing linewidths. The goal is to provide a high density memory array that can be avoided without impact.

SUMMARY OF THE INVENTION The present invention provides a single polysilicon one device FET dynamic random access memory (RAM) that produces short channel effects at reduced linewidths of, for example, approximately 1 micrometer.
It provides an array. If the chip linewidth is reduced, the associated device dimensions are proportionally scaled to achieve higher densities.
drain without reducing device voltage.
In cases where source spacing is minimized, information in memory cells associated with unselected bit lines can lose that information due to short channel effects. If the voltage difference at the source and drain exceeds the voltage at which all bit lines were pre-charged, then
The threshold voltage of a FET device is affected such that the FET falsely conducts and the information stored in the associated storage capacitor is lost. In the present invention, the above effect is achieved by opening a pair of bit line switches after the bit line has been charged to voltage Vdd so that the potential on the unselected bit line is maintained at Vdd and does not reach zero voltage. thwarted.
During read, write, and refresh memory cycles, there is the possibility of applying a potential to the source-drain of a FET associated with a bit line that has not been accessed. After precharging to voltage Vdd, the unselected bit lines, which would normally drop to ground potential, are held at potential Vdd by opening the bit line switches. The latter potential exists at the source of the FET device connected to each of the unaccessed bit lines.
If the storage capacitors arranged in series are charged to approximately Vdd, this potential will appear at the drain of each FET associated with the unaccessed bit line, and the source-drain potential difference will be determined by the design of the auxiliary circuit. is approximately the threshold voltage V _t of the FET, depending more or less on .
When writing to, reading from, or refreshing an accessed memory cell, other memory cells with storage capacitor electrodes formed from the accessed portion of the word line will be activated when the word line rises by approximately Vdd. , it experiences an additional voltage of approximately Vdd. Any storage node already charged to potential Vdd will experience an additional voltage change manifesting as a potential of approximately 2 Vdd at the drain of its associated series-arrayed FET.
Already approximately Vdd at the source of the FET device
Since there exists a potential of Vdd, the potential difference between the drain and the source is maintained at approximately the potential of Vdd, and the probability that the short channel effect starts to act is reduced. This is because the boost voltage 2Vdd does not appear at the device. When implementing the above solution, four switches per paired bit line are required, sharing a common sense amplifier. Each bit line has two switches and a pulse source is used to energize the two switches per bit line at different times. Apart from this, the operation of the memory array of the present invention is conventional.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a conventional single polysilicon 1-device FET dynamic random access array showing how stored information can be inadvertently lost if short channel effects are not taken into account. A block diagram is shown. The portion of the array shown uses the well-known folded bit line technique in which paired bit lines share a common sense amplifier. FIG. 1 shows a portion 1 of a memory array employing the folded bit line technique described above. In this technique, adjacent bit lines in pairs are connected to a sense amplifier 3. Sense amplifier 3 operates with a differential signal between paired bit lines to provide an output signal.

In FIG. 1, each single n-channel
A memory cell 4 consisting of a FET 5 and a series connected charge storage capacitor 6 is disposed between each bit line of each pair of bit lines 2 and an associated word line 7. In FIG. 1, the top pair of bit lines 2 are shown as bit line 1 (top) and bit line (bottom), and the bottom pair of bit lines 2 are shown as bit line 2 (top) and bit line (bottom). Shown as bit line 2 (bottom). Furthermore, word line 7
From left to right in Figure 1 are word line n, word line n+
1, word line n+2 and word line n+3. For example, in the leftmost memory cell 4, the source electrode of its transistor 5 is connected to bit line 1.
(top) and its drain is connected to capacitor 6
is connected to one electrode of the The other electrode of capacitor 6 is connected to word line n+1.
The gate electrode 8 of the transistor 5 of the upper leftmost memory cell 4 is connected to the word line n. Each memory cell 4 in the top row of memory cells 4 is similarly connected to an adjacent word line 7, such as bit line 1 (top) and word line n+2, word line n+3.

The other of the top bit line pair, bit line 1
(Bottom) shows the transistor 5 of the memory cell 4 located directly below the upper leftmost cell 4 in FIG.
is connected to the source electrode S of. The drain electrode D of the same transistor 5 is connected via the node A to one electrode of the capacitor 6 associated therewith;
The other electrode of capacitor 6 is connected to word line n. The gate electrode 9 of the same transistor 5 is connected to word line n+1. All other memory cells 4 in the same row are connected in the same way to bit line 1 (bottom) as well as to the associated word lines 7 of different pairs.

Next, looking at the memory cells 4 connected to bit line 2 (top) and bit line (bottom), these memory cells 4 connect to bit line 1 (top) and bit line 1 (bottom), respectively. It can be seen that they are connected in a similar manner to the connected memory cells 4.

Array portion 1 in FIG. 1 operates as follows during the read portion of the memory cycle.
When a predetermined word line 7, e.g. word line n, is selected, the capacitor 6, e.g. It is connected.

Depending on the stored voltage state of capacitor Cn,1 a signal appears on bit line 1 (top),
A differential sense signal is generated by using a dummy cell (not shown) with a half charge stored on bit line 1 (bottom) in accordance with known methods. However, if word line n is selected and connects the memory cell capacitor Cn,1 to the topmost of the sense amplifiers 3, then it also transmits a positive signal to the top leftmost memory cell 4. to node A of memory cell 4 directly below. Node A is located between transistor 5 and capacitor 6 (designated as Cn+1,1 in FIG. 1). The capacitor can be accessed through the word line n+1 and the transistor 5 arranged in series, which is gated via the gate 9. Word line n+1 is held at ground potential. After the sensing operation is complete, the data being read is typically refreshed by placing a positive potential on bit line 1 (top). That is, data can be rewritten into the storage capacitor Cn,1 via the associated FET transistor 5, which is still conducting as a result of the positive potential on the gate 8. At the same time, a complementary signal (ground level) is generated on the opposite side of the sense amplifier latching circuit and applied to bit line 1 (bottom). The FET transistor 5 that accesses the node A and the capacitors Cn+1, 1 is in a state where the ground potential level is applied to its source S, and a high voltage is applied to its drain D. This is because node A to which it is connected has been boosted to a relatively large value by accessing word line n to rewrite data to capacitor Cn,1. If the spacing between the drain and source of transistor 5 connected to node A is sufficiently small, the application of a high voltage will extend the depletion region from drain D to near source S, and the device Lowers the switching threshold (short channel effect). The threshold of that transistor 5 must be designed to be high enough so that it remains off even under this condition to prevent the discharge of the stored voltage at node A. That is, if Vdd is applied to word line n, capacitor Cn+1,1 is approximately
If we are storing a binary value "1" represented by a voltage of Vdd, then the voltage is additive and a potential of approximately 2Vdd is present at the drain/source of transistor 5 associated with capacitor Cn+1,1. appear. If that transistor conducts, the voltage on capacitor Cn+1,1 is discharged and information is lost.

In a typical memory array, the FET threshold value of a memory cell must be on the order of one volt to keep these devices completely off even under worst case manufacturing tolerance conditions. This results in some reduction in threshold (typically around
0.2 volts). However, the single polysilicon layer memory in the array of FIG.
Boosting the memory cell voltage unique to the cell results in an additional drop in threshold voltage of as much as 0.2 volts in minimum channel length FET devices. To compensate for this, the array
It is necessary to increase the drain/source spacing to increase the threshold value in the device or to avoid short channel effects.
The former alternative is that if a larger word line voltage is not used (a disadvantage), the charge stored on the capacitor will be lost due to the larger threshold drop that occurs in the device during writing. The second alternative results in a lower density due to the larger channel length (approximately 20-30%), resulting in increased capacitive loading on the word line due to the larger gate area and cell The larger size increases the bit line capacitance. These solutions are unsatisfactory because the alternatives mentioned above have adverse effects. The memory array shown in FIG. 2 overcomes the problems caused by short channel effects without imposing undue requirements on the resulting memory array.

Referring to Figure 2, a single polysilicon 1 device where a bit line switch is used to avoid problems caused by short channel effects.
A block diagram of a FET dynamic random access memory array is shown. FIG. 2 shows a portion of the memory array 1 in which the portions of the paired bit lines are symmetrically arranged and share the same sense amplifiers, differing in this respect from the folded bit line technique shown in FIG. It is shown. The same reference numbers and letters used in FIG. 1 are used in FIG. 2 for the same elements. The arrangements of FIGS. 1 and 2 are identical in that the memory cells 4 are connected to the bit lines 2 and word lines 7 in the same way. However, bit line 2 has the following parts: bit line L (top),
Bit line R (top), bit line L (bottom), bit line R
(Bottom) Each of the above bit line sections is connected to a bit line switch L (top), R (top), L
(bottom) and R (bottom) are arranged in series. Bit line switches L (top) and R (top) are energized by power supply V (top), and bit line switches L (bottom) and R (bottom) are energized by power supply V (bottom). . Each row of memory cells 4 has similar bit line sections and similarly activated bit line switches. Sense amplifier 3 is shown in some detail in FIG. 2 to clearly illustrate how the bit line switch works in conjunction with a standard cross-coupled sense amplifier. The sense amplifier 3 includes a pair of cross-coupled FETs T1 whose gates are cross-coupled to nodes N1 and N2;
Contains T2. A pair of FETs T3 and T4 each have a power supply
Connect Vdd to nodes N2 and N1. FET T3, T4
is energized by a power supply φPC connected to the gate electrodes of devices T3 and T4. Power supply VSet is connected to FET T1 and T2. Further, a pair of input/output lines, ie, I/O, which apply a signal and its complementary signal to word line n and word line n+1, respectively, during writing are connected to the node N2 of the sense amplifier 3 via a pair of FETs T5 and T6. , N1, respectively. FETs T5 and T6 are energized by a power supply Yc connected to their gates.

In operation, the capacitance of all bit line sections is precharged to the level Vdd by applying a voltage φPC that turns on FET devices T3, T4. During the pre-charge cycle, bit line switches L (top), R (top), L (bottom) and R (bottom) are placed at potentials V (top) and V (bottom) with respect to the appropriate associated switches.
is made conductive by applying . I/
If you want to store the binary value "1" in the capacitor Cn,1 by applying a positive potential to the O line, you can do so by applying the decoder output Yc to the gates of FETs T5 and T6. FET T5 and
T6 becomes conductive. Due to the conduction of FET T5,
Bit line switch L (top) and capacitor Cn, 1 conductive by application of power supply V (top) from I/O
A current path is formed through transistor 5 of memory cell 4 in series with . Transistor 5 is made conductive by applying potential Vdd to gate 8 via word line n. Capacitor Cn,1 is now charged to a potential of approximately Vdd.

Similarly, by simply applying ground potential to the input/output line I/O, capacitor Cn, 1 and 2
A base value of “0” can be stored.

In order to read or sense the information stored in the capacitor Cn, 1, the word line n is energized and the node N2 of the sense amplifier 3 is connected to the associated
Due to conduction of FET5, the potential applied to node N2 becomes higher or lower than that of node N1 depending on the potential of capacitor Cn,1. If a binary value "1" is being sensed, the potential at node N2 is a high potential, ie Vdd, and device T2 of sense amplifier 3 is rendered conductive. Device T1 remains non-conductive because the potential at node N1, taken from a dummy cell (not shown), is insufficient to cause it to conduct. When device T2 is conducting, current flows through the I/O line, device T6, node N1, and device T2 to VSet, which is at ground potential. Conversely, node N2
is at a low potential as a result of the binary value “0” being stored in capacitor Cn,1, device T1 conducts and the I/O line, device T5, node
N2 and device T1 are at ground potential
Current flows to VSet. Under such circumstances, assuming that bit line L (bottom) is connected directly to node N2, a low potential at node N2 appears at the source S of FET 5 connected to bit line L (bottom). Memory capacitor Cn+1, 1 again
If is charged to a potential of approximately Vdd indicating the storage of a binary value "1", the potential difference at the source S and drain D of FET 5 arranged in series is approximately
Vdd. However, word line n is energized for reading, writing, or refreshing with respect to the memory cell associated with any of the bit lines that is the designated bit line (top) and the node
When N2 is at a low potential, the potential of approximately Vdd applied to word n is additive with respect to the potential stored in capacitor Cn+1,1, so that approximately twice the potential of 2Vdd is placed in series.
Appears at the drain of FET5. With a low potential applied to the source S, the source/drain potential difference is approximately 2Vdd, causing a short channel effect, which causes the FETs associated with capacitors Cn+1, 1 to
5 conducts, resulting in the erroneous erasure of the information stored in that capacitor.

However, by providing a bit line switch in each of the bit lines as shown in FIG. 2, the unselected bit lines can be isolated from ground potential and held at potential Vdd. This creates a potential difference at the source/drain of any memory cell FET that is approximately no greater than Vdd. In this example, bit line switch L (lower)
and R (bottom) are deenergized by the removal of potential V (bottom), so that bit lines L (bottom) and R (bottom) do not fall to the low potential of node 2. The source S of the transistor 5 arranged in series is always maintained at approximately Vdd, and its drain D is connected to the capacitor Cn+1,
When 1 stores the binary value "0", approximately Vdd is applied, and the capacitor Cn+1, 1 stores the binary value "1".
When storing , it exhibits either 2Vdd.
In either case, the maximum drain-source potential difference is always approximately Vdd and approximately twice
Excessive threshold voltage drop (short channel effect) due to 2Vdd drain-source potential difference is avoided. At this point, an unselected bit line portion in any row of memory cells 4 is connected to a pair of bit lines 2
It is clear that if it is the lower bit line of the lower bit line, then all the lower bit line switches of all other lower bit line sections must be open. Similarly, if the upper bit line of a pair of bit line 2 sections is not selected, all upper bit line switches of all other upper bit line sections must be open.

If the memory cell 4 is being refreshed, all unselected bit lines below or above must have their associated bit line switches deenergized, provided the same conditions as above occur.

From the above, it can be concluded that the operation of the sense amplifier 3 is not different from that of known sense amplifiers, and that the memory
Although cell portion 1 has been described in relation to an n-channel device, the device used may also be a p-channel device.
It is clear that it may be a device. As can be seen from the above, each memory cell in array portion 1 is selected in a manner similar to that described above. That is, a similar pair of memory cells 4 at any location in a memory array of the same type.
The operation was explained. The manufacturing processes involved in manufacturing memory arrays of the type described above do not form part of the present invention. In one exemplary array, potential Vdd may be 5 volts and V(top) and V(bottom) may be 7 volts.

[Brief explanation of drawings]

Figure 1 shows conventional random access memory.
FIG. 2 is a diagram of an array. FIG. 2 is a diagram of a random access memory array according to an embodiment of the invention. In FIG. 2, 1... memory array, 2...
...Bit line, 3...Sense amplifier, 4...Memory
cell, 5...transistor, 6...capacitor,
8...gate, 9...gate.

Claims (1)

[Claims] 1. One electrode is connected to one of the pair of bit lines via a FET controlled by one of the pair of word lines, and the other electrode is integrally connected to the other of the pair of word lines. a first storage capacitor connected to the first storage capacitor, one electrode of which is connected to the other of the pair of bit lines via a FET controlled by the other of the pair of word lines; a second storage capacitor integrally connected to one of the word lines of the bit line; a sense amplifier for sensing the states of the first and second storage capacitors; and between each of the pair of bit lines and the sense amplifier. switch means for decoupling the unselected one of the pair of bit lines from the sense amplifier when one of the pair of word lines is selectively energized; memory array.