JPH0785354B2 - Semiconductor memory - Google Patents

Description

The present invention relates to a semiconductor memory.

(Prior Art and Problems Thereof) Semiconductor memories have achieved large capacity and high performance due to reduction of geometrical dimensions. If the geometrical dimension reduction is performed in the same ratio in the horizontal and vertical directions, the wiring resistance increases in proportion to the reciprocal of the geometrical dimension reduction rate, resulting in performance degradation (increase in delay time). Invite. In addition, electromigration becomes strict, which causes a problem in device reliability. Further, if the interlayer insulating film is thinned, the risk of short circuit between wirings due to pinholes or the like increases. Therefore, generally, a method is adopted in which the vertical direction is hardly reduced and only the horizontal direction is reduced. If the vertical and horizontal dimensions of the wiring cross section become the same size as this method continues to shrink further, the mutual capacitance between adjacent wirings will rapidly increase in the total wiring capacitance. . Then, the potential fluctuation of the adjacent wiring has a great influence. In the case of a semiconductor memory, this problem becomes particularly noticeable in the bit line. When a certain word line is selected and the information of the memory cell is read to the bit line, the signal amount of the bit line is reduced due to the influence of the potential change of the adjacent bit line, and the operation margin is reduced. is there. To prevent this,
It is sufficient that the potential of the adjacent bit line does not change when information is read out to a certain bit line. In other words, every other bit line may be activated.

Conventionally, a semiconductor memory as shown in FIG. 2 in which the bit line is divided is known from the viewpoint of reducing C _B / C _S , not from such a viewpoint (Electronic Material Vol.23, No.3, 1981, P15
7). In this known example, two pairs of bit lines BL1 and BL4 are used.
And BL2 and BL3 are connected to a common sense amplifier 2 via transfer gates T1, T2, T3, T4, and when the word line WL1 is selected, the transfer gates T1, T4 are conductive,
The bit line pair BL1, BL4 is connected to the sense amplifier 2, the information of the bit line pair BL1, BL4 is amplified, and when the word line WL2 is selected, the transfer gates T2, T3 become conductive and the bit line pair BL2, BL3 becomes The information of the bit line pair BL2, BL3 connected to the sense amplifier 2 is amplified, and the unselected bit line pair is separated from the sense amplifier 2.

In this known example, since the bit line precharge signal φ _P is turned off before the word line rises, the unselected bit line pair is disconnected from the constant voltage source V _CC and becomes a floating state. Therefore, in the known example, even if every other bit line is activated, the bit line that is not activated is in a floating state, so that the shield effect is small and the potential change of the bit lines separated by one line is suppressed. As a result, there is a problem that the signal voltage decreases. Moreover, since the I / O buses A and B are arranged on one side in the known example, a new problem occurs. For example, consider the case where the word line WL1 is selected and "1" is stored in the memory cell 1. When the sense amplifier 2 operates by setting the sense amplifier activation signal φ _SE to a low potential, the bit line BL1 is kept at a high potential,
The paired bit line BL4 is at the ground level. Here, the transfer gate T2 is opened, and the control signal φ _I of the transfer gate T5 and the transfer gate T6 is set to a high potential via the bit line BL2 to transfer information to the I / O buses A and B. Therefore, the bit line BL2 at the precharge level becomes the ground level, and the bit line BL1 at a high potential receives the influence of this potential change, and the potential drops. That is, when the mutual capacitance between adjacent bit lines is large, this known memory malfunctions, which is a very serious problem.

As described above, the known semiconductor memory has a problem that when the mutual capacitance between adjacent bit lines becomes relatively large, the operation margin decreases and the inversion of information occurs.

Therefore, an object of the present invention is to provide a semiconductor memory that has a sufficient operation margin and is less likely to invert information even when the mutual capacitance between adjacent bit lines is large in the total wiring capacitance of the bit lines. To provide.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the first invention of the present subject provides means for connecting a first bit line pair to a sense amplifier via a first switch circuit. The second bit line pair is connected to the sense amplifier via the second switch circuit, and the first switch circuit is opened when the memory cell connected to the first bit line pair is selected. To bring the first bit line pair and the sense amplifier into a conductive state,
A semiconductor memory in which the second switch circuit is opened to bring the second bit line pair and the sense amplifier into a conductive state when a memory cell connected to the second bit line pair is selected, The two bit lines forming each bit line pair are arranged on opposite sides of the sense amplifier, and the first bit line pair precharges the first bit line pair.
A precharge signal input circuit and a second precharge signal input circuit for precharging the second bit line pair are provided, and the bit line pair to which unselected memory cells are connected is read. It is characterized in that it is held in a precharged state during the period.

(Operation) The present invention has solved the problems of the known art by the means described above.

That is, the present invention is based on the idea of fixing the potentials of adjacent bit lines to eliminate the influence of the capacitance between adjacent bit lines. In other words, by using the divided bit line method that activates every other bit line, it is possible to precharge adjacent bit lines separately and connect all bit lines to the I / O bus. The potential of the unselected bit line is held at the precharge level during the read period, and the effect as a shield line is provided.

(Example) Hereinafter, the Example of this invention is described with reference to drawings.

FIG. 1 is a diagram showing the configuration of a typical embodiment of the present invention. Although the dummy cell is omitted in this embodiment, the dummy cell may be added to the bit line from which the information from the memory cell is read, or may be paired with the bit line from which information has been widely used in the past. It may be added to the bit line.

Consider the case where word line WL1 is selected in FIG. First, before the word line WL1 becomes high potential, the precharge signal φ _P1 connecting the bit line BL1 and bit line BL4 to the constant voltage source V _CC is made low potential, and the bit line BL1 and bit line BL4 are made constant voltage source. Disconnect from V _CC . Meanwhile, the bit line
The precharge signal φ _P2 of BL2 and the bit line BL3 remains at the high potential, and the bit lines BL2 and BL3 are held in the precharged state. Further, the control signal φ _T1 of the transfer gate T1 that connects the bit line BL1 to the sense amplifier 2 and the transfer gate T4 that connects the bit line BL4 to the sense amplifier 2 becomes high potential, and the bit line BL1 and the bit line BL4.
Is connected to the sense amplifier 2. Transfer gate T2 and bit line connecting bit line BL2 to sense amplifier 2
Transfer gate T3 connecting BL3 to the sense amplifier
The control signal φ _T2 of the bit line BL2 and the bit line BL3
Is separated from the sense amplifier 2. In this state, the word line WL1 has a high potential, and the information in the memory cell 1 is read to the bit line BL1. At this time, as described above, the bit line BL2 is fixed at a constant potential and the potential does not change.

Although FIG. 1 shows one sense amplifier, a large number of sense amplifiers are actually arranged, and if the bit lines are arranged in the same manner as in FIG. 1, both of the activated bit lines are shown. There is always a bit line fixed to a constant potential next to it, and this constant potential bit line serves as a shield line, and the capacitive coupling between the activated bit lines can be ignored. That is, the loss of the signal voltage due to the mutual capacitance between the adjacent wirings at the time of reading information from the memory cell is significantly reduced.

In addition, in the present embodiment, the sense amplifier 2 serves as the bit line BL.
After amplifying the signals of 1 and the bit line BL4, the control signals φ _I1 of the transfer gate T5 and the transfer gate T8 are set to a high potential, so that the I / O bus A and the I / O bus B are connected to the bit line BL1 and the bit line BL4. The information of each is output. Therefore, unlike the known example shown in FIG. 2, since the bit line which is not activated is not used for output, there is no influence of capacitive coupling at the time of output. When the word line WL2 is selected, the bit line BL2 and the bit line BL3 are activated, the bit line BL1 and the bit line BL4 remain in the precharged state, and the same operation as described above is performed.

(Effects of the Invention) As described above, according to the present invention, even when the mutual capacitance between adjacent bit lines is large, the loss of signal data of the bit lines is small, and therefore the operation margin is sufficient and the inversion of information can be performed. A semiconductor memory with less fear can be obtained.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration of a typical embodiment of the present invention, and FIG. 2 is a diagram showing the configuration of a known semiconductor memory. WL1, WL2, WL3, WL4 …… Word line, BL1, BL2, BL3, BL4 …… Bit line, T1, T2, T3, T4, T5, T6, T7, T8 …… Transfer gate, φ _T1 , φ _T2 , φ _I , φ _I1 , φ _I2 ...... Control signal,
φ _P , φ _P1 , φ _P2 …… Precharge signal, φ _SE …… Sense amplifier activation signal, A, B …… I / O bus, V _CC …… Constant voltage source, 1 …… Memory cell, 2… ... sense amplifier.

Claims (1)

[Claims] 1. A first bit line pair is connected to a sense amplifier via a first switch circuit, and a second bit line pair is connected to the sense amplifier via a second switch circuit. When a memory cell connected to one bit line pair is selected, the first switch circuit is opened to bring the first bit line pair and the sense amplifier into a conductive state,
In the semiconductor memory, when the memory cell connected to the second bit line pair is selected, the second switch circuit opens to bring the second bit line pair and the sense amplifier into a conductive state. Two bit lines forming a bit line pair are arranged on opposite sides of the sense amplifier, and the first bit line pair precharges the first bit line pair.
A precharge signal input circuit and a second precharge signal input circuit for precharging the second bit line pair are provided, and the bit line pair to which unselected memory cells are connected is read. A semiconductor memory, which is held in a precharged state for a period.