JPH09186251A - Dynamic sram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an SRAM (static memory) capable of operating at a high speed with a small power-supply consumption current. SOLUTION: In the load circuit of a flip-flop Q1+Q2 constituting a memory cell CEL11, a pair of capacitors C1+C2 charged to the corresponding voltage to a bit-line voltage (about Vdd) is used. The pair of capacitors C1+C2 holds the circuit potential for maintaining the circuit operation state (information storing state) of the flip-flop Q1+Q2 not to hold directly the storage information of the memory cell CEL11. But, when the charge accumulated in the pair of capacitors C1+C2 is discharged by leakage currents, etc., to lower the drain voltage of the flip-flop Q1+Q2 to the one not larger than a certain limit, the circuit operation state of this flip-flop Q1+Q2 can not be maintained to volatilize the storage content of the memory cell CEL11. For preventing the volatilization of the storage content, there are provided means Q11-Q42; DW10+DB10 for charging refreshingly at a certain period the pair of capacitors (C1, C2; information non-holding medium).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage device that involves a refresh operation to maintain stored information.

[0002]

2. Description of the Related Art Currently, mainstream semiconductor memory devices are a dynamic memory (hereinafter referred to as DRAM) which requires refreshing to maintain stored contents and a static memory (hereinafter referred to as SRAM) which does not require refreshed to maintain stored contents. It can be roughly divided.

The DRAM retains its stored contents by charging a very small capacity memory cell capacitor. If the electric charges (stored contents) charged / stored in the memory cell capacitor are left as they are, they will disappear within a short time due to a leak current inside the memory chip. In order to prevent the loss of the stored contents, in the DRAM, the stored contents are once read out from the individual memory cells with a relatively short cycle (usually within 10 ms) in a period when there is no external memory access (read / write). The read contents are written back to the same memory cell. The read / write-back operation of the stored contents repeated in this short cycle,
This is called a DRAM refresh operation.

Since the refresh operation in the DRAM is repeated charging / discharging with respect to the total capacitance of all memory cell capacitors, the power consumption of the refresh operation is large.

On the other hand, the SRAM retains its stored contents depending on the operating state of the flip-flop which is always in the power supply state (one of the pair of cross-connected transistors is on or off). The SRAM does not need a refresh operation (read / write back operation of stored contents) like that of a DRAM, and has a minimum power supply current required to maintain a circuit operation state of a flip-flop (it can be suppressed to almost a leak current level). Only possible).

However, in order to obtain the above-mentioned feature of the SRAM "consumes almost no power supply current", the DC resistance value of the drain load circuit of the flip-flop needs to be extremely large. For example, S operating at power supply voltage + 3V
To keep the current consumption per cell of RAM below 1 nA (nanoampere), the drain load resistance is 3000M.
Must be greater than Ω.

[0007]

Generally, the high resistance load resistance (a pair of flip-flop load resistances) of SRAM is formed of low impurity concentration polysilicon. However, since this polysilicon high resistance has a high temperature dependency, at a high temperature, the resistance value becomes small and the power consumption current increases. On the other hand, at low temperatures, the value of the pair of flip-flop load resistors does not always balance and increases,
The balance of the operational states of the flip-flop circuit is lost, and an error easily occurs in the stored contents. To prevent this, keep the flip-flop load resistance low and allow the flip-flop circuit current to flow to some extent so that the on / off state of the flip-flop does not change even if the load resistance balance is slightly disturbed. There is a need.

After all, in an SRAM using a high resistance load resistor, there is a trade-off relationship between low current consumption and low error occurrence rate.

An object of the present invention is to provide a new type SRAM which can operate at high speed with a power consumption current as low as that of an ordinary SRAM and yet is less likely to cause an error.

[0010]

In order to achieve the above object, according to the present invention, an SRAM memory cell (CE shown in FIG. 2 is used.
The load circuit of the flip-flops (Q1, Q2) forming L11) has a pair of capacitors (C1) charged to a voltage corresponding to the power supply voltage (Vdd) instead of the high load resistance connected to the power supply circuit (Vdd). , C2) are used.

The paired capacitors (C1, C2) hold the circuit potential for maintaining the circuit operation state (information storage state) of the flip-flops (Q1, Q2), and directly hold the storage information of the memory cell. Not a thing. But,
The charge accumulated in the pair of capacitors (C1, C2) is discharged by a leak current or the like, and the flip-flops (Q1, Q2) are discharged.
When the drain voltage of 2) becomes lower than a certain level, the circuit operating state of the flip-flops (Q1, Q2) cannot be maintained, and the stored contents of the memory cells (CEL11 etc.) configured by the flip-flops disappear.

In order to prevent the memory contents of the memory cell from being lost, in the present invention, a pair of capacitors (C1, C2; a non-information holding medium) forming a load circuit is cycled for a certain period (T in FIG. 8).
Means for charging with R1 or TR2 (Q3, Q4; Q1
1 to Q42; DW10 + DR10) are provided. This charging means (Q3, Q4; Q11 to Q42; DW10 + D
Since the cyclic charging operation of the pair of capacitors (C1, C2) by R10) is similar to the refresh operation in the DRAM, the SRAM of the present invention is referred to as a dynamic SRAM in this specification.

However, while the normal DRAM refresh is an operation of "precharging for each corresponding bit line, then reading the current memory cell storage contents and writing back the read contents", the dynamic of the present invention SR
The AM refresh is an operation of "not reading the current stored contents, precharging the bit line for refreshing, but simply intermittently charging the load capacitor for maintaining the state of the flip-flop circuit". , The pair capacitor C1 and C2 of the present invention is S
It can be said that it is a switched capacitor for a load circuit instead of the high load resistance of a RAM flip-flop). This point is essentially different from a normal DRAM.

Therefore, the refresh of the present invention can be collectively executed for a plurality of memory cells at an appropriate timing (a period without memory access) for a short time. Therefore, the refresh of the present invention reduces the read / write operation speed of the memory. It does not become a factor, and high speed performance comparable to a normal SRAM can be obtained.

The refresh of the present invention is based on SRA.
Since a long cycle intermittent operation is sufficient as long as the flip-flop circuit state in the M cell is maintained, the current consumption can be made sufficiently small.

[0016]

DETAILED DESCRIPTION OF THE INVENTION A dynamic SRAM according to an embodiment of the present invention will be described below with reference to the drawings. In order to avoid redundant description, common reference numerals are used for functionally common parts in a plurality of drawings.

FIG. 1 is a block diagram for explaining a schematic structure of a dynamic SRAM according to an embodiment of the present invention. Here, for the sake of clarity, 16 cells CEL11 among a large number of memory cells CELmn
Only the CEL 44 and its peripheral circuit blocks are shown.

In FIG. 1, bit line pairs BL1 / BL1 * to BL4 / BL4 * of the first to fourth columns are connected to sense amplifiers SA1 to SA4, respectively (the asterisk * attached to the reference numeral of the bit line). Refers to having the opposite logic level to the one without *).

Bit line pair BL1 / BL1 * in the first column
Are connected to the cells CEL11 to CEL41, and the bit lines BL2 / BL2 * in the second column are connected to the cells CEL12 to CEL12.
CEL42 is connected and bit line pair BL3 of the third column
The cells CEL13 to CEL43 are connected to / BL3 *, and the cells CEL14 to CEL44 are connected to the bit line pair BL4 / BL4 * in the fourth column.

The cells CEL11 to CEL14 are connected to the first word line WL1, the cells CEL21 to CEL24 are connected to the second word line WL2, and the cells CEL31 to CEL are connected.
The third word line WL3 is connected to EL34, and the cell CE
The fourth word line WL4 is connected to L41 to CEL44.

The word lines W1 to W4 are word line decoders D
The sense amplifiers SA1 to SA4 are connected to W10 and are connected to the bit line decoder DB10.

Further, the bit line pair BL1 / of the first column
BL1 * is connected to the power supply line Vdd via the first column refresh transistor pair Q11, Q12, respectively. Similarly, bit line pairs BL2 / BL2 * to BL4 / B
L4 * is a refresh transistor pair Q2
It is connected to the power supply line Vdd through 1 to Q42.

The refresh line RE0 is connected to a refresh pulse generating circuit or a refresh decoder (not shown) (described later with reference to FIGS. 6 to 9).

Each refresh transistor pair (Q11 /
Voltage fluctuation absorbing capacitors Css of about 100 fF to 10 pF are connected to connection points between Q12 to Q41 / Q42) and the power supply line Vdd, respectively. The sum of the capacitor Css and the capacitance of each bit line pair (BL1 / BL1 *, etc.) itself hangs on the bit line pair (BL1 / BL1 *, etc.) (CEL11-CEL4).
(1 etc.) is sufficiently large with respect to the total value of the internal capacitors C1 and C2 (10 fF or less per cell), the voltage fluctuation of the power supply line Vdd due to the refresh of the internal capacitors C1 and C2 of these memory cell groups is suppressed. be able to.

FIG. 2 shows an example of the internal structure of each cell of FIG. 1 for the cell CEL11 (the same applies to the structures of other cells). That is, the sources (lightly doped drain LDD structure) of the Nch transistors Q1 and Q2 are connected to the ground line Vss. The polysilicon gate of the transistor Q1 is connected to the drain (lightly-doped drain LDD structure) of the transistor Q2 via the wiring L1. Similarly, the polysilicon gate of the transistor Q2 is
2 to the drain of the transistor Q1 (lightly-doped drain LDD structure). The flip-flop circuit (Q1 + Q2) whose gates are cross-connected (cross-coupled) in this way is used in the information storage unit (SR) of the cell CEL11.
AM cell structure).

This flip-flop circuit (Q1 + Q2)
Has a pair of output nodes that output the stored contents whose logic levels are opposite to each other. One output node is connected to the source (or drain) of the Nch (or Pch) transistor Q3 via the wiring region (diffusion layer) AR1. The drain (or source) of the transistor Q3 is
It is connected to one of the bit line pairs BL1 / BL1 * BL1.

Similarly, a flip-flop circuit (Q1 + Q
The other output node of 2) is the wiring region (diffusion layer) AR2.
Is connected to the source (or drain) of the Nch (or Pch) transistor Q4. The drain (or source) of the transistor Q4 is connected to the other BL1 * of the bit line pair (metal wiring layer) BL1 / BL1 *. The polysilicon gates of transistors Q3 and Q4 are connected to word line (polysilicon layer) WL1.

A drain capacitor C1 is provided between the wiring region AR1 (the drain output of the transistor Q1) and the ground line Vss, and a drain capacitor C1 is provided between the wiring region AR2 (the drain output of the transistor Q2) and the ground line Vss. C2 is provided.

The capacitor C1 or C2 is charged by the voltage (approximately Vdd) of the bit line BL1 / BL1 * at the moment when the transistors Q3 and Q4 are rendered conductive by the refresh pulse on the word line WL1. For example, when the transistor Q1 is off and the transistor Q2 is on, and the bit line voltage is +3 V, the capacitor C1 is changed according to the high level period of the refresh pulse and its repetition period.
Is charged to, for example, about +1 to + 2.5V. When the transistor Q2 is off and the transistor Q1 is on, the capacitor C2 has, for example, +1 to +1 depending on the high level period of the refresh pulse and its repetition period.
It is charged to about + 2.5V.

Turning on the transistors Q1 and Q2
In the off state (contents of SRAM cell CEL11), when both capacitors C1 and C2 are completely discharged,
Lost. In order to prevent the loss of the stored contents, the capacitors C1 and C2 are connected to the refresh pulse (PR1 of FIG. 8).
Etc.), the transistors Q3 and Q4 are intermittently turned on.
Via the bit line voltage Vdd. (The capacitors C1 and C2 can be considered as switched capacitors in view of the circuit operation of being intermittently charged by the transistor switch.) Furthermore, between the power supply line Vdd and the ground line Vss,
Total capacitance of capacitors C1 and C2 (eg 10f
A power supply voltage fluctuation absorbing capacitor Css (for example, about 100 fF to 10 pF) that is sufficiently larger than F) is connected. Since the relative large-capacity capacitor Css is constantly charged with the power supply voltage Vdd, the power supply voltage of the cell CEL11 does not drop drastically at the moment when the relative small-capacity capacitors C1 and C2 are refresh-charged.

FIG. 3 is a plan view exemplifying a deformed integrated circuit structure in the case where the transistors Q1 to Q4 of FIG. 2 are all formed of NchMOS transistors on a P substrate or P well.

For example, the cell formation region of the P substrate (3 to 4 μm)
N-type impurities (phosphorus, etc.) in an area of about mx 4-5 μm)
Are thermally diffused to form the drain and source regions of the transistors Q1 to Q4 (in this region, a small amount of P-type impurity such as boron is ion-implanted in advance, which becomes a lightly doped drain LDD region). . Simultaneously with the formation of the drain / source LDD regions, connection wiring regions (diffusion layers) AR1 and AR2 that connect the electrodes of the transistors Q1 to Q4 as shown in FIG. 2 and power supply lines (diffusion layer) Vdd. (Not shown) are formed.

After the diffusion layer is formed, the gate regions of the transistors Q1 to Q4 and the word line WL1 are formed of a polysilicon layer in one step through a silicon oxide layer (not shown).

After the polysilicon layer is formed, the metal wiring 1 of the ground line Vss is interposed via a silicon oxide layer (not shown).
Is formed. A part of this Vss metal wiring pattern is parallel to the connection wiring regions AR1 and AR2 and the Vdd diffusion layer via the silicon oxide layer. Then, a capacitor C1 having a silicon oxide layer as a dielectric is formed between the area AR1 and the Vss metal wiring, and a capacitor C2 having a silicon oxide layer as a dielectric is formed as the areas AR2 and V2.
It is formed between the ss metal wiring.

After the metal wiring layer 1 is formed, a bit line pair BLn / BLn * orthogonal to the word line WL1 is formed by the metal wiring 2 via a silicon oxide layer (not shown). In addition, a square mark in the drawing indicates a contact hole.

In the structure shown in FIG. 3, only one type of polysilicon (polysilicon layer having a relatively low resistance) may be used. Therefore, a conventional SRAM using two types of polysilicon (one type for low resistance wiring and another type for polysilicon) is used. Seeds are less expensive to manufacture than high resistance flip-flop load resistors). Further, since the polysilicon high resistance having a large temperature change is not used, it is possible to obtain a flip-flop memory cell having excellent temperature stability in the storage state.

In FIG. 4, the transistors Q1 and Q2 in FIG. 2 are N-channel MOS transistors on the P substrate or P well, and the transistors Q3 and Q4 are Pc in the N well.
It is a top view which deforms and exemplifies the integrated circuit structure when it comprises an hMOS transistor.

FIG. 4 shows the Nch transistor Q3 of FIG.
Pch transistors Q3 and Q in which Q4 is housed in the N well
4 and the other structure is the same as that of FIG.

In the embodiment of FIG. 3 or 4, the capacitors C1 and C2 have a parallel plate capacitor structure using silicon oxide as a dielectric. However, these capacitors may be ferroelectric capacitors or PN junction capacitors as long as the required capacitance can be obtained and the leakage current can be reduced to a level that poses no practical problem.

FIG. 5 is a block diagram for explaining the schematic structure of the dynamic SRAM according to the second embodiment of the present invention. The configuration of FIG. 5 has a sense amplifier group SAn.
The configuration is the same as that of FIG. 1 except that the arrangement of the bit line decoder DB10 is changed.

FIG. 6 is a block diagram for explaining a schematic structure of a dynamic SRAM according to the third embodiment of the present invention. The configuration of FIG. 6 has a refresh pulse (refresh line RE1) applied to the gate of each refresh transistor pair (Q11 / Q12 to Q41 / Q42).
~ PR4 on PR4; see FIG. 9) are the same as the configuration of FIG. 1 except that they are independent of each other. These refresh pulses are applied to the refresh decoder DR.
Generated by 10.

FIG. 7 is a block diagram for explaining the schematic structure of a dynamic SRAM according to the fourth embodiment of the present invention. The configuration of FIG. 7 has a sense amplifier group SAn.
The configuration is the same as that of FIG. 6 except that the arrangement of the bit line decoder DB10 is changed.

FIG. 8 shows the refresh line drive voltage VRE0 (refresh pulse) when the capacitors C1 and C2 in all the cells of the memory cell matrix of FIG. 1 or FIG. 5 are collectively (simultaneously) refreshed (intermittently charged). It is a timing chart figure explaining whether it should generate in this way.

For example, the pulse PW1 of the word line drive voltage VWL is applied to the word line WL1 (time t01), the data is written to the cell CEL11 (or the data is read), and then the refresh line RE0.
The pulse PR1 of the refresh line drive voltage VRE0 is applied to the (at time t03). Then, the transistor Q11
.About.Q42 are simultaneously turned on, and the bit line select transistors Q3 and Q4 of the cell CEL11 are turned on.

If the contents stored in the cell at that time are the transistor Q1 off and the transistor Q2 on, the capacitor C1 has the potential of the bit lines BL1 / BL1 * (approximately Vdd).
It is charged (refreshed) to the side, and the circuit state of transistor Q1 off and transistor Q2 on is guaranteed.

If the contents stored in the cell at that time are the transistor Q2 off and the transistor Q1 on, the capacitor C2 has the potential of the bit lines BL1 / BL1 * (approximately Vdd).
It is charged (refreshed) to the side, and the circuit state of transistor Q2 off and transistor Q1 on is guaranteed.

After refreshing the capacitors C1 and C2, the pulse PW2 of the word line drive voltage VWL is applied to the word line WL1 again (time t05), and the cell CEL11.
Data is written (or data is read) to the data. After that, when the pulse PR2 of the refresh line drive voltage VRE is applied to the refresh line RE1, the transistors Q11 to Q42 and Q3 and Q4 are simultaneously turned on, and the capacitors C1 and C2 are refreshed again.

In this way, the memory access (PW1 to PW1
By refreshing during the interval (when W3 is generated) (when PW1 to PW3 is not generated), the storage state of SRAM cells (circuit state of flip-flops) is dynamically maintained without damaging the reading speed of SRAM. Will be done.

In the above example (upper part of FIG. 8), the word line drive pulses (PW1 to PW3) and the refresh pulse (PR
1 to PR3) have the same cycle and a phase shift, but the capacitors C1 and C2 in FIG. 2 can be refreshed at other timings. That is, as long as the stored contents of the cell can be maintained, the refresh pulse (PR
1 to PR3) is set to a multiple of the period (TW2) of the word line drive pulses (PW1 to PW3),
The number of refreshes may be relatively reduced. If the refresh times of the capacitors C1 and C2 are reduced, the power consumption current of the cell is correspondingly reduced (the power supply current decrease per cell is small, but when the cells are collected for several tens of megabytes or more, the power supply current decrease is reduced. The amount is not stupid).

The refresh drive voltage VRE shown in FIG.
The waveform of 0 is shown when the transistors Q11 to Q42 are enhancement type. If transistor Q11
When -Q42 is configured as a depletion type, the potential level of the refresh drive voltage VRE0 is shifted in parallel (in the case of an Nch transistor, to the negative potential side) so that the transistors Q11 to Q42 are turned off during the period when there is no memory access or refresh. There is a need.

FIG. 9 shows refresh line drive voltages VRE1 to VRE4 (refresh pulse) when the capacitors C1 and C2 in all cells of the memory cell matrix of FIG. 6 or 7 are collectively (simultaneously) refreshed (intermittently charged). FIG. 9 is a timing chart diagram for explaining another example of how to generate?

In the example of FIG. 8, a plurality of cells are refreshed simultaneously in units of a plurality of word lines, but in FIG. 9, the refresh timing is shifted by one pulse for each word line. In the method of FIG. 9, the number of refresh operations performed in a unit time is smaller than that of the case of FIG. 8 when viewed from the whole memory, so that the cell current can be further reduced. Moreover, since the refresh timing is shifted for each word line, the magnitude of the power supply voltage fluctuation (or the ground line potential fluctuation) accompanying the refresh can be further reduced.

[0053]

According to the present invention, the flip-flop (Q) which constitutes the memory cell (CEL 11 in FIG. 2) of the SRAM.
1, Q2) is charged to the bit line voltage corresponding to the power supply voltage (Vdd) instead of the high load resistance 1
A pair of capacitors (C1, C2) is used. This capacitor can be formed around the flip-flop circuit using, for example, a silicon oxide film as a dielectric and a semiconductor diffusion layer or a metal wiring layer as an electrode. The temperature coefficient of such a capacitor can be reduced by one digit from the temperature coefficient of high resistance polysilicon. Therefore, it is possible to obtain a memory in which increase in current consumption and occurrence of error are unlikely to occur with respect to temperature changes.

Further, unlike the ordinary DRAM which requires the bit line precharge at the time of reading the stored information, the present invention does not require such bit line precharge, and the load circuit capacitors (C1, C2) can be used to store various memories. It does not read the contents and write them back. Therefore, the common bit lines (for example, BL1 and BL1 *) are used for a moment without memory access (for example, t03 to t04 in FIG. 8).
It is possible to perform batch refresh (simultaneous charging of C1 and C2) on the load circuit capacitors (a large number of capacitor pairs C1 + C2) of all the cells above. Therefore, in the present invention,
Refreshing does not slow down the information reading operation (memory access).

Further, as long as the circuit state (on / off state) of the flip-flop can be maintained, the charging voltage of the load circuit capacitors (C1, C2) may be in an arbitrary range to some extent. Therefore, if the charge voltage of the load circuit capacitors (C1, C2) immediately after refreshing is set sufficiently high, no error occurs even if refreshing (charging / discharging) is not performed as frequently as in a normal DRAM that stores information in the cell capacitors. . Therefore, the refresh cycle can be made longer than that of the DRAM of the same scale, and the current consumption due to the refresh can be reduced (the current consumption per cell can be 1 nanoampere or less).

Further, since the formation of the high resistance polysilicon layer (load resistance of the flip-flop), which requires a separate step, is not necessary, the polysilicon forming step in the memory cell manufacturing is the gate polysilicon forming of the MOS transistor. Only one step is required. Therefore, the integrated circuit of the dynamic SRAM of the present invention can be manufactured with a small number of masks.

[Brief description of the drawings]

FIG. 1 is a dynamic S according to an embodiment of the present invention.
FIG. 3 is a block diagram for explaining a schematic configuration of a RAM.

FIG. 2 is a circuit diagram illustrating an internal configuration of each cell in FIG.

FIG. 3 is a plan view showing a deformed example of an integrated circuit structure in the case where transistors Q1 to Q4 of FIG. 2 are all formed of NchMOS transistors on a P substrate or P well.

FIG. 4 is a deformation of an integrated circuit structure in which the transistors Q1 and Q2 of FIG. 2 are composed of NchMOS transistors in a P substrate or a P well, and the transistors Q3 and Q4 are composed of PchMOS transistors in an N well. The top view which illustrates.

FIG. 5 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a second embodiment of the present invention.

FIG. 6 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a third embodiment of the present invention.

FIG. 7 is a block diagram for explaining a schematic configuration of a dynamic SRAM according to a fourth embodiment of the present invention.

FIG. 8 shows how to generate a refresh line drive voltage VRE (refresh pulse) when collectively (simultaneously) refreshing (intermittent charging) capacitors C1 and C2 in all cells of a memory cell matrix. The timing chart figure explaining.

FIG. 9 shows how to generate a refresh line drive voltage VRE (refresh pulse) when collectively (simultaneously) refreshing (intermittently charging) capacitors C1 and C2 in all cells of a memory cell matrix. The timing chart figure explaining other examples.

[Description of Codes] CELmn ... Memory cell; DW10 ... Word line decoder; DB10 ... Bit line decoder; DR10 ... Refresh decoder; SAn ... Sense amplifier; WLm ... Word line; REm ... Refresh line; BLn / BLn * ... Bit line pair Q1, Q2 ... Nch flip-flop transistor pair (information storage unit); Q3, Q4 ... Nch (or P
ch) transistor (bit line connecting means); Q11 to Q
42 ... Refresh transistor pair (for refresh charging of C1 and C2); C1, C2 ... Drain capacitor (capacitor part); Css ... Power supply voltage fluctuation absorbing capacitor; Vss ... Ground line; Vdd ... Power supply line; AR1, A
R2 ... Connection wiring region (diffusion layer); VWL ... Word line drive voltage; VRE ... Refresh line drive voltage; TW1 to TW
3 ... 1st period; TR1-TR3 ... 2nd period.

Claims (8)

[Claims] 1. A memory device having a matrix structure in which a plurality of memory cells are arranged at intersections of a plurality of pairs of bit lines and a plurality of word lines, wherein each of the memory cells is formed, and is opposite to each other. A flip-flop circuit having a pair of output nodes for outputting storage contents having a logic level of; and a flip-flop to the pair of bit lines by selectively conducting in accordance with a signal level of the word line. Bit line connecting means for respectively connecting a pair of output nodes of the circuit; a capacitor section for applying a circuit operating voltage of a predetermined value or more to the flip-flop circuit so that the stored contents of the memory cell are held; In order that the circuit operating voltage is maintained at the predetermined value or higher, the bit line connecting means is temporarily turned on in a predetermined cycle, and the pair of the pair of electrodes are at substantially the same potential. A dynamic SRA, comprising: intermittent charging means for intermittently charging the capacitor section using a bit line;
M. 2. The intermittent charging means is provided with a second cycle having a length equal to or longer than the first cycle by excluding a period of intermittently bringing the bit line connecting means into a conductive state in the first cycle. The dynamic SRAM according to claim 1, wherein the dynamic SRAM is configured to be charged. 3. The intermittent operation of the bit line connecting means in the first cycle is removed, and the intermittent operation of a plurality of the memory cells is performed in a second cycle having a length longer than the first cycle. 2. The dynamic SRAM according to claim 1, wherein the charging means is configured to sequentially charge the capacitor section at different timings. 4. A capacitor, which is connected between a pair of power supply lines for each pair of bit lines and has a capacitance larger than that of the capacitor portion, according to claim 1. The described dynamic SRAM. 5. A MOS transistor pair forming a flip-flop; a capacitor section for applying an operating voltage to the drain circuit of each of the flip-flop MOS transistor pair; and a capacitor section for controlling the capacitor section by a potential of a bit line pair at a predetermined cycle. A bit line connecting MOS transistor pair to be charged; and a gate portion of the flip-flop MOS transistor pair and a gate portion of the bit line connecting MOS transistor pair are formed of polysilicon in the same step. A memory structure characterized by: 6. The memory structure according to claim 5, wherein the capacitor portion is composed of a capacitor formed between the drain diffusion layer of the flip-flop MOS transistor pair and the ground wiring. 7. A drain circuit of each of the flip-flop MOS transistor pairs is selectively connected to the bit line pair, and a MOS transistor gate portion of the same conductivity type as the flip-flop MOS transistor pair is further provided. The memory structure according to claim 5, wherein: 8. A drain circuit of each of the flip-flop MOS transistor pairs is selectively connected to the bit line pair, and a MOS transistor gate portion of a conductivity type different from that of the flip-flop MOS transistor pair is further provided. The memory structure according to claim 5, wherein: